diff options
Diffstat (limited to 'ports/cortex_r5/ac5/src')
8 files changed, 121 insertions, 27 deletions
diff --git a/ports/cortex_r5/ac5/src/tx_port_offset_check.c b/ports/cortex_r5/ac5/src/tx_port_offset_check.c new file mode 100644 index 00000000..11eaa253 --- /dev/null +++ b/ports/cortex_r5/ac5/src/tx_port_offset_check.c @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (c) 2026 Eclipse ThreadX contributors + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * AI Disclosure: This file was largely AI-generated by Copilot (Opus 5). + * The AI-generated portions may be considered public domain (CC0-1.0) + * and not subject to the project's licence. The human contributor has + * reviewed and verified that the code is correct. + * + * SPDX-License-Identifier: MIT and CC0-1.0 + **************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port_offset_check.c Cortex-R5/AC5 */ +/* */ +/* DESCRIPTION */ +/* */ +/* Compile-time verification of the TX_THREAD structure offsets that */ +/* this port's assembly reaches by hard-coded displacement. The file */ +/* emits no code; it exists purely so that a layout change becomes a */ +/* build failure. */ +/* */ +/* Why this is needed: tx_thread_schedule.s, */ +/* tx_thread_system_return.s and tx_thread_context_restore.s read and */ +/* write the per-thread VFP enable flag as [thread, #144]. Nothing in */ +/* the toolchain connects that literal to the C structure, so adding a */ +/* member, enabling an option that adds one, or reordering the port */ +/* extensions would silently retarget those accesses at an unrelated */ +/* field -- corrupting thread state in a way that is extremely hard to */ +/* diagnose from the symptom. The offset was measured at 144 for the */ +/* default build and is asserted here. */ +/* */ +/* NOTE: this port has no CMake build of its own, so this file takes */ +/* effect only in builds that compile everything under src/. It is */ +/* still worthwhile: it emits no code, costs nothing, and protects every */ +/* build that does pick it up. */ +/* */ +/* A negative array dimension is used rather than _Static_assert */ +/* because this project targets C99, where _Static_assert does not */ +/* exist. If an assertion below fails, the compiler reports a negative */ +/* or zero-sized array for the named typedef. */ +/* */ +/**************************************************************************/ + +#include "tx_api.h" +#include <stddef.h> + +/* Offset of the VFP enable flag as encoded in this port's assembly. + Overridable only so that the assertion itself can be tested. */ + +#ifndef TX_PORT_VFP_ENABLE_OFFSET +#define TX_PORT_VFP_ENABLE_OFFSET 144 +#endif + +typedef char +tx_port_assert_vfp_enable_offset_is_144[ + (offsetof(TX_THREAD, tx_thread_vfp_enable) == TX_PORT_VFP_ENABLE_OFFSET) + ? 1 : -1]; + +/* The stack pointer is read as [thread, #8] by tx_thread_schedule.S and + written by tx_thread_system_return.s, and the run counter as + [thread, #4]. Assert those too, since they are on the context-switch + critical path. */ + +typedef char +tx_port_assert_stack_ptr_offset_is_8[ + (offsetof(TX_THREAD, tx_thread_stack_ptr) == 8) ? 1 : -1]; + +typedef char +tx_port_assert_run_count_offset_is_4[ + (offsetof(TX_THREAD, tx_thread_run_count) == 4) ? 1 : -1]; diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s index 1d070d89..0063a523 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -47,7 +49,7 @@ SVC_MODE EQU 0x93 ; SVC mode IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IMPORT _tx_thread_preempt_disable - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_isr_exit ENDIF ; @@ -101,7 +103,7 @@ _tx_thread_context_restore CPSID i ; Disable IRQ interrupts ENDIF - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR exit function to indicate an ISR is complete. */ ; @@ -245,4 +247,3 @@ __tx_thread_idle_system_restore ;} ; END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_context_save.s index 043fbdeb..05961bf7 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -32,7 +34,7 @@ IMPORT _tx_thread_system_state IMPORT _tx_thread_current_ptr IMPORT __tx_irq_processing_return - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_isr_enter ENDIF ; @@ -109,7 +111,7 @@ _tx_thread_context_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -149,7 +151,7 @@ __tx_thread_not_nested_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -173,7 +175,7 @@ __tx_thread_idle_system_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -189,4 +191,3 @@ __tx_thread_idle_system_save ;} ; END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s index f58456b9..3f5ae682 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -43,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IMPORT _tx_thread_preempt_disable - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_isr_exit ENDIF ; @@ -93,7 +95,7 @@ _tx_thread_fiq_context_restore ; CPSID if ; Disable IRQ and FIQ interrupts - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR exit function to indicate an ISR is complete. */ ; @@ -235,4 +237,3 @@ __tx_thread_fiq_idle_system_restore ;} ; END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s index 67bc6290..eb8f4e2e 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -32,7 +34,7 @@ IMPORT _tx_thread_system_state IMPORT _tx_thread_current_ptr IMPORT __tx_fiq_processing_return - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_isr_enter ENDIF ; @@ -106,7 +108,7 @@ _tx_thread_fiq_context_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -150,7 +152,7 @@ __tx_thread_fiq_not_nested_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -169,7 +171,7 @@ __tx_thread_fiq_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -193,4 +195,3 @@ __tx_thread_fiq_idle_system_save ;} ; END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_schedule.s b/ports/cortex_r5/ac5/src/tx_thread_schedule.s index b50d0614..47bdc971 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_r5/ac5/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -33,7 +35,7 @@ IMPORT _tx_thread_execute_ptr IMPORT _tx_thread_current_ptr IMPORT _tx_timer_time_slice - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_thread_enter ENDIF ; @@ -136,7 +138,7 @@ __tx_thread_schedule_loop ; /* Switch to the thread's stack. */ ; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; ; - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the thread entry function to indicate the thread is executing. */ ; @@ -223,4 +225,3 @@ __tx_no_thread_to_disable ENDIF END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_system_return.s b/ports/cortex_r5/ac5/src/tx_thread_system_return.s index ac35c95f..5680174b 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_r5/ac5/src/tx_thread_system_return.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -32,7 +34,7 @@ IMPORT _tx_thread_current_ptr IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_thread_exit ENDIF ; @@ -106,7 +108,7 @@ _tx_skip_solicited_vfp_save STMDB sp!, {r0-r1} ; Save type and CPSR ; ; - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -148,4 +150,3 @@ __tx_thread_dont_save_ts ; ;} END - diff --git a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s index b1918801..02394cb5 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation +; * Copyright (c) 2026 Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -7,6 +8,7 @@ ; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ +; Portions of this file were generated with AI assistance. ; ; ;/**************************************************************************/ @@ -31,7 +33,7 @@ ; IMPORT _tx_thread_system_state IMPORT _tx_thread_current_ptr - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE IMPORT _tx_execution_isr_enter ENDIF ; @@ -102,7 +104,7 @@ _tx_thread_vectored_context_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -142,7 +144,7 @@ __tx_thread_not_nested_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -170,7 +172,7 @@ __tx_thread_idle_system_save ; MOV r10, #0 ; Clear stack limit - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY :LOR: :DEF:TX_EXECUTION_PROFILE_ENABLE ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; @@ -190,4 +192,3 @@ __tx_thread_idle_system_save ;} ; END - |