diff options
Diffstat (limited to 'ports/risc-v64/gnu/src/tx_thread_context_save.S')
| -rw-r--r-- | ports/risc-v64/gnu/src/tx_thread_context_save.S | 85 |
1 files changed, 84 insertions, 1 deletions
diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index df6f2c9a..7935bfee 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -94,7 +94,11 @@ _tx_thread_context_save: sd t4, 15*8(sp) // Store t4 sd t5, 14*8(sp) // Store t5 sd t6, 13*8(sp) // Store t6 +#ifdef TX_RISCV_SMODE + csrr t0, sepc // Load exception program counter +#else csrr t0, mepc // Load exception program counter +#endif sd t0, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ @@ -146,6 +150,36 @@ _tx_thread_context_save: sd t0, 63*8(sp) // Store fcsr #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_isr_enter // Call the ISR execution enter function #endif @@ -184,7 +218,11 @@ _tx_thread_not_nested_save: sd t5, 14*8(sp) // Store t5 sd t6, 13*8(sp) // Store t6 +#ifdef TX_RISCV_SMODE + csrr t1, sepc // Load exception program counter +#else csrr t1, mepc // Load exception program counter +#endif sd t1, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ @@ -236,6 +274,36 @@ _tx_thread_not_nested_save: sd t0, 63*8(sp) // Store fcsr #endif +#if defined(__riscv_vector) + /* Store vector registers and CSRs */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t1, sp, 64*8 +#else + addi t1, sp, 31*8 +#endif + /* Store vector CSRs */ + csrr t2, vstart // Store vstart + sd t2, 0*8(t1) + csrr t2, vtype // Store vtype + sd t2, 1*8(t1) + csrr t2, vl // Store vl + sd t2, 2*8(t1) + csrr t2, vcsr // Store vcsr + sd t2, 3*8(t1) + + /* Store vector registers v0-v31 */ + addi t2, t1, 4*8 + vsetvli t3, zero, e8, m8, ta, ma + vse8.v v0, 0(t2) // Store v0 ~ v7 + add t2, t2, t3 + vse8.v v8, 0(t2) // Store v8 ~ v15 + add t2, t2, t3 + vse8.v v16, 0(t2) // Store v16 ~ v23 + add t2, t2, t3 + vse8.v v24, 0(t2) // Store v24 ~ v31 + add t2, t2, t3 +#endif + /* Save the current stack pointer in the thread's control block. */ /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ @@ -244,7 +312,7 @@ _tx_thread_not_nested_save: la t1, _tx_thread_current_ptr // Pickup current thread pointer address ld t1, 0(t1) // Pickup current thread pointer - sd sp, 16(t1) // Save stack pointer + sd sp, 8(t1) // Save stack pointer #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY /* _tx_execution_isr_enter is called with thread stack pointer */ @@ -275,4 +343,19 @@ _tx_thread_idle_system_save: #else addi sp, sp, 32*8 // Recover the reserved stack space #endif + +#if defined(__riscv_vector) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, sp, -65*8 +#else + addi t0, sp, -32*8 +#endif + csrr t1, vlenb // Get vector register byte length + slli t1, t1, 5 // Multiply by 32 (number of vector registers) + addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr + add sp, sp, t1 // Recover vector stack frame + + ld t1, 18*8(t0) // Recover t1 + ld t0, 19*8(t0) // Recover t0 +#endif ret // Return to calling ISR |