diff options
Diffstat (limited to 'ports')
92 files changed, 2557 insertions, 1702 deletions
diff --git a/ports/c667x/ccs/example_build/tx/Release/makefile b/ports/c667x/ccs/example_build/tx/Release/makefile new file mode 100644 index 00000000..45d27b35 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/makefile @@ -0,0 +1,351 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +CG_TOOL_ROOT := C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4 + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./tx_block_allocate.obj" \ +"./tx_block_pool_cleanup.obj" \ +"./tx_block_pool_create.obj" \ +"./tx_block_pool_delete.obj" \ +"./tx_block_pool_info_get.obj" \ +"./tx_block_pool_initialize.obj" \ +"./tx_block_pool_performance_info_get.obj" \ +"./tx_block_pool_performance_system_info_get.obj" \ +"./tx_block_pool_prioritize.obj" \ +"./tx_block_release.obj" \ +"./tx_byte_allocate.obj" \ +"./tx_byte_pool_cleanup.obj" \ +"./tx_byte_pool_create.obj" \ +"./tx_byte_pool_delete.obj" \ +"./tx_byte_pool_info_get.obj" \ +"./tx_byte_pool_initialize.obj" \ +"./tx_byte_pool_performance_info_get.obj" \ +"./tx_byte_pool_performance_system_info_get.obj" \ +"./tx_byte_pool_prioritize.obj" \ +"./tx_byte_pool_search.obj" \ +"./tx_byte_release.obj" \ +"./tx_event_flags_cleanup.obj" \ +"./tx_event_flags_create.obj" \ +"./tx_event_flags_delete.obj" \ +"./tx_event_flags_get.obj" \ +"./tx_event_flags_info_get.obj" \ +"./tx_event_flags_initialize.obj" \ +"./tx_event_flags_performance_info_get.obj" \ +"./tx_event_flags_performance_system_info_get.obj" \ +"./tx_event_flags_set.obj" \ +"./tx_event_flags_set_notify.obj" \ +"./tx_initialize_high_level.obj" \ +"./tx_initialize_kernel_enter.obj" \ +"./tx_initialize_kernel_setup.obj" \ +"./tx_mutex_cleanup.obj" \ +"./tx_mutex_create.obj" \ +"./tx_mutex_delete.obj" \ +"./tx_mutex_get.obj" \ +"./tx_mutex_info_get.obj" \ +"./tx_mutex_initialize.obj" \ +"./tx_mutex_performance_info_get.obj" \ +"./tx_mutex_performance_system_info_get.obj" \ +"./tx_mutex_prioritize.obj" \ +"./tx_mutex_priority_change.obj" \ +"./tx_mutex_put.obj" \ +"./tx_queue_cleanup.obj" \ +"./tx_queue_create.obj" \ +"./tx_queue_delete.obj" \ +"./tx_queue_flush.obj" \ +"./tx_queue_front_send.obj" \ +"./tx_queue_info_get.obj" \ +"./tx_queue_initialize.obj" \ +"./tx_queue_performance_info_get.obj" \ +"./tx_queue_performance_system_info_get.obj" \ +"./tx_queue_prioritize.obj" \ +"./tx_queue_receive.obj" \ +"./tx_queue_send.obj" \ +"./tx_queue_send_notify.obj" \ +"./tx_semaphore_ceiling_put.obj" \ +"./tx_semaphore_cleanup.obj" \ +"./tx_semaphore_create.obj" \ +"./tx_semaphore_delete.obj" \ +"./tx_semaphore_get.obj" \ +"./tx_semaphore_info_get.obj" \ +"./tx_semaphore_initialize.obj" \ +"./tx_semaphore_performance_info_get.obj" \ +"./tx_semaphore_performance_system_info_get.obj" \ +"./tx_semaphore_prioritize.obj" \ +"./tx_semaphore_put.obj" \ +"./tx_semaphore_put_notify.obj" \ +"./tx_thread_context_restore.obj" \ +"./tx_thread_context_save.obj" \ +"./tx_thread_create.obj" \ +"./tx_thread_delete.obj" \ +"./tx_thread_entry_exit_notify.obj" \ +"./tx_thread_identify.obj" \ +"./tx_thread_info_get.obj" \ +"./tx_thread_initialize.obj" \ +"./tx_thread_interrupt_control.obj" \ +"./tx_thread_performance_info_get.obj" \ +"./tx_thread_performance_system_info_get.obj" \ +"./tx_thread_preemption_change.obj" \ +"./tx_thread_priority_change.obj" \ +"./tx_thread_relinquish.obj" \ +"./tx_thread_reset.obj" \ +"./tx_thread_resume.obj" \ +"./tx_thread_schedule.obj" \ +"./tx_thread_shell_entry.obj" \ +"./tx_thread_sleep.obj" \ +"./tx_thread_stack_analyze.obj" \ +"./tx_thread_stack_build.obj" \ +"./tx_thread_stack_error_handler.obj" \ +"./tx_thread_stack_error_notify.obj" \ +"./tx_thread_suspend.obj" \ +"./tx_thread_system_preempt_check.obj" \ +"./tx_thread_system_resume.obj" \ +"./tx_thread_system_return.obj" \ +"./tx_thread_system_suspend.obj" \ +"./tx_thread_terminate.obj" \ +"./tx_thread_time_slice.obj" \ +"./tx_thread_time_slice_change.obj" \ +"./tx_thread_timeout.obj" \ +"./tx_thread_wait_abort.obj" \ +"./tx_time_get.obj" \ +"./tx_time_set.obj" \ +"./tx_timer_activate.obj" \ +"./tx_timer_change.obj" \ +"./tx_timer_create.obj" \ +"./tx_timer_deactivate.obj" \ +"./tx_timer_delete.obj" \ +"./tx_timer_expiration_process.obj" \ +"./tx_timer_info_get.obj" \ +"./tx_timer_initialize.obj" \ +"./tx_timer_interrupt.obj" \ +"./tx_timer_performance_info_get.obj" \ +"./tx_timer_performance_system_info_get.obj" \ +"./tx_timer_system_activate.obj" \ +"./tx_timer_system_deactivate.obj" \ +"./tx_timer_thread_entry.obj" \ +"./tx_trace_buffer_full_notify.obj" \ +"./tx_trace_disable.obj" \ +"./tx_trace_enable.obj" \ +"./tx_trace_event_filter.obj" \ +"./tx_trace_event_unfilter.obj" \ +"./tx_trace_initialize.obj" \ +"./tx_trace_interrupt_control.obj" \ +"./tx_trace_isr_enter_insert.obj" \ +"./tx_trace_isr_exit_insert.obj" \ +"./tx_trace_object_register.obj" \ +"./tx_trace_object_unregister.obj" \ +"./tx_trace_user_event_insert.obj" \ +"./txe_block_allocate.obj" \ +"./txe_block_pool_create.obj" \ +"./txe_block_pool_delete.obj" \ +"./txe_block_pool_info_get.obj" \ +"./txe_block_pool_prioritize.obj" \ +"./txe_block_release.obj" \ +"./txe_byte_allocate.obj" \ +"./txe_byte_pool_create.obj" \ +"./txe_byte_pool_delete.obj" \ +"./txe_byte_pool_info_get.obj" \ +"./txe_byte_pool_prioritize.obj" \ +"./txe_byte_release.obj" \ +"./txe_event_flags_create.obj" \ +"./txe_event_flags_delete.obj" \ +"./txe_event_flags_get.obj" \ +"./txe_event_flags_info_get.obj" \ +"./txe_event_flags_set.obj" \ +"./txe_event_flags_set_notify.obj" \ +"./txe_mutex_create.obj" \ +"./txe_mutex_delete.obj" \ +"./txe_mutex_get.obj" \ +"./txe_mutex_info_get.obj" \ +"./txe_mutex_prioritize.obj" \ +"./txe_mutex_put.obj" \ +"./txe_queue_create.obj" \ +"./txe_queue_delete.obj" \ +"./txe_queue_flush.obj" \ +"./txe_queue_front_send.obj" \ +"./txe_queue_info_get.obj" \ +"./txe_queue_prioritize.obj" \ +"./txe_queue_receive.obj" \ +"./txe_queue_send.obj" \ +"./txe_queue_send_notify.obj" \ +"./txe_semaphore_ceiling_put.obj" \ +"./txe_semaphore_create.obj" \ +"./txe_semaphore_delete.obj" \ +"./txe_semaphore_get.obj" \ +"./txe_semaphore_info_get.obj" \ +"./txe_semaphore_prioritize.obj" \ +"./txe_semaphore_put.obj" \ +"./txe_semaphore_put_notify.obj" \ +"./txe_thread_create.obj" \ +"./txe_thread_delete.obj" \ +"./txe_thread_entry_exit_notify.obj" \ +"./txe_thread_info_get.obj" \ +"./txe_thread_preemption_change.obj" \ +"./txe_thread_priority_change.obj" \ +"./txe_thread_relinquish.obj" \ +"./txe_thread_reset.obj" \ +"./txe_thread_resume.obj" \ +"./txe_thread_suspend.obj" \ +"./txe_thread_terminate.obj" \ +"./txe_thread_time_slice_change.obj" \ +"./txe_thread_wait_abort.obj" \ +"./txe_timer_activate.obj" \ +"./txe_timer_change.obj" \ +"./txe_timer_create.obj" \ +"./txe_timer_deactivate.obj" \ +"./txe_timer_delete.obj" \ +"./txe_timer_info_get.obj" \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +LIB_OUTPUTS += \ +tx.lib \ + +LIB_OUTPUTS__QUOTED += \ +"tx.lib" \ + + +# All Target +all: tx.lib + +# Tool invocations +tx.lib: $(OBJS) $(OBJ_SRCS) $(LIB_SRCS) +ifneq ($(strip $(ORDERED_OBJS)),) + @echo 'Building target: "$@"' + @echo 'Invoking: C6000 Archiver' + "C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/ar6x" r "tx.lib" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' +endif + +# Other Targets +clean: + -$(RM) $(LIB_OUTPUTS__QUOTED) + -$(RM) "tx_block_allocate.obj" "tx_block_pool_cleanup.obj" "tx_block_pool_create.obj" "tx_block_pool_delete.obj" "tx_block_pool_info_get.obj" "tx_block_pool_initialize.obj" "tx_block_pool_performance_info_get.obj" "tx_block_pool_performance_system_info_get.obj" "tx_block_pool_prioritize.obj" "tx_block_release.obj" "tx_byte_allocate.obj" "tx_byte_pool_cleanup.obj" "tx_byte_pool_create.obj" "tx_byte_pool_delete.obj" "tx_byte_pool_info_get.obj" "tx_byte_pool_initialize.obj" "tx_byte_pool_performance_info_get.obj" "tx_byte_pool_performance_system_info_get.obj" "tx_byte_pool_prioritize.obj" "tx_byte_pool_search.obj" "tx_byte_release.obj" "tx_event_flags_cleanup.obj" "tx_event_flags_create.obj" "tx_event_flags_delete.obj" "tx_event_flags_get.obj" "tx_event_flags_info_get.obj" "tx_event_flags_initialize.obj" "tx_event_flags_performance_info_get.obj" "tx_event_flags_performance_system_info_get.obj" "tx_event_flags_set.obj" "tx_event_flags_set_notify.obj" "tx_initialize_high_level.obj" "tx_initialize_kernel_enter.obj" + -$(RM) "tx_initialize_kernel_setup.obj" "tx_mutex_cleanup.obj" "tx_mutex_create.obj" "tx_mutex_delete.obj" "tx_mutex_get.obj" "tx_mutex_info_get.obj" "tx_mutex_initialize.obj" "tx_mutex_performance_info_get.obj" "tx_mutex_performance_system_info_get.obj" "tx_mutex_prioritize.obj" "tx_mutex_priority_change.obj" "tx_mutex_put.obj" "tx_queue_cleanup.obj" "tx_queue_create.obj" "tx_queue_delete.obj" "tx_queue_flush.obj" "tx_queue_front_send.obj" "tx_queue_info_get.obj" "tx_queue_initialize.obj" "tx_queue_performance_info_get.obj" "tx_queue_performance_system_info_get.obj" "tx_queue_prioritize.obj" "tx_queue_receive.obj" "tx_queue_send.obj" "tx_queue_send_notify.obj" "tx_semaphore_ceiling_put.obj" "tx_semaphore_cleanup.obj" "tx_semaphore_create.obj" "tx_semaphore_delete.obj" "tx_semaphore_get.obj" "tx_semaphore_info_get.obj" "tx_semaphore_initialize.obj" "tx_semaphore_performance_info_get.obj" "tx_semaphore_performance_system_info_get.obj" "tx_semaphore_prioritize.obj" "tx_semaphore_put.obj" "tx_semaphore_put_notify.obj" + -$(RM) "tx_thread_context_restore.obj" "tx_thread_context_save.obj" "tx_thread_create.obj" "tx_thread_delete.obj" "tx_thread_entry_exit_notify.obj" "tx_thread_identify.obj" "tx_thread_info_get.obj" "tx_thread_initialize.obj" "tx_thread_interrupt_control.obj" "tx_thread_performance_info_get.obj" "tx_thread_performance_system_info_get.obj" "tx_thread_preemption_change.obj" "tx_thread_priority_change.obj" "tx_thread_relinquish.obj" "tx_thread_reset.obj" "tx_thread_resume.obj" "tx_thread_schedule.obj" "tx_thread_shell_entry.obj" "tx_thread_sleep.obj" "tx_thread_stack_analyze.obj" "tx_thread_stack_build.obj" "tx_thread_stack_error_handler.obj" "tx_thread_stack_error_notify.obj" "tx_thread_suspend.obj" "tx_thread_system_preempt_check.obj" "tx_thread_system_resume.obj" "tx_thread_system_return.obj" "tx_thread_system_suspend.obj" "tx_thread_terminate.obj" "tx_thread_time_slice.obj" "tx_thread_time_slice_change.obj" "tx_thread_timeout.obj" "tx_thread_wait_abort.obj" "tx_time_get.obj" "tx_time_set.obj" + -$(RM) "tx_timer_activate.obj" "tx_timer_change.obj" "tx_timer_create.obj" "tx_timer_deactivate.obj" "tx_timer_delete.obj" "tx_timer_expiration_process.obj" "tx_timer_info_get.obj" "tx_timer_initialize.obj" "tx_timer_interrupt.obj" "tx_timer_performance_info_get.obj" "tx_timer_performance_system_info_get.obj" "tx_timer_system_activate.obj" "tx_timer_system_deactivate.obj" "tx_timer_thread_entry.obj" "tx_trace_buffer_full_notify.obj" "tx_trace_disable.obj" "tx_trace_enable.obj" "tx_trace_event_filter.obj" "tx_trace_event_unfilter.obj" "tx_trace_initialize.obj" "tx_trace_interrupt_control.obj" "tx_trace_isr_enter_insert.obj" "tx_trace_isr_exit_insert.obj" "tx_trace_object_register.obj" "tx_trace_object_unregister.obj" "tx_trace_user_event_insert.obj" "txe_block_allocate.obj" "txe_block_pool_create.obj" "txe_block_pool_delete.obj" "txe_block_pool_info_get.obj" "txe_block_pool_prioritize.obj" "txe_block_release.obj" "txe_byte_allocate.obj" "txe_byte_pool_create.obj" "txe_byte_pool_delete.obj" "txe_byte_pool_info_get.obj" + -$(RM) "txe_byte_pool_prioritize.obj" "txe_byte_release.obj" "txe_event_flags_create.obj" "txe_event_flags_delete.obj" "txe_event_flags_get.obj" "txe_event_flags_info_get.obj" "txe_event_flags_set.obj" "txe_event_flags_set_notify.obj" "txe_mutex_create.obj" "txe_mutex_delete.obj" "txe_mutex_get.obj" "txe_mutex_info_get.obj" "txe_mutex_prioritize.obj" "txe_mutex_put.obj" "txe_queue_create.obj" "txe_queue_delete.obj" "txe_queue_flush.obj" "txe_queue_front_send.obj" "txe_queue_info_get.obj" "txe_queue_prioritize.obj" "txe_queue_receive.obj" "txe_queue_send.obj" "txe_queue_send_notify.obj" "txe_semaphore_ceiling_put.obj" "txe_semaphore_create.obj" "txe_semaphore_delete.obj" "txe_semaphore_get.obj" "txe_semaphore_info_get.obj" "txe_semaphore_prioritize.obj" "txe_semaphore_put.obj" "txe_semaphore_put_notify.obj" "txe_thread_create.obj" "txe_thread_delete.obj" "txe_thread_entry_exit_notify.obj" "txe_thread_info_get.obj" "txe_thread_preemption_change.obj" "txe_thread_priority_change.obj" "txe_thread_relinquish.obj" + -$(RM) "txe_thread_reset.obj" "txe_thread_resume.obj" "txe_thread_suspend.obj" "txe_thread_terminate.obj" "txe_thread_time_slice_change.obj" "txe_thread_wait_abort.obj" "txe_timer_activate.obj" "txe_timer_change.obj" "txe_timer_create.obj" "txe_timer_deactivate.obj" "txe_timer_delete.obj" "txe_timer_info_get.obj" + -$(RM) "tx_block_allocate.d" "tx_block_pool_cleanup.d" "tx_block_pool_create.d" "tx_block_pool_delete.d" "tx_block_pool_info_get.d" "tx_block_pool_initialize.d" "tx_block_pool_performance_info_get.d" "tx_block_pool_performance_system_info_get.d" "tx_block_pool_prioritize.d" "tx_block_release.d" "tx_byte_allocate.d" "tx_byte_pool_cleanup.d" "tx_byte_pool_create.d" "tx_byte_pool_delete.d" "tx_byte_pool_info_get.d" "tx_byte_pool_initialize.d" "tx_byte_pool_performance_info_get.d" "tx_byte_pool_performance_system_info_get.d" "tx_byte_pool_prioritize.d" "tx_byte_pool_search.d" "tx_byte_release.d" "tx_event_flags_cleanup.d" "tx_event_flags_create.d" "tx_event_flags_delete.d" "tx_event_flags_get.d" "tx_event_flags_info_get.d" "tx_event_flags_initialize.d" "tx_event_flags_performance_info_get.d" "tx_event_flags_performance_system_info_get.d" "tx_event_flags_set.d" "tx_event_flags_set_notify.d" "tx_initialize_high_level.d" "tx_initialize_kernel_enter.d" "tx_initialize_kernel_setup.d" "tx_mutex_cleanup.d" + -$(RM) "tx_mutex_create.d" "tx_mutex_delete.d" "tx_mutex_get.d" "tx_mutex_info_get.d" "tx_mutex_initialize.d" "tx_mutex_performance_info_get.d" "tx_mutex_performance_system_info_get.d" "tx_mutex_prioritize.d" "tx_mutex_priority_change.d" "tx_mutex_put.d" "tx_queue_cleanup.d" "tx_queue_create.d" "tx_queue_delete.d" "tx_queue_flush.d" "tx_queue_front_send.d" "tx_queue_info_get.d" "tx_queue_initialize.d" "tx_queue_performance_info_get.d" "tx_queue_performance_system_info_get.d" "tx_queue_prioritize.d" "tx_queue_receive.d" "tx_queue_send.d" "tx_queue_send_notify.d" "tx_semaphore_ceiling_put.d" "tx_semaphore_cleanup.d" "tx_semaphore_create.d" "tx_semaphore_delete.d" "tx_semaphore_get.d" "tx_semaphore_info_get.d" "tx_semaphore_initialize.d" "tx_semaphore_performance_info_get.d" "tx_semaphore_performance_system_info_get.d" "tx_semaphore_prioritize.d" "tx_semaphore_put.d" "tx_semaphore_put_notify.d" "tx_thread_create.d" "tx_thread_delete.d" "tx_thread_entry_exit_notify.d" "tx_thread_identify.d" "tx_thread_info_get.d" + -$(RM) "tx_thread_initialize.d" "tx_thread_performance_info_get.d" "tx_thread_performance_system_info_get.d" "tx_thread_preemption_change.d" "tx_thread_priority_change.d" "tx_thread_relinquish.d" "tx_thread_reset.d" "tx_thread_resume.d" "tx_thread_shell_entry.d" "tx_thread_sleep.d" "tx_thread_stack_analyze.d" "tx_thread_stack_error_handler.d" "tx_thread_stack_error_notify.d" "tx_thread_suspend.d" "tx_thread_system_preempt_check.d" "tx_thread_system_resume.d" "tx_thread_system_suspend.d" "tx_thread_terminate.d" "tx_thread_time_slice.d" "tx_thread_time_slice_change.d" "tx_thread_timeout.d" "tx_thread_wait_abort.d" "tx_time_get.d" "tx_time_set.d" "tx_timer_activate.d" "tx_timer_change.d" "tx_timer_create.d" "tx_timer_deactivate.d" "tx_timer_delete.d" "tx_timer_expiration_process.d" "tx_timer_info_get.d" "tx_timer_initialize.d" "tx_timer_performance_info_get.d" "tx_timer_performance_system_info_get.d" "tx_timer_system_activate.d" "tx_timer_system_deactivate.d" "tx_timer_thread_entry.d" "tx_trace_buffer_full_notify.d" + -$(RM) "tx_trace_disable.d" "tx_trace_enable.d" "tx_trace_event_filter.d" "tx_trace_event_unfilter.d" "tx_trace_initialize.d" "tx_trace_interrupt_control.d" "tx_trace_isr_enter_insert.d" "tx_trace_isr_exit_insert.d" "tx_trace_object_register.d" "tx_trace_object_unregister.d" "tx_trace_user_event_insert.d" "txe_block_allocate.d" "txe_block_pool_create.d" "txe_block_pool_delete.d" "txe_block_pool_info_get.d" "txe_block_pool_prioritize.d" "txe_block_release.d" "txe_byte_allocate.d" "txe_byte_pool_create.d" "txe_byte_pool_delete.d" "txe_byte_pool_info_get.d" "txe_byte_pool_prioritize.d" "txe_byte_release.d" "txe_event_flags_create.d" "txe_event_flags_delete.d" "txe_event_flags_get.d" "txe_event_flags_info_get.d" "txe_event_flags_set.d" "txe_event_flags_set_notify.d" "txe_mutex_create.d" "txe_mutex_delete.d" "txe_mutex_get.d" "txe_mutex_info_get.d" "txe_mutex_prioritize.d" "txe_mutex_put.d" "txe_queue_create.d" "txe_queue_delete.d" "txe_queue_flush.d" "txe_queue_front_send.d" "txe_queue_info_get.d" + -$(RM) "txe_queue_prioritize.d" "txe_queue_receive.d" "txe_queue_send.d" "txe_queue_send_notify.d" "txe_semaphore_ceiling_put.d" "txe_semaphore_create.d" "txe_semaphore_delete.d" "txe_semaphore_get.d" "txe_semaphore_info_get.d" "txe_semaphore_prioritize.d" "txe_semaphore_put.d" "txe_semaphore_put_notify.d" "txe_thread_create.d" "txe_thread_delete.d" "txe_thread_entry_exit_notify.d" "txe_thread_info_get.d" "txe_thread_preemption_change.d" "txe_thread_priority_change.d" "txe_thread_relinquish.d" "txe_thread_reset.d" "txe_thread_resume.d" "txe_thread_suspend.d" "txe_thread_terminate.d" "txe_thread_time_slice_change.d" "txe_thread_wait_abort.d" "txe_timer_activate.d" "txe_timer_change.d" "txe_timer_create.d" "txe_timer_deactivate.d" "txe_timer_delete.d" "txe_timer_info_get.d" + -$(RM) "tx_thread_context_restore.d" "tx_thread_context_save.d" "tx_thread_interrupt_control.d" "tx_thread_schedule.d" "tx_thread_stack_build.d" "tx_thread_system_return.d" "tx_timer_interrupt.d" + -@echo 'Finished clean' + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s index d30a2fb6..18b8d6ab 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -240,11 +247,23 @@ __tx_ts_wait STR r1, [r0] ; Store it in the current pointer CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; - IF :DEF:TX_ENABLE_WFI + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF __tx_ts_ISB CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S index 8563a92f..f1ee3a94 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -25,6 +25,10 @@ .global _tx_thread_execute_ptr .global _tx_timer_time_slice .global _tx_thread_system_stack_ptr +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif @ @ .text @@ -35,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/AC6 */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +72,10 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -244,11 +251,25 @@ __tx_ts_wait: STR r1, [r0] @ Store it in the current pointer CMP r1, #0 @ If non-NULL, a new thread is ready! BNE __tx_ts_ready @ + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m0/gnu/CMakeLists.txt b/ports/cortex_m0/gnu/CMakeLists.txt index 0e3cc8ec..0e3cc8ec 100644..100755 --- a/ports/cortex_m0/gnu/CMakeLists.txt +++ b/ports/cortex_m0/gnu/CMakeLists.txt diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index fc453b61..fc453b61 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index 710f5e26..710f5e26 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S index 4854108c..4854108c 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S index 96c9f60c..96c9f60c 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S index 9591c805..9591c805 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index 788eddde..e110259b 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -27,6 +27,10 @@ .global _tx_thread_system_stack_ptr .global _tx_execution_thread_enter .global _tx_execution_thread_exit +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif @ @ .text @@ -37,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/GNU */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,9 +74,12 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ @/* resulting in version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -248,11 +255,25 @@ __tx_ts_wait: STR r1, [r0] @ Store it in the current pointer CMP r1, #0 @ If non-NULL, a new thread is ready! BNE __tx_ts_ready @ + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index 352739b1..352739b1 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index a6a9109e..a6a9109e 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S index 9a61b0d3..9a61b0d3 100755..100644 --- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s index 02c60b6e..e4bac172 100644 --- a/ports/cortex_m0/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s @@ -28,6 +28,10 @@ EXTERN _tx_thread_preempt_disable EXTERN _tx_execution_thread_enter EXTERN _tx_execution_thread_exit +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -37,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/IAR */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +74,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -238,11 +245,25 @@ __tx_ts_wait: STR r1, [r0] ; Store it in the current pointer CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s index c1699d87..7eb7451e 100644 --- a/ports/cortex_m0/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -241,11 +248,25 @@ __tx_ts_wait STR r1, [r0] ; Store it in the current pointer CMP r1, #0 ; If non-NULL, a new thread is ready! BNE __tx_ts_ready ; - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + __tx_ts_ISB CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 9a185550..0781c2b0 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/AC6 */ -/* 6.1 */ +/* 6.1.5 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -82,6 +85,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m23/ac6/readme_threadx.txt b/ports/cortex_m23/ac6/readme_threadx.txt index 0b5ace53..66bf1636 100644 --- a/ports/cortex_m23/ac6/readme_threadx.txt +++ b/ports/cortex_m23/ac6/readme_threadx.txt @@ -15,6 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index bb9c05a9..47850b84 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -47,11 +47,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), */ /* remove unneeded headers, */ -/* use builtins, */ -/* resulting in version 6.1.3 */ +/* use builtins, added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -84,6 +85,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m23/gnu/readme_threadx.txt b/ports/cortex_m23/gnu/readme_threadx.txt index e5dacfec..357990cb 100644 --- a/ports/cortex_m23/gnu/readme_threadx.txt +++ b/ports/cortex_m23/gnu/readme_threadx.txt @@ -6,7 +6,8 @@ 1. Building the ThreadX run-time Library An example .bat file is in the example_build directory. - +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index bd9aa33b..f62f6aec 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/IAR */ -/* 6.1 */ +/* 6.1.5 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -85,6 +88,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m23/iar/readme_threadx.txt b/ports/cortex_m23/iar/readme_threadx.txt index 83cd5e2b..7f454e17 100644 --- a/ports/cortex_m23/iar/readme_threadx.txt +++ b/ports/cortex_m23/iar/readme_threadx.txt @@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project. Configure the project to build a library rather than an executable. This results in the ThreadX run-time library file tx.a, which is needed by the application. - +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index c0753dfe..82158967 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -217,11 +224,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index 526bfd35..1998d02a 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -25,6 +25,11 @@ .global _tx_thread_execute_ptr .global _tx_timer_time_slice .global _tx_thread_system_stack_ptr +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif + @ @ .text @@ -35,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/AC6 */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +73,10 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -218,11 +226,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm index 61546f63..81e1e8e0 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/GHS */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,7 +61,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -210,11 +213,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m3/gnu/CMakeLists.txt b/ports/cortex_m3/gnu/CMakeLists.txt index 71e2d4f2..71e2d4f2 100644..100755 --- a/ports/cortex_m3/gnu/CMakeLists.txt +++ b/ports/cortex_m3/gnu/CMakeLists.txt diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index b2689609..b9227c28 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -27,6 +27,10 @@ .global _tx_thread_system_stack_ptr .global _tx_execution_thread_enter .global _tx_execution_thread_exit +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif @ @ .text @@ -37,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/GNU */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,9 +74,12 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -222,11 +229,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s index e8a3c13d..4d109e86 100644 --- a/ports/cortex_m3/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -28,6 +28,10 @@ EXTERN _tx_execution_thread_enter EXTERN _tx_execution_thread_exit EXTERN _tx_thread_preempt_disable +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -37,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/IAR */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +74,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -216,11 +223,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s index beae1e0f..405f28f9 100644 --- a/ports/cortex_m3/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -217,11 +224,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m33/ac5/readme_threadx.txt b/ports/cortex_m33/ac5/readme_threadx.txt index 291d070e..6846668b 100644 --- a/ports/cortex_m33/ac5/readme_threadx.txt +++ b/ports/cortex_m33/ac5/readme_threadx.txt @@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 6. Improving Performance diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index dc9aa58f..061edfc5 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC6 */ -/* 6.1 */ +/* 6.1.5 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -82,6 +85,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt index fbc3451f..74b488f8 100644 --- a/ports/cortex_m33/ac6/readme_threadx.txt +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -15,7 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. - +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System @@ -53,80 +54,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 6. Improving Performance diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 5ded9c99..4bfb27e3 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/GNU */ -/* 6.1 */ +/* 6.1.5 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -80,6 +83,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m33/gnu/readme_threadx.txt b/ports/cortex_m33/gnu/readme_threadx.txt index 822b73ec..72f6e25e 100644 --- a/ports/cortex_m33/gnu/readme_threadx.txt +++ b/ports/cortex_m33/gnu/readme_threadx.txt @@ -8,7 +8,8 @@ Import all ThreadX common and port-specific source files into a GNU project. Configure the project to build a library rather than an executable. This results in the ThreadX run-time library file tx.a, which is needed by the application. - +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System @@ -39,80 +40,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index 5661f114..d0ff11ce 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/IAR */ -/* 6.1 */ +/* 6.1.5 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), added */ +/* ULONG64_DEFINED, */ +/* resulting in version 6.1.5 */ /* */ /**************************************************************************/ @@ -85,6 +88,7 @@ typedef unsigned long ULONG; typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt index c808670d..588fa29f 100644 --- a/ports/cortex_m33/iar/readme_threadx.txt +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project. Configure the project to build a library rather than an executable. This results in the ThreadX run-time library file tx.a, which is needed by the application. - +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System @@ -45,80 +46,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt index 9cf1f019..ac83f1ef 100644 --- a/ports/cortex_m4/ac5/readme_threadx.txt +++ b/ports/cortex_m4/ac5/readme_threadx.txt @@ -56,78 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 s0 - 0x04 s1 - 0x08 s2 - 0x0C s3 - 0x10 s4 - 0x14 s5 - 0x18 s6 - 0x1C s7 - 0x20 s8 - 0x24 s9 - 0x28 s10 - 0x2C s11 - 0x30 s12 - 0x34 s13 - 0x38 s14 - 0x3C s15 - 0x40 s16 - 0x44 s17 - 0x48 s18 - 0x4C s19 - 0x50 s20 - 0x54 s21 - 0x58 s22 - 0x5C s23 - 0x60 s24 - 0x64 s25 - 0x68 s26 - 0x6C s27 - 0x70 s28 - 0x74 s29 - 0x78 s30 - 0x7C s31 - 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 - 0xA0 r11 - 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s index 184477ff..29c8f956 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -237,11 +244,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt index dfd53faf..a4b76be4 100644 --- a/ports/cortex_m4/ac6/readme_threadx.txt +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -56,80 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 (sl) - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 6. Improving Performance diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index 9edd6a99..bd08fc2f 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -25,6 +25,11 @@ .global _tx_thread_execute_ptr .global _tx_timer_time_slice .global _tx_thread_system_stack_ptr +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif + @ @ .text @@ -35,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/AC6 */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +73,10 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -238,11 +246,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m4/ghs/readme_threadx.txt b/ports/cortex_m4/ghs/readme_threadx.txt index ad268020..f17937dd 100644 --- a/ports/cortex_m4/ghs/readme_threadx.txt +++ b/ports/cortex_m4/ghs/readme_threadx.txt @@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 s0 - 0x04 s1 - 0x08 s2 - 0x0C s3 - 0x10 s4 - 0x14 s5 - 0x18 s6 - 0x1C s7 - 0x20 s8 - 0x24 s9 - 0x28 s10 - 0x2C s11 - 0x30 s12 - 0x34 s13 - 0x38 s14 - 0x3C s15 - 0x40 s16 - 0x44 s17 - 0x48 s18 - 0x4C s19 - 0x50 s20 - 0x54 s21 - 0x58 s22 - 0x5C s23 - 0x60 s24 - 0x64 s25 - 0x68 s26 - 0x6C s27 - 0x70 s28 - 0x74 s29 - 0x78 s30 - 0x7C s31 - 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 - 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 7. Improving Performance diff --git a/ports/cortex_m4/ghs/src/tx_thread_schedule.arm b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm index bac40b7d..87ccf6d7 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/GHS */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,7 +61,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -230,11 +233,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m4/gnu/CMakeLists.txt b/ports/cortex_m4/gnu/CMakeLists.txt index 71e2d4f2..71e2d4f2 100644..100755 --- a/ports/cortex_m4/gnu/CMakeLists.txt +++ b/ports/cortex_m4/gnu/CMakeLists.txt diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt index 3d6f02a0..dc04f8e1 100644 --- a/ports/cortex_m4/gnu/readme_threadx.txt +++ b/ports/cortex_m4/gnu/readme_threadx.txt @@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 (sl) - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index f6cb7af7..47d5e3e9 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -27,6 +27,10 @@ .global _tx_thread_system_stack_ptr .global _tx_execution_thread_enter .global _tx_execution_thread_exit +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif @ @ .text @@ -37,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/GNU */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,9 +74,12 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -242,11 +249,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt index 3dfa5c42..fee26deb 100644 --- a/ports/cortex_m4/iar/readme_threadx.txt +++ b/ports/cortex_m4/iar/readme_threadx.txt @@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 (sl) - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 (sl) - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s index d4356990..45008ba3 100644 --- a/ports/cortex_m4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s @@ -28,6 +28,10 @@ EXTERN _tx_execution_thread_enter EXTERN _tx_execution_thread_exit EXTERN _tx_thread_preempt_disable +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -37,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/IAR */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +74,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -236,11 +243,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt index 0557e507..74917d18 100644 --- a/ports/cortex_m4/keil/readme_threadx.txt +++ b/ports/cortex_m4/keil/readme_threadx.txt @@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 s0 - 0x04 s1 - 0x08 s2 - 0x0C s3 - 0x10 s4 - 0x14 s5 - 0x18 s6 - 0x1C s7 - 0x20 s8 - 0x24 s9 - 0x28 s10 - 0x2C s11 - 0x30 s12 - 0x34 s13 - 0x38 s14 - 0x3C s15 - 0x40 s16 - 0x44 s17 - 0x48 s18 - 0x4C s19 - 0x50 s20 - 0x54 s21 - 0x58 s22 - 0x5C s23 - 0x60 s24 - 0x64 s25 - 0x68 s26 - 0x6C s27 - 0x70 s28 - 0x74 s29 - 0x78 s30 - 0x7C s31 - 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 - 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m4/keil/src/tx_thread_schedule.s b/ports/cortex_m4/keil/src/tx_thread_schedule.s index 347681c8..a0efcbbf 100644 --- a/ports/cortex_m4/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m4/keil/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -237,11 +244,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt index 648b030d..212fad5c 100644 --- a/ports/cortex_m7/ac5/readme_threadx.txt +++ b/ports/cortex_m7/ac5/readme_threadx.txt @@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 s0 - 0x04 s1 - 0x08 s2 - 0x0C s3 - 0x10 s4 - 0x14 s5 - 0x18 s6 - 0x1C s7 - 0x20 s8 - 0x24 s9 - 0x28 s10 - 0x2C s11 - 0x30 s12 - 0x34 s13 - 0x38 s14 - 0x3C s15 - 0x40 s16 - 0x44 s17 - 0x48 s18 - 0x4C s19 - 0x50 s20 - 0x54 s21 - 0x58 s22 - 0x5C s23 - 0x60 s24 - 0x64 s25 - 0x68 s26 - 0x6C s27 - 0x70 s28 - 0x74 s29 - 0x78 s30 - 0x7C s31 - 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 - 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s index 6f5e9daa..66f9770d 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s @@ -30,6 +30,10 @@ IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit ENDIF + IF :DEF:TX_LOW_POWER + IMPORT tx_low_power_enter + IMPORT tx_low_power_exit + ENDIF ; ; AREA ||.text||, CODE, READONLY @@ -39,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/AC5 */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +76,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -237,11 +244,25 @@ __tx_ts_wait LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} + ENDIF + + IF:DEF:TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed ENDIF + + IF:DEF:TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} + ENDIF + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt index a7f9aaae..d8dff01a 100644 --- a/ports/cortex_m7/ac6/readme_threadx.txt +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -55,24 +55,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents +Non-FPU Stack Frame: - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 6. Improving Performance diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index be98698a..302eb176 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -25,6 +25,11 @@ .global _tx_thread_execute_ptr .global _tx_timer_time_slice .global _tx_thread_system_stack_ptr +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif + @ @ .text @@ -35,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/AC6 */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +73,10 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -237,11 +245,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m7/ghs/readme_threadx.txt b/ports/cortex_m7/ghs/readme_threadx.txt index 2f0cc0ea..853e92db 100644 --- a/ports/cortex_m7/ghs/readme_threadx.txt +++ b/ports/cortex_m7/ghs/readme_threadx.txt @@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 s0 - 0x04 s1 - 0x08 s2 - 0x0C s3 - 0x10 s4 - 0x14 s5 - 0x18 s6 - 0x1C s7 - 0x20 s8 - 0x24 s9 - 0x28 s10 - 0x2C s11 - 0x30 s12 - 0x34 s13 - 0x38 s14 - 0x3C s15 - 0x40 s16 - 0x44 s17 - 0x48 s18 - 0x4C s19 - 0x50 s20 - 0x54 s21 - 0x58 s22 - 0x5C s23 - 0x60 s24 - 0x64 s25 - 0x68 s26 - 0x6C s27 - 0x70 s28 - 0x74 s29 - 0x78 s30 - 0x7C s31 - 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 - 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 7. Improving Performance diff --git a/ports/cortex_m7/ghs/src/tx_thread_schedule.arm b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm index 0871821c..07bba657 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/GHS */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -61,7 +61,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -230,11 +233,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m7/gnu/CMakeLists.txt b/ports/cortex_m7/gnu/CMakeLists.txt index 6a8d5852..6a8d5852 100644..100755 --- a/ports/cortex_m7/gnu/CMakeLists.txt +++ b/ports/cortex_m7/gnu/CMakeLists.txt diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt index 04a541cd..cdc66a3e 100644 --- a/ports/cortex_m7/gnu/readme_threadx.txt +++ b/ports/cortex_m7/gnu/readme_threadx.txt @@ -52,24 +52,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents +Non-FPU Stack Frame: - 0x00 r4 - 0x04 r5 - 0x08 r6 - 0x0C r7 - 0x10 r8 - 0x14 r9 - 0x18 r10 - 0x1C r11 - 0x20 r0 (Hardware stack starts here!!) - 0x24 r1 - 0x28 r2 - 0x2C r3 - 0x30 r12 - 0x34 lr - 0x38 pc - 0x3C xPSR + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index 2cc089dd..2cc089dd 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index 98330daa..98330daa 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S index ba269498..ba269498 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index 4dd2ae83..83363d36 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -27,6 +27,10 @@ .global _tx_thread_system_stack_ptr .global _tx_execution_thread_enter .global _tx_execution_thread_exit +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif @ @ .text @@ -37,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/GNU */ -@/* 6.1 */ +@/* 6.1.5 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,9 +74,12 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ +@/* 03-02-2021 Scott Larson Modified comment(s), add */ +@/* low power code, */ +@/* resulting in version 6.1.5 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -241,11 +248,25 @@ __tx_ts_wait: LDR r1, [r2] @ Pickup the next thread to execute pointer STR r1, [r0] @ Store it in the current pointer CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter @ Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB @ Ensure no outstanding memory transactions WFI @ Wait for interrupt ISB @ Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit @ Exit low power mode + POP {r0-r3} +#endif + CPSIE i @ Enable interrupts B __tx_ts_wait @ Loop to continue waiting @ diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S index a163ab91..a163ab91 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index 965f4482..965f4482 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S diff --git a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S index 5e1a1570..5e1a1570 100755..100644 --- a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt index 1f82f580..c35753ca 100644 --- a/ports/cortex_m7/iar/readme_threadx.txt +++ b/ports/cortex_m7/iar/readme_threadx.txt @@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 (sl) - 0x20 r11 - 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 Software stacked GP registers + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 Hardware stacked registers + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents - 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 s0 - 0x08 s1 - 0x0C s2 - 0x10 s3 - 0x14 s4 - 0x18 s5 - 0x1C s6 - 0x20 s7 - 0x24 s8 - 0x28 s9 - 0x2C s10 - 0x30 s11 - 0x34 s12 - 0x38 s13 - 0x3C s14 - 0x40 s15 - 0x44 s16 - 0x48 s17 - 0x4C s18 - 0x50 s19 - 0x54 s20 - 0x58 s21 - 0x5C s22 - 0x60 s23 - 0x64 s24 - 0x68 s25 - 0x6C s26 - 0x70 s27 - 0x74 s28 - 0x78 s29 - 0x7C s30 - 0x80 s31 - 0x84 fpscr - 0x88 r4 - 0x8C r5 - 0x90 r6 - 0x94 r7 - 0x98 r8 - 0x9C r9 - 0xA0 r10 (sl) - 0xA4 r11 - 0xA8 r0 (Hardware stack starts here!!) - 0xAC r1 - 0xB0 r2 - 0xB4 r3 - 0xB8 r12 - 0xBC lr - 0xC0 pc - 0xC4 xPSR + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s16 Software stacked FPU registers + 0x08 s17 + 0x0C s18 + 0x10 s19 + 0x14 s20 + 0x18 s21 + 0x1C s22 + 0x20 s23 + 0x24 s24 + 0x28 s25 + 0x2C s26 + 0x30 s27 + 0x34 s28 + 0x38 s29 + 0x3C s30 + 0x40 s31 + 0x44 r4 Software stacked registers + 0x48 r5 + 0x4C r6 + 0x50 r7 + 0x54 r8 + 0x58 r9 + 0x5C r10 + 0x60 r11 + 0x64 r0 Hardware stacked registers + 0x68 r1 + 0x6C r2 + 0x70 r3 + 0x74 r12 + 0x78 lr + 0x7C pc + 0x80 xPSR + 0x84 s0 Hardware stacked FPU registers + 0x88 s1 + 0x8C s2 + 0x90 s3 + 0x94 s4 + 0x98 s5 + 0x9C s6 + 0xA0 s7 + 0xA4 s8 + 0xA8 s9 + 0xAC s10 + 0xB0 s11 + 0xB4 s12 + 0xB8 s13 + 0xBC s14 + 0xC0 s15 + 0xC4 fpscr 5. Improving Performance diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s index 409c6987..15f8316c 100644 --- a/ports/cortex_m7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s @@ -28,6 +28,10 @@ EXTERN _tx_execution_thread_enter EXTERN _tx_execution_thread_exit EXTERN _tx_thread_preempt_disable +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -37,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/IAR */ -;/* 6.1 */ +;/* 6.1.5 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +74,10 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 03-02-2021 Scott Larson Modified comment(s), add */ +;/* low power code, */ +;/* resulting in version 6.1.5 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -236,11 +243,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index 21931297..8c443e84 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -12,7 +12,7 @@ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -21,35 +21,35 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h RX/CCRX */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RXv2/CCRX */ /* 6.1.3 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Express Logic, Inc. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Express Logic, Inc. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ /* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -271,7 +271,7 @@ extern volatile ULONG _tx_thread_system_state; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/CCRX Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/CCRX Version 6.1.3 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/ccrx/src/tx_initialize_low_level.src b/ports/rxv2/ccrx/src/tx_initialize_low_level.src index 72b297bf..b899086c 100644 --- a/ports/rxv2/ccrx/src/tx_initialize_low_level.src +++ b/ports/rxv2/ccrx/src/tx_initialize_low_level.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -29,47 +29,47 @@ .SECTION P,CODE ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ .GLB __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv2/ccrx/src/tx_thread_context_restore.src b/ports/rxv2/ccrx/src/tx_thread_context_restore.src index 9601dfda..7604f910 100644 --- a/ports/rxv2/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv2/ccrx/src/tx_thread_context_restore.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,46 +40,46 @@ .GLB __tx_thread_preempt_disable ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .GLB __tx_thread_context_restore diff --git a/ports/rxv2/ccrx/src/tx_thread_context_save.src b/ports/rxv2/ccrx/src/tx_thread_context_save.src index 26e94078..a5a9fdca 100644 --- a/ports/rxv2/ccrx/src/tx_thread_context_save.src +++ b/ports/rxv2/ccrx/src/tx_thread_context_save.src @@ -35,45 +35,45 @@ .GLB __tx_thread_system_stack_ptr .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .GLB __tx_thread_context_save diff --git a/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src index 39168c1d..df217a6c 100644 --- a/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src +++ b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -30,44 +30,44 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/rxv2/ccrx/src/tx_thread_schedule.src b/ports/rxv2/ccrx/src/tx_thread_schedule.src index a34c12f5..68dd53bc 100644 --- a/ports/rxv2/ccrx/src/tx_thread_schedule.src +++ b/ports/rxv2/ccrx/src/tx_thread_schedule.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,47 +37,47 @@ ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ .GLB __tx_thread_schedule diff --git a/ports/rxv2/ccrx/src/tx_thread_stack_build.src b/ports/rxv2/ccrx/src/tx_thread_stack_build.src index 38da71c9..fec60003 100644 --- a/ports/rxv2/ccrx/src/tx_thread_stack_build.src +++ b/ports/rxv2/ccrx/src/tx_thread_stack_build.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -31,46 +31,46 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ .GLB __tx_thread_stack_build diff --git a/ports/rxv2/ccrx/src/tx_thread_system_return.src b/ports/rxv2/ccrx/src/tx_thread_system_return.src index fb70a970..65918cfb 100644 --- a/ports/rxv2/ccrx/src/tx_thread_system_return.src +++ b/ports/rxv2/ccrx/src/tx_thread_system_return.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,46 +35,46 @@ .GLB __tx_thread_schedule .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the system. Only a minimal context */ -;/* is saved since the compiler assumes temp registers are going to get */ -;/* slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the system. Only a minimal context */ +;/* is saved since the compiler assumes temp registers are going to get */ +;/* slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ .GLB __tx_thread_system_return diff --git a/ports/rxv2/ccrx/src/tx_timer_interrupt.src b/ports/rxv2/ccrx/src/tx_timer_interrupt.src index cf88b6c1..ca311030 100644 --- a/ports/rxv2/ccrx/src/tx_timer_interrupt.src +++ b/ports/rxv2/ccrx/src/tx_timer_interrupt.src @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -45,50 +45,50 @@ .GLB __tx_thread_context_restore ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt RX/CCRX */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt RXv2/CCRX */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_context_save Save interrupted context */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_restore Restore interrupted context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Save interrupted context */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_restore Restore interrupted context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ .GLB __tx_timer_interrupt diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h index 57841625..912cf314 100644 --- a/ports/rxv2/gnu/inc/tx_port.h +++ b/ports/rxv2/gnu/inc/tx_port.h @@ -12,7 +12,7 @@ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -21,35 +21,35 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h RX/GNURX */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RXv2/GNURX */ /* 6.1.3 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Express Logic, Inc. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Express Logic, Inc. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ /* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -255,7 +255,7 @@ static void _tx_thread_system_return_inline(void) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/GNURX Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/GNURX Version 6.1.3 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/gnu/src/tx_initialize_low_level.S b/ports/rxv2/gnu/src/tx_initialize_low_level.S index 197ae936..0e67a2fa 100644 --- a/ports/rxv2/gnu/src/tx_initialize_low_level.S +++ b/ports/rxv2/gnu/src/tx_initialize_low_level.S @@ -28,7 +28,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_initialize_low_level RX/GNURX */ +;/* _tx_initialize_low_level RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_context_restore.S b/ports/rxv2/gnu/src/tx_thread_context_restore.S index c2799838..38ed5b8a 100644 --- a/ports/rxv2/gnu/src/tx_thread_context_restore.S +++ b/ports/rxv2/gnu/src/tx_thread_context_restore.S @@ -45,7 +45,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_restore RX/GNURX */ +;/* _tx_thread_context_restore RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_context_save.S b/ports/rxv2/gnu/src/tx_thread_context_save.S index cae38615..2ca64199 100644 --- a/ports/rxv2/gnu/src/tx_thread_context_save.S +++ b/ports/rxv2/gnu/src/tx_thread_context_save.S @@ -19,17 +19,7 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; + .global __tx_thread_system_state .global __tx_thread_current_ptr .global __tx_thread_system_stack_ptr @@ -39,7 +29,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_save RX/GNURX */ +;/* _tx_thread_context_save RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_interrupt_control.S b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S index 096c0568..e5eb4c81 100644 --- a/ports/rxv2/gnu/src/tx_thread_interrupt_control.S +++ b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S @@ -19,22 +19,13 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; + .text ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_control RX/GNURX */ +;/* _tx_thread_interrupt_control RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_schedule.S b/ports/rxv2/gnu/src/tx_thread_schedule.S index c48840e7..9742d838 100644 --- a/ports/rxv2/gnu/src/tx_thread_schedule.S +++ b/ports/rxv2/gnu/src/tx_thread_schedule.S @@ -19,18 +19,7 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; + .global __tx_thread_execute_ptr .global __tx_thread_current_ptr .global __tx_timer_time_slice @@ -41,7 +30,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_schedule RX/GNURX */ +;/* _tx_thread_schedule RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_stack_build.S b/ports/rxv2/gnu/src/tx_thread_stack_build.S index 752372bf..464e9381 100644 --- a/ports/rxv2/gnu/src/tx_thread_stack_build.S +++ b/ports/rxv2/gnu/src/tx_thread_stack_build.S @@ -19,23 +19,13 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; + .text ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_stack_build RX/GNURX */ +;/* _tx_thread_stack_build RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_thread_system_return.S b/ports/rxv2/gnu/src/tx_thread_system_return.S index baa5314a..93578b5f 100644 --- a/ports/rxv2/gnu/src/tx_thread_system_return.S +++ b/ports/rxv2/gnu/src/tx_thread_system_return.S @@ -19,17 +19,7 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; + .global __tx_thread_current_ptr .global __tx_timer_time_slice .global __tx_thread_schedule @@ -39,7 +29,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_system_return RX/GNURX */ +;/* _tx_thread_system_return RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/gnu/src/tx_timer_interrupt.S b/ports/rxv2/gnu/src/tx_timer_interrupt.S index 3511e2c8..1160a36b 100644 --- a/ports/rxv2/gnu/src/tx_timer_interrupt.S +++ b/ports/rxv2/gnu/src/tx_timer_interrupt.S @@ -19,19 +19,7 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... -; + .global __tx_timer_time_slice .global __tx_timer_system_clock .global __tx_timer_current_ptr @@ -43,13 +31,13 @@ .global __tx_thread_context_save .global __tx_thread_time_slice .global __tx_thread_context_restore -; + .SECTION P,CODE ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_timer_interrupt RX/GNURX */ +;/* _tx_timer_interrupt RXv2/GNURX */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h index 14b9728f..a63370c9 100644 --- a/ports/rxv2/iar/inc/tx_port.h +++ b/ports/rxv2/iar/inc/tx_port.h @@ -12,7 +12,7 @@ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -21,35 +21,35 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h RX/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RXv2/IAR */ /* 6.1.3 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Express Logic, Inc. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Express Logic, Inc. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ /* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -263,7 +263,7 @@ extern volatile ULONG _tx_thread_system_state; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/IAR Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.1.3 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/iar/src/tx_initialize_low_level.s b/ports/rxv2/iar/src/tx_initialize_low_level.s index 49336a57..23d2d0d5 100644 --- a/ports/rxv2/iar/src/tx_initialize_low_level.s +++ b/ports/rxv2/iar/src/tx_initialize_low_level.s @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -26,47 +26,47 @@ section .text:CODE:ROOT ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level RX/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level RXv2/IAR */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ public __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv2/iar/src/tx_thread_context_restore.s b/ports/rxv2/iar/src/tx_thread_context_restore.s index 491dae82..e01dfe63 100644 --- a/ports/rxv2/iar/src/tx_thread_context_restore.s +++ b/ports/rxv2/iar/src/tx_thread_context_restore.s @@ -12,25 +12,14 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; + extern __tx_thread_system_state extern __tx_thread_current_ptr extern __tx_thread_preempt_disable @@ -40,46 +29,46 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore RX/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore RXv2/IAR */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ public __tx_thread_context_restore __tx_thread_context_restore: diff --git a/ports/rxv2/iar/src/tx_thread_context_save.s b/ports/rxv2/iar/src/tx_thread_context_save.s index 218f65cd..597dfd71 100644 --- a/ports/rxv2/iar/src/tx_thread_context_save.s +++ b/ports/rxv2/iar/src/tx_thread_context_save.s @@ -12,67 +12,57 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; + extern __tx_thread_system_state extern __tx_thread_current_ptr section .text:CODE:ROOT - ;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save RX/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save RXv2/IAR */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ public __tx_thread_context_save diff --git a/ports/rxv2/iar/src/tx_thread_interrupt_control.s b/ports/rxv2/iar/src/tx_thread_interrupt_control.s index bd8474df..6b713ccd 100644 --- a/ports/rxv2/iar/src/tx_thread_interrupt_control.s +++ b/ports/rxv2/iar/src/tx_thread_interrupt_control.s @@ -19,54 +19,46 @@ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; + section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control RX/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control RXv2/IAR */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ public __tx_thread_interrupt_control diff --git a/ports/rxv2/iar/src/tx_thread_schedule.s b/ports/rxv2/iar/src/tx_thread_schedule.s index 9de14be1..75a138a9 100644 --- a/ports/rxv2/iar/src/tx_thread_schedule.s +++ b/ports/rxv2/iar/src/tx_thread_schedule.s @@ -12,72 +12,61 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; + extern __tx_thread_execute_ptr extern __tx_thread_current_ptr extern __tx_timer_time_slice section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule RX/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule RXv2/IAR */ ;/* 6.1.3 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ public __tx_thread_schedule diff --git a/ports/rxv2/iar/src/tx_thread_stack_build.s b/ports/rxv2/iar/src/tx_thread_stack_build.s index 688f0bc8..c66da92c 100644 --- a/ports/rxv2/iar/src/tx_thread_stack_build.s +++ b/ports/rxv2/iar/src/tx_thread_stack_build.s @@ -27,7 +27,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_stack_build RX/IAR */ +;/* _tx_thread_stack_build RXv2/IAR */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/iar/src/tx_thread_system_return.s b/ports/rxv2/iar/src/tx_thread_system_return.s index 808e345e..2c907acf 100644 --- a/ports/rxv2/iar/src/tx_thread_system_return.s +++ b/ports/rxv2/iar/src/tx_thread_system_return.s @@ -22,11 +22,11 @@ section .text:CODE:ROOT - ;/**************************************************************************/ +;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_system_return RX/IAR */ +;/* _tx_thread_system_return RXv2/IAR */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ diff --git a/ports/rxv2/iar/src/tx_timer_interrupt.s b/ports/rxv2/iar/src/tx_timer_interrupt.s index 645f73b4..700e59bc 100644 --- a/ports/rxv2/iar/src/tx_timer_interrupt.s +++ b/ports/rxv2/iar/src/tx_timer_interrupt.s @@ -36,7 +36,7 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_timer_interrupt RX/IAR */ +;/* _tx_timer_interrupt RXv2/IAR */ ;/* 6.1.3 */ ;/* AUTHOR */ ;/* */ |