diff options
Diffstat (limited to 'ports')
143 files changed, 2986 insertions, 2926 deletions
diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 11b81ac8..4a4f20db 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -236,10 +236,14 @@ __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif ; /* Do interrupt handler work here */ ; /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr @@ -253,7 +257,13 @@ SysTick_Handler ; { ; PUSH {r0, lr} +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 9dc3ea55..9099af52 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -159,12 +159,12 @@ SysTick_Handler: @ { @ PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function #endif BL _tx_timer_interrupt -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, r1} MOV lr, r1 diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index b4c52df3..aaf3ece2 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -135,55 +135,95 @@ _tx_initialize_low_level: @ LDR r0, =0xE000E000 @ Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - LDR r1, =0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control -@ -@ /* Configure handler priorities. */ -@ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD18 @ - ADD r0, r0, r2 @ - STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD1C @ - ADD r0, r0, r2 @ - STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 @ Build address of NVIC registers - LDR r2, =0xD20 @ - ADD r0, r0, r2 @ - STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF - -@ -@ /* Return to caller. */ -@ - BX lr -@} -@ -@ /* System Tick timer interrupt handler */ + STR r1, [r0, #0x14] // Setup SysTick Reload Value + LDR r1, =0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + +/* Define shells for each of the unused vectors. */ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* BL <your C Function>.... */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, r1} + MOV lr, r1 + BX lr +// } + +/* System Tick timer interrupt handler */ .global __tx_SysTickHandler .global SysTick_Handler .thumb_func __tx_SysTickHandler: .thumb_func SysTick_Handler: -@ VOID SysTick_Handler (VOID) -@ { -@ +// VOID SysTick_Handler (VOID) +// { PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function #endif BL _tx_timer_interrupt -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, r1} MOV lr, r1 BX lr -@ } +// } + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index ce79ceca..3de316e5 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -166,12 +166,12 @@ SysTick_Handler: ; { ; PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter ; Call the ISR enter function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function #endif BL _tx_timer_interrupt -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit ; Call the ISR exit function +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function #endif POP {r0, r1} MOV lr, r1 diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 11b81ac8..4a4f20db 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -236,10 +236,14 @@ __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {r0, lr} - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif ; /* Do interrupt handler work here */ ; /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr @@ -253,7 +257,13 @@ SysTick_Handler ; { ; PUSH {r0, lr} +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr diff --git a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 3ea33abb..2ef87233 100644 --- a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -29,13 +29,12 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) STACK_SIZE = 0x00000400 HEAP_SIZE = 0x00000000 - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M23/AC6 */ -/* 6.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -88,16 +87,15 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address -// /* Enable the cycle count register. */ -// + /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit @@ -165,10 +163,14 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif /* Do interrupt handler work here */ /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr @@ -186,7 +188,13 @@ SysTick_Handler: // VOID TimerInterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index baa59bfd..c70cb4d0 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -91,6 +91,12 @@ typedef short SHORT; typedef unsigned short USHORT; #define ULONG64_DEFINED +/* This port overrides tx_thread_stack_error_notify with an architecture specific version */ +#define TX_PORT_THREAD_STACK_ERROR_NOTIFY + +/* This port overrides tx_thread_stack_error_handler with an architecture specific version */ +#define TX_PORT_THREAD_STACK_ERROR_HANDLER + /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); @@ -98,12 +104,6 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); -/* This port overrides tx_thread_stack_error_notify with an architecture specific version */ -#define TX_PORT_THREAD_STACK_ERROR_NOTIFY - -/* This port overrides tx_thread_stack_error_handler with an architecture specific version */ -#define TX_PORT_THREAD_STACK_ERROR_HANDLER - /* This hardware has stack checking that we take advantage of - do NOT define. */ #ifdef TX_ENABLE_STACK_CHECKING #error "Do not define TX_ENABLE_STACK_CHECKING" diff --git a/ports/cortex_m23/ac6/inc/tx_secure_interface.h b/ports/cortex_m23/ac6/inc/tx_secure_interface.h index 976f32be..bab64f05 100644 --- a/ports/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m23/ac6/inc/tx_secure_interface.h @@ -25,8 +25,8 @@ /* */ /* COMPONENT DEFINITION RELEASE */ /* */ -/* tx_secure_interface.h Cortex-M23 */ -/* 6.1 */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_restore.s b/ports/cortex_m23/ac6/src/tx_thread_context_restore.s index ec3fe294..5a1efa6f 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_restore.s +++ b/ports/cortex_m23/ac6/src/tx_thread_context_restore.s @@ -19,11 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif - - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -48,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_save.s b/ports/cortex_m23/ac6/src/tx_thread_context_save.s index 6a7db9ff..2b45d9dc 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_save.s +++ b/ports/cortex_m23/ac6/src/tx_thread_context_save.s @@ -20,8 +20,7 @@ /**************************************************************************/ /**************************************************************************/ - -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -48,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -72,15 +71,13 @@ .type _tx_thread_context_save, function _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s index 7a24fffd..16aae2b6 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s index d99f1713..ca010871 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s index b03ad941..64a5c8ca 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports/cortex_m23/ac6/src/tx_thread_schedule.s b/ports/cortex_m23/ac6/src/tx_thread_schedule.s index a8c6f78c..4c06e1d5 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_schedule.s +++ b/ports/cortex_m23/ac6/src/tx_thread_schedule.s @@ -21,7 +21,7 @@ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -94,7 +94,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -108,7 +107,7 @@ __tx_wait_here: // } /* Generic context switching PendSV handler. */ - + .section .text .balign 4 .syntax unified @@ -120,7 +119,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -129,11 +128,9 @@ __tx_ts_handler: MOV lr, r1 // CPSIE i // Enable interrupts #endif - - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -146,27 +143,27 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0x90 // Secure stack index offset LDR r5, [r1, r5] // Load secure stack index CBZ r5, _skip_secure_save // Skip save if there is no secure context - PUSH {r0, r1, r2, r3} // Save scratch registers + PUSH {r0-r3} // Save scratch registers MOV r0, r1 // Move thread ptr to r0 BL _tx_thread_secure_stack_context_save // Save secure stack - POP {r0, r1, r2, r3} // Restore secure registers + POP {r0-r3} // Restore secure registers _skip_secure_save: #endif @@ -204,8 +201,7 @@ __tx_ts_new: __tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count - MOVW r4, #:lower16:_tx_timer_time_slice // Build address of time-slice variable - MOVT r4, #:upper16:_tx_timer_time_slice + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice ADDS r7, r7, #1 // Increment the thread run count STR r7, [r1, #4] // Store the new run count @@ -214,7 +210,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -243,15 +239,14 @@ _skip_secure_restore: LDR r5, [r3] // Recover saved LR ADDS r3, r3, #4 // Position past LR MOV lr, r5 // Restore LR - LDM r3!, {r4-r7} // Recover thread's registers (r4-r11) - MOV r11, r7 // - MOV r10, r6 // - MOV r9, r5 // - MOV r8, r4 // - LDM r3!, {r4-r7} // + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) MSR PSP, r3 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -295,6 +290,7 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) @@ -307,27 +303,27 @@ __tx_ts_ready: .thumb_func .type SVC_Handler, function SVC_Handler: - MOVW r0, #4 - MOV r1, lr - TST r1, r0 // Determine return stack from EXC_RETURN bit 2 - BEQ _tx_get_msp - MRS r0, PSP // Get PSP if return stack is PSP - B _tx_got_sp -_tx_get_msp: - MRS r0, MSP // Get MSP if return stack is MSP -_tx_got_sp: - LDR r1, [r0, #24] // Load saved PC from stack - SUBS r1, r1, #2 // Calculate SVC number address - LDRB r1, [r1] // Load SVC number + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP if return stack is PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP if return stack is MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r1, [r1,r3] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c index 0ecf2ac9..7892402b 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -308,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -393,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s index 8abd3686..4bf5c963 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -66,7 +66,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_allocate + .global _tx_thread_secure_stack_allocate .thumb_func .type _tx_thread_secure_stack_allocate, function _tx_thread_secure_stack_allocate: @@ -78,7 +78,6 @@ _tx_thread_secure_stack_allocate: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s index b142c5da..c5fc5f79 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -64,7 +64,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_free + .global _tx_thread_secure_stack_free .thumb_func .type _tx_thread_secure_stack_free, function _tx_thread_secure_stack_free: @@ -76,7 +76,6 @@ _tx_thread_secure_stack_free: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_build.s b/ports/cortex_m23/ac6/src/tx_thread_stack_build.s index 5a95a14f..4b4f443d 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_stack_build.s +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_build.s @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m23/ac6/src/tx_thread_system_return.s b/ports/cortex_m23/ac6/src/tx_thread_system_return.s index 175a9109..749b0fc1 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_system_return.s +++ b/ports/cortex_m23/ac6/src/tx_thread_system_return.s @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports/cortex_m23/ac6/src/tx_timer_interrupt.s b/ports/cortex_m23/ac6/src/tx_timer_interrupt.s index fdfcdcc5..81df88f7 100644 --- a/ports/cortex_m23/ac6/src/tx_timer_interrupt.s +++ b/ports/cortex_m23/ac6/src/tx_timer_interrupt.s @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports/cortex_m23/gnu/inc/tx_secure_interface.h b/ports/cortex_m23/gnu/inc/tx_secure_interface.h index 976f32be..bab64f05 100644 --- a/ports/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m23/gnu/inc/tx_secure_interface.h @@ -25,8 +25,8 @@ /* */ /* COMPONENT DEFINITION RELEASE */ /* */ -/* tx_secure_interface.h Cortex-M23 */ -/* 6.1 */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S index 08b635c4..e72581ac 100644 --- a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S @@ -29,13 +29,12 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) STACK_SIZE = 0x00000400 HEAP_SIZE = 0x00000000 - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M23/GNU */ -/* 6.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -165,10 +164,14 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif /* Do interrupt handler work here */ /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr @@ -186,7 +189,13 @@ SysTick_Handler: // VOID TimerInterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_restore.s b/ports/cortex_m23/gnu/src/tx_thread_context_restore.s index 2ebed08a..084635a3 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_restore.s +++ b/ports/cortex_m23/gnu/src/tx_thread_context_restore.s @@ -19,11 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif - - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -48,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_save.s b/ports/cortex_m23/gnu/src/tx_thread_context_save.s index 61ccafd8..cf58aabd 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_save.s +++ b/ports/cortex_m23/gnu/src/tx_thread_context_save.s @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -69,15 +71,13 @@ .type _tx_thread_context_save, function _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s index 4f05f3ff..b80112b3 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s index 3a1fc9f6..2ee36199 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s index 696c227b..3812e0d3 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports/cortex_m23/gnu/src/tx_thread_schedule.s b/ports/cortex_m23/gnu/src/tx_thread_schedule.s index 4cdd9773..9e73dc4f 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_schedule.s +++ b/ports/cortex_m23/gnu/src/tx_thread_schedule.s @@ -90,7 +90,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -104,7 +103,7 @@ __tx_wait_here: // } /* Generic context switching PendSV handler. */ - + .section .text .balign 4 .syntax unified @@ -116,7 +115,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -125,11 +124,9 @@ __tx_ts_handler: MOV lr, r1 // CPSIE i // Enable interrupts #endif - - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -142,27 +139,27 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0x90 // Secure stack index offset LDR r5, [r1, r5] // Load secure stack index CBZ r5, _skip_secure_save // Skip save if there is no secure context - PUSH {r0, r1, r2, r3} // Save scratch registers + PUSH {r0-r3} // Save scratch registers MOV r0, r1 // Move thread ptr to r0 BL _tx_thread_secure_stack_context_save // Save secure stack - POP {r0, r1, r2, r3} // Restore secure registers + POP {r0-r3} // Restore secure registers _skip_secure_save: #endif @@ -200,8 +197,7 @@ __tx_ts_new: __tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count - MOVW r4, #:lower16:_tx_timer_time_slice // Build address of time-slice variable - MOVT r4, #:upper16:_tx_timer_time_slice + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice ADDS r7, r7, #1 // Increment the thread run count STR r7, [r1, #4] // Store the new run count @@ -210,7 +206,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -239,15 +235,14 @@ _skip_secure_restore: LDR r5, [r3] // Recover saved LR ADDS r3, r3, #4 // Position past LR MOV lr, r5 // Restore LR - LDM r3!, {r4-r7} // Recover thread's registers (r4-r11) - MOV r11, r7 // - MOV r10, r6 // - MOV r9, r5 // - MOV r8, r4 // - LDM r3!, {r4-r7} // + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) MSR PSP, r3 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -291,6 +286,7 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) @@ -303,27 +299,27 @@ __tx_ts_ready: .thumb_func .type SVC_Handler, function SVC_Handler: - MOVW r0, #4 - MOV r1, lr - TST r1, r0 // Determine return stack from EXC_RETURN bit 2 - BEQ _tx_get_msp - MRS r0, PSP // Get PSP if return stack is PSP - B _tx_got_sp -_tx_get_msp: - MRS r0, MSP // Get MSP if return stack is MSP -_tx_got_sp: - LDR r1, [r0, #24] // Load saved PC from stack - SUBS r1, r1, #2 // Calculate SVC number address - LDRB r1, [r1] // Load SVC number + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP if return stack is PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP if return stack is MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r1, [r1,r3] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c index 57864edd..cd91548d 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c @@ -105,6 +105,7 @@ UINT _tx_thread_secure_mode_stack_initialize(void) { UINT status; ULONG control; +ULONG ipsr; /* Make sure function is called from interrupt (threads should not call). */ asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s index 527a0332..c3d973f6 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -78,7 +78,6 @@ _tx_thread_secure_stack_allocate: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s index 94ef8f55..9e20b48d 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -76,7 +76,6 @@ _tx_thread_secure_stack_free: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_build.s b/ports/cortex_m23/gnu/src/tx_thread_stack_build.s index 704c5dfd..bd9fe738 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_stack_build.s +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_build.s @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m23/gnu/src/tx_thread_system_return.s b/ports/cortex_m23/gnu/src/tx_thread_system_return.s index 7aa911b0..cf3536d5 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_system_return.s +++ b/ports/cortex_m23/gnu/src/tx_thread_system_return.s @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports/cortex_m23/gnu/src/tx_timer_interrupt.s b/ports/cortex_m23/gnu/src/tx_timer_interrupt.s index 0e2ea836..7b42d195 100644 --- a/ports/cortex_m23/gnu/src/tx_timer_interrupt.s +++ b/ports/cortex_m23/gnu/src/tx_timer_interrupt.s @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index 82e2ed90..ac6e2baf 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -94,6 +94,12 @@ typedef short SHORT; typedef unsigned short USHORT; #define ULONG64_DEFINED +/* This port overrides tx_thread_stack_error_notify with an architecture specific version */ +#define TX_PORT_THREAD_STACK_ERROR_NOTIFY + +/* This port overrides tx_thread_stack_error_handler with an architecture specific version */ +#define TX_PORT_THREAD_STACK_ERROR_HANDLER + /* Function prototypes for this port. */ struct TX_THREAD_STRUCT; UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); @@ -101,12 +107,6 @@ UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); -/* This port overrides tx_thread_stack_error_notify with an architecture specific version */ -#define TX_PORT_THREAD_STACK_ERROR_NOTIFY - -/* This port overrides tx_thread_stack_error_handler with an architecture specific version */ -#define TX_PORT_THREAD_STACK_ERROR_HANDLER - /* This hardware has stack checking that we take advantage of - do NOT define. */ #ifdef TX_ENABLE_STACK_CHECKING #error "Do not define TX_ENABLE_STACK_CHECKING" diff --git a/ports/cortex_m23/iar/inc/tx_secure_interface.h b/ports/cortex_m23/iar/inc/tx_secure_interface.h index 976f32be..bab64f05 100644 --- a/ports/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m23/iar/inc/tx_secure_interface.h @@ -25,8 +25,8 @@ /* */ /* COMPONENT DEFINITION RELEASE */ /* */ -/* tx_secure_interface.h Cortex-M23 */ -/* 6.1 */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m23/iar/src/tx_initialize_low_level.s b/ports/cortex_m23/iar/src/tx_initialize_low_level.s index 92a5f4d2..f73a5563 100644 --- a/ports/cortex_m23/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m23/iar/src/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,135 +27,123 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -164,40 +151,48 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } - +// } PUBLIC HardFault_Handler HardFault_Handler: - ; A stack overflow will trigger a hardfault. - ; There is no CFSR in M23, so we will not try to - ; determine if the fault is caused by a stack overflow - ; or some other condition. + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. B HardFault_Handler diff --git a/ports/cortex_m23/iar/src/tx_thread_context_restore.s b/ports/cortex_m23/iar/src/tx_thread_context_restore.s index 51704008..81fa6815 100644 --- a/ports/cortex_m23/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m23/iar/src/tx_thread_context_restore.s @@ -1,71 +1,71 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_exit SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function @@ -73,5 +73,5 @@ _tx_thread_context_restore: #endif BX lr -;} +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_context_save.s b/ports/cortex_m23/iar/src/tx_thread_context_save.s index 68219205..2ad3e476 100644 --- a/ports/cortex_m23/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m23/iar/src/tx_thread_context_save.s @@ -1,79 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_enter SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { PUBLIC _tx_thread_context_save _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr -;} +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s index 83381d72..d9ee6e88 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s @@ -1,77 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s index 41ad894f..010d3331 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s @@ -1,76 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ MRS r0, PRIMASK CPSID i BX lr -; -;} +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s index dd1c2985..054d3d8e 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s @@ -1,75 +1,71 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: -; -; /* Restore previous interrupt lockout posture. */ -; + /* Restore previous interrupt lockout posture. */ MSR PRIMASK, r0 BX lr -; -;} +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_schedule.s b/ports/cortex_m23/iar/src/tx_thread_schedule.s index 8b5ebf20..fed4d1e2 100644 --- a/ports/cortex_m23/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m23/iar/src/tx_thread_schedule.s @@ -84,8 +84,8 @@ /* resulting in version 6.1.7 */ /* */ /**************************************************************************/ -;VOID _tx_thread_schedule(VOID) -;{ +// VOID _tx_thread_schedule(VOID) +// { PUBLIC _tx_thread_schedule _tx_thread_schedule: /* This function should only ever be called on Cortex-M @@ -93,7 +93,7 @@ _tx_thread_schedule: from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOV r0, #0 // Build value for TX_FALSE + MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag @@ -101,7 +101,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -120,7 +119,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -130,9 +129,9 @@ __tx_ts_handler: CPSIE i // Enable interrupts #endif - MOV32 r0, _tx_thread_current_ptr // Build current thread pointer address - MOV32 r2, _tx_thread_execute_ptr // Build execute thread pointer address - MOV r3, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer /* Determine if there is a current thread to finish preserving. */ @@ -144,27 +143,27 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0x90 // Secure stack index offset LDR r5, [r1, r5] // Load secure stack index CBZ r5, _skip_secure_save // Skip save if there is no secure context - PUSH {r0, r1, r2, r3} // Save scratch registers + PUSH {r0-r3} // Save scratch registers MOV r0, r1 // Move thread ptr to r0 BL _tx_thread_secure_stack_context_save // Save secure stack - POP {r0, r1, r2, r3} // Restore secure registers + POP {r0-r3} // Restore secure registers _skip_secure_save: #endif @@ -180,7 +179,7 @@ _skip_secure_save: /* Clear the global time-slice. */ - MOVS r5, #0 // Build clear value + MOVW r5, #0 // Build clear value STR r5, [r4] // Clear time-slice /* Executing thread is now completely preserved!!! */ @@ -202,7 +201,7 @@ __tx_ts_new: __tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count - MOV32 r4, _tx_timer_time_slice // Build address of time-slice variable + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice ADDS r7, r7, #1 // Increment the thread run count STR r7, [r1, #4] // Store the new run count @@ -211,7 +210,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -240,15 +239,14 @@ _skip_secure_restore: LDR r5, [r3] // Recover saved LR ADDS r3, r3, #4 // Position past LR MOV lr, r5 // Restore LR - LDM r3!, {r4-r7} // Recover thread's registers (r4-r11) - MOV r11, r7 // - MOV r10, r6 // - MOV r9, r5 // - MOV r8, r4 // - LDM r3!, {r4-r7} // + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) MSR PSP, r3 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -292,33 +290,34 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // SVC_Handler is not needed when ThreadX is running in single mode. PUBLIC SVC_Handler SVC_Handler: - MOVS r0, #4 - MOV r1, lr - TST r1, r0 // Determine return stack from EXC_RETURN bit 2 - BEQ _tx_get_msp - MRS r0, PSP // Get PSP if return stack is PSP - B _tx_got_sp -_tx_get_msp: - MRS r0, MSP // Get MSP if return stack is MSP -_tx_got_sp: - LDR r1, [r0, #24] // Load saved PC from stack - SUBS r1, r1, #2 // Calculate SVC number address - LDRB r1, [r1] // Load SVC number + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP if return stack is PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP if return stack is MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r1, [r1,r3] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c index 4ffc8d10..72e3af97 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c @@ -308,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -393,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s index 9ae3dcdb..357cef18 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s @@ -1,82 +1,80 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to allocate a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* stack_size Size of secure stack to */ -;/* allocate */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { EXPORT _tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 1 - CMP r3, #0 ; If interrupts enabled, just return + CMP r3, #0 // If interrupts enabled, just return BEQ _alloc_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled BX lr - END diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s index b8e5bef8..51906446 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s @@ -1,78 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_free Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to free a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 2 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { EXPORT _tx_thread_secure_stack_free _tx_thread_secure_stack_free: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 2 - CMP r3, #0 ; If interrupts enabled, just return + CMP r3, #0 // If interrupts enabled, just return BEQ _free_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled BX lr diff --git a/ports/cortex_m23/iar/src/tx_thread_stack_build.s b/ports/cortex_m23/iar/src/tx_thread_stack_build.s index 6525df4a..204be424 100644 --- a/ports/cortex_m23/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m23/iar/src/tx_thread_stack_build.s @@ -1,138 +1,136 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M23 should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; - BICS r2, r2, r3 ; Align frame for 8-byte alignment - SUBS r2, r2, #68 ; Subtract frame size + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE - LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode #else - LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP #endif - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r8 - STR r3, [r2, #8] ; Store initial r9 - STR r3, [r2, #12] ; Store initial r10 - STR r3, [r2, #16] ; Store initial r11 - STR r3, [r2, #20] ; Store initial r4 - STR r3, [r2, #24] ; Store initial r5 - STR r3, [r2, #28] ; Store initial r6 - STR r3, [r2, #32] ; Store initial r7 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - LDR r3, =0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports/cortex_m23/iar/src/tx_thread_system_return.s b/ports/cortex_m23/iar/src/tx_thread_system_return.s index 1afb41f6..4c977e88 100644 --- a/ports/cortex_m23/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m23/iar/src/tx_thread_system_return.s @@ -1,87 +1,84 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - LDR r0, =0x10000000 ; Load PENDSVSET bit - LDR r1, =0xE000ED04 ; Load ICSR address - STR r0, [r1] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture _isr_context: - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports/cortex_m23/iar/src/tx_timer_interrupt.s b/ports/cortex_m23/iar/src/tx_timer_interrupt.s index 89e185b3..df397a64 100644 --- a/ports/cortex_m23/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m23/iar/src/tx_timer_interrupt.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock EXTERN _tx_timer_current_ptr @@ -33,224 +32,220 @@ EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_preempt_disable -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* the expiration functions are called. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { PUBLIC _tx_timer_interrupt _tx_timer_interrupt: -; -; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADDS r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUBS r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADDS r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -; -; } -; + // } + __tx_timer_not_ts_expiration: -; - POP {r0, r1} ; Recover lr register (r0 is just there for - MOV lr, r1 ; the 8-byte stack alignment -; -; } -; + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } END diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s index 75d971d2..aa2f30a4 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit #endif @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_save.s b/ports/cortex_m3/ac5/src/tx_thread_context_save.s index d9f27da5..78cbc3c9 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_save.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter #endif @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_save _tx_thread_context_save -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index 61371a3b..f2b1d103 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -25,7 +25,7 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr IMPORT _tx_thread_preempt_disable -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif @@ -124,7 +124,7 @@ PendSV_Handler __tx_ts_handler -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S index 5159d0a3..9dbe0204 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S index 0e8dd3bd..5061b512 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -23,7 +23,7 @@ .text .align 4 .syntax unified -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -70,7 +70,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index f93ea4e2..7f43ef4e 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -23,7 +23,7 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -130,7 +130,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -204,7 +204,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -239,7 +239,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -249,7 +251,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S index 017a8809..4b62c21c 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_save.S b/ports/cortex_m3/gnu/src/tx_thread_context_save.S index f45292d8..13283881 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_save.S @@ -67,7 +67,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index 9ee1d9f7..7c2d6c3e 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -128,7 +128,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -202,7 +202,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -237,7 +237,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -247,7 +249,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m3/iar/src/tx_thread_context_restore.s b/ports/cortex_m3/iar/src/tx_thread_context_restore.s index 45341c70..992585eb 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_restore.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m3/iar/src/tx_thread_context_save.s b/ports/cortex_m3/iar/src/tx_thread_context_save.s index 8bb771cb..cae664e0 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_save.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s index 7b1235a5..d27465a3 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s @@ -67,7 +67,7 @@ _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ #ifdef TX_PORT_USE_BASEPRI MRS r0, BASEPRI - LDR r1, =TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI MSR BASEPRI, r1 #else MRS r0, PRIMASK diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s index 941f5398..6584a90a 100644 --- a/ports/cortex_m3/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -124,7 +124,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct index 4f774274..b31ea8a4 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -11,8 +11,8 @@ ; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; <h> RAM Configuration @@ -20,8 +20,8 @@ ; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00020000 /*--------------------- Stack / Heap Configuration --------------------------- ; <h> Stack / Heap Configuration @@ -29,29 +29,27 @@ ; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 /*---------------------------------------------------------------------------- - User Stack & Heap boundary definition + User Stack & Heap boundery definition *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 95ceb7a1..a5e8e946 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -154,10 +154,14 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif /* Do interrupt handler work here */ /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} BX LR // } @@ -174,7 +178,13 @@ SysTick_Handler: // VOID TimerInterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} BX LR // } @@ -223,7 +233,7 @@ _unhandled_usage_loop: BL _tx_thread_stack_error_handler // Call ThreadX/user handler POP {r0,lr} // Restore LR and dummy reg -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) // Call the thread exit function to indicate the thread is no longer executing. PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function diff --git a/ports/cortex_m33/ac6/inc/tx_secure_interface.h b/ports/cortex_m33/ac6/inc/tx_secure_interface.h index c2779f40..bab64f05 100644 --- a/ports/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m33/ac6/inc/tx_secure_interface.h @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index a148559a..3267966b 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -19,11 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif - - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index 90c8e61a..8ca8d4af 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -20,8 +20,7 @@ /**************************************************************************/ /**************************************************************************/ - -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -72,15 +71,13 @@ .type _tx_thread_context_save, function _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index bbb3da9a..452c4cae 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -68,11 +68,15 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index e3a95f5c..51e528ae 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 @@ -70,8 +70,14 @@ .type _tx_thread_interrupt_disable, function _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index 2e29b3cb..f79cb12a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 @@ -70,7 +70,11 @@ .type _tx_thread_interrupt_restore, function _tx_thread_interrupt_restore: /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr // } .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index e0c71318..9ca58e90 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -21,7 +21,7 @@ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -101,7 +101,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -127,7 +126,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -135,6 +134,7 @@ __tx_ts_handler: POP {r0, lr} // Recover LR CPSIE i // Enable interrupts #endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOV r3, #0 // Build NULL value @@ -211,7 +211,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -243,7 +243,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -287,6 +286,7 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) @@ -299,44 +299,44 @@ __tx_ts_ready: .thumb_func .type SVC_Handler, function SVC_Handler: - TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP if return stack is MSP - MRSNE r0, PSP // Get PSP if return stack is PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP - LDR r1, [r0,#24] // Load saved PC from stack - LDRB r1, [r1,#-2] // Load SVC number + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr _tx_svc_secure_alloc: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_free: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_init: - PUSH {r0,lr} // Save SP and EXC_RETURN + PUSH {r0,lr} // Save SP and EXC_RETURN BL _tx_thread_secure_mode_stack_initialize - POP {r12,lr} // Restore SP and EXC_RETURN + POP {r12,lr} // Restore SP and EXC_RETURN BX lr #endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c index e8edd2f5..af8d77f0 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -305,7 +305,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -390,7 +390,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index 3e3870b0..a3e42ba9 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -66,7 +66,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_allocate + .global _tx_thread_secure_stack_allocate .thumb_func .type _tx_thread_secure_stack_allocate, function _tx_thread_secure_stack_allocate: diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index 1511d779..a30f9e8b 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -64,7 +64,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_free + .global _tx_thread_secure_stack_free .thumb_func .type _tx_thread_secure_stack_free, function _tx_thread_secure_stack_free: diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index 16f98ef2..f4de0fe6 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -72,7 +72,7 @@ .type _tx_thread_stack_build, function _tx_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack - on the Cortex-M33 should look like the following after it is built: + on the Cortex-M should look like the following after it is built: Stack Top: LR Interrupted LR (LR at time of PENDSV) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c index 98e86a2e..5c643784 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,7 +75,6 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c index afa5b98f..0ad24a46 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index 7094adfd..851eae4e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -75,14 +75,21 @@ _tx_thread_system_return: replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit - LDR r1, =0xE000E000 // Load NVIC base + MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller // } diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index b1599312..63615c0f 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -74,8 +73,7 @@ .type _tx_timer_interrupt, function _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -92,22 +90,23 @@ _tx_timer_interrupt: LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUB r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOV r0, #1 // Build expired value @@ -127,8 +126,8 @@ __tx_timer_no_time_slice: CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; LDR r3, =_tx_timer_expired // Pickup expiration flag address MOV r2, #1 // Build expired value @@ -140,21 +139,21 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADD r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start @@ -166,7 +165,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -182,7 +180,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -194,8 +192,8 @@ __tx_something_expired: CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -211,8 +209,8 @@ __tx_timer_dont_activate: CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -223,17 +221,17 @@ __tx_timer_dont_activate: LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register - MOV r2, 0x10000000 // Build value for PendSV bit + LDR r2, =0x10000000 // Build value for PendSV bit CMP r1, r3 // Are they the same? BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment // } @@ -241,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..e67ebacc 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c index f8207c68..9f6ed6b9 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports/cortex_m33/gnu/inc/tx_secure_interface.h b/ports/cortex_m33/gnu/inc/tx_secure_interface.h index 6fa51319..bab64f05 100644 --- a/ports/cortex_m33/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m33/gnu/inc/tx_secure_interface.h @@ -25,8 +25,8 @@ /* */ /* COMPONENT DEFINITION RELEASE */ /* */ -/* tx_secure_interface.h Cortex-M33 */ -/* 6.1 */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S index 3f7cc108..97a26765 100644 --- a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S @@ -117,11 +117,9 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -154,12 +152,16 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif /* Do interrupt handler work here */ /* .... */ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR + BX lr // } @@ -174,9 +176,15 @@ SysTick_Handler: // VOID TimerInterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR + BX lr // } @@ -223,7 +231,7 @@ _unhandled_usage_loop: BL _tx_thread_stack_error_handler // Call ThreadX/user handler POP {r0,lr} // Restore LR and dummy reg -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) // Call the thread exit function to indicate the thread is no longer executing. PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S index ab7931d0..b86c6ea3 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S @@ -19,11 +19,10 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif - - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_save.S b/ports/cortex_m33/gnu/src/tx_thread_context_save.S index 0f76ccaa..5f180511 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -69,15 +71,13 @@ .type _tx_thread_context_save, function _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S index bbe60f44..f0335e70 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S @@ -68,11 +68,15 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S index 62ed1d07..eca0f5d4 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 @@ -70,8 +70,14 @@ .type _tx_thread_interrupt_disable, function _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr // } .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S index e33ce2b0..a42b12d0 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 @@ -70,7 +70,11 @@ .type _tx_thread_interrupt_restore, function _tx_thread_interrupt_restore: /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr // } .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_schedule.S b/ports/cortex_m33/gnu/src/tx_thread_schedule.S index 31da6fc8..9f3adbbf 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m33/gnu/src/tx_thread_schedule.S @@ -97,7 +97,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -123,7 +122,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -131,6 +130,7 @@ __tx_ts_handler: POP {r0, lr} // Recover LR CPSIE i // Enable interrupts #endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOV r3, #0 // Build NULL value @@ -207,7 +207,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -239,7 +239,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -283,6 +282,7 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) @@ -295,44 +295,44 @@ __tx_ts_ready: .thumb_func .type SVC_Handler, function SVC_Handler: - TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP if return stack is MSP - MRSNE r0, PSP // Get PSP if return stack is PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP - LDR r1, [r0,#24] // Load saved PC from stack - LDRB r1, [r1,#-2] // Load SVC number + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr _tx_svc_secure_alloc: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_free: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_init: - PUSH {r0,lr} // Save SP and EXC_RETURN + PUSH {r0,lr} // Save SP and EXC_RETURN BL _tx_thread_secure_mode_stack_initialize - POP {r12,lr} // Restore SP and EXC_RETURN + POP {r12,lr} // Restore SP and EXC_RETURN BX lr #endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE @@ -345,6 +345,8 @@ _tx_svc_secure_init: .thumb_func .type _tx_vfp_access, function _tx_vfp_access: +#if TX_ENABLE_FPU_SUPPORT VMOV.F32 s0, s0 // Simply access the VFP +#endif BX lr // Return to caller .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c index f1b7e8d5..38ddfbf8 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c @@ -81,10 +81,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* CALLS */ /* */ -/* __get_CONTROL Intrinsic to get CONTROL */ -/* __set_CONTROL Intrinsic to set CONTROL */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ @@ -163,12 +160,9 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ /* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ /* free Compiler's free() function */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ /* */ /* CALLED BY */ /* */ @@ -291,7 +285,6 @@ ULONG psplim_ns; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ /* free Compiler's free() function */ /* */ /* CALLED BY */ @@ -374,10 +367,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ -/* __get_PSP Intrinsic to get PSP */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ @@ -462,9 +452,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S index 5bda6d11..0e85e2a1 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S @@ -72,7 +72,7 @@ .type _tx_thread_stack_build, function _tx_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack - on the Cortex-M33 should look like the following after it is built: + on the Cortex-M should look like the following after it is built: Stack Top: LR Interrupted LR (LR at time of PENDSV) diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c index 8d892e6c..5c643784 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c @@ -38,7 +38,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/GNU */ +/* _tx_thread_stack_error_handler Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c index 6c2006ad..0ad24a46 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c @@ -35,7 +35,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/GNU */ +/* _tx_thread_stack_error_notify Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ diff --git a/ports/cortex_m33/gnu/src/tx_thread_system_return.S b/ports/cortex_m33/gnu/src/tx_thread_system_return.S index a053e85f..ed3b627b 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m33/gnu/src/tx_thread_system_return.S @@ -75,14 +75,21 @@ _tx_thread_system_return: replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit - LDR r1, =0xE000E000 // Load NVIC base + MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller // } diff --git a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S index 5e5311a3..13deac48 100644 --- a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -74,8 +73,7 @@ .type _tx_timer_interrupt, function _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -92,22 +90,23 @@ _tx_timer_interrupt: LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUB r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOV r0, #1 // Build expired value @@ -127,8 +126,8 @@ __tx_timer_no_time_slice: CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; LDR r3, =_tx_timer_expired // Pickup expiration flag address MOV r2, #1 // Build expired value @@ -140,21 +139,21 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADD r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start @@ -166,7 +165,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -182,7 +180,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -194,8 +192,8 @@ __tx_something_expired: CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -211,8 +209,8 @@ __tx_timer_dont_activate: CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -223,17 +221,17 @@ __tx_timer_dont_activate: LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register - MOV r2, 0x10000000 // Build value for PendSV bit + LDR r2, =0x10000000 // Build value for PendSV bit CMP r1, r3 // Are they the same? BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment // } @@ -241,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c index 9ad9b439..e67ebacc 100644 --- a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c @@ -33,7 +33,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_allocate Cortex-M33/GNU */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c index 3b9f2f2f..9f6ed6b9 100644 --- a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c @@ -33,7 +33,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free Cortex-M33/GNU */ +/* _txe_thread_secure_stack_free Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ diff --git a/ports/cortex_m33/iar/inc/tx_secure_interface.h b/ports/cortex_m33/iar/inc/tx_secure_interface.h index c2779f40..bab64f05 100644 --- a/ports/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m33/iar/inc/tx_secure_interface.h @@ -51,9 +51,10 @@ /* Define internal secure thread stack function prototypes. */ -extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_initialize(void); extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_initialize(void); extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s index 27922ca2..1ba0a002 100644 --- a/ports/cortex_m33/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,126 +27,112 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -155,30 +140,39 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC HardFault_Handler HardFault_Handler: @@ -187,48 +181,48 @@ HardFault_Handler: PUBLIC UsageFault_Handler UsageFault_Handler: - CPSID i ; Disable interrupts - ; Check for stack limit fault - LDR r0, =0xE000ED28 ; CFSR address - LDR r1,[r0] ; Pick up CFSR - TST r1, #0x00100000 ; Check for Stack Overflow + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow _unhandled_usage_loop - BEQ _unhandled_usage_loop ; If not stack overflow then loop + BEQ _unhandled_usage_loop // If not stack overflow then loop - ; Handle stack overflow - STR r1, [r0] ; Clear CFSR flag(s) + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) #ifdef __ARMVFP__ - LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address - LDR r1, [r0] ; Load FPCCR - BIC r1, r1, #1 ; Clear the lazy preservation active bit - STR r1, [r0] ; Store the value + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value #endif - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r0,[r0] ; Pick up current thread pointer - PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) - BL _tx_thread_stack_error_handler ; Call ThreadX/user handler - POP {r0,lr} ; Restore LR and dummy reg + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - ; Call the thread exit function to indicate the thread is no longer executing. - PUSH {r0, lr} ; Save LR (and r0 just for alignment) - BL _tx_execution_thread_exit ; Call the thread exit function - POP {r0, lr} ; Recover LR +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR #endif - MOV r1, #0 ; Build NULL value - LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer - STR r1, [r0] ; Clear current thread pointer + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer - ; Return from UsageFault_Handler exception - LDR r0, =0xE000ED04 ; Load ICSR - LDR r1, =0x10000000 ; Set PENDSVSET bit - STR r1, [r0] ; Store ICSR - DSB ; Wait for memory access to complete - CPSIE i ; Enable interrupts - BX lr ; Return from exception + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception PUBLIC __tx_NMIHandler diff --git a/ports/cortex_m33/iar/src/tx_thread_context_restore.s b/ports/cortex_m33/iar/src/tx_thread_context_restore.s index 3217ef18..19f225d6 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_restore.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_exit SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_context_save.s b/ports/cortex_m33/iar/src/tx_thread_context_save.s index 49f55f4f..1e725265 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_save.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_enter SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { PUBLIC _tx_thread_context_save _tx_thread_context_save: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s index faa06ed3..45e5c5de 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s @@ -1,77 +1,78 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s index fb01c9d1..68421f0e 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s @@ -1,76 +1,78 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr -; -;} +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s index ce4da3c3..c590eb13 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s @@ -1,75 +1,75 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: -; -; /* Restore previous interrupt lockout posture. */ -; + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr -; -;} +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index d9accd71..003f8114 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -108,7 +108,6 @@ _tx_thread_schedule: CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -127,7 +126,7 @@ __tx_wait_here: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -135,6 +134,7 @@ __tx_ts_handler: POP {r0, lr} // Recover LR CPSIE i // Enable interrupts #endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address MOV r3, #0 // Build NULL value @@ -211,7 +211,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -243,7 +243,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ BX lr // Return to thread! /* The following is the idle wait processing... in this case, no threads are ready for execution and the @@ -287,50 +286,51 @@ __tx_ts_ready: /* Re-enable interrupts and restore new thread. */ CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // SVC_Handler is not needed when ThreadX is running in single mode. PUBLIC SVC_Handler SVC_Handler: - TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP if return stack is MSP - MRSNE r0, PSP // Get PSP if return stack is PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP - LDR r1, [r0,#24] // Load saved PC from stack - LDRB r1, [r1,#-2] // Load SVC number + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number - CMP r1, #1 // Is it a secure stack allocate request? - BEQ _tx_svc_secure_alloc // Yes, go there + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there - CMP r1, #2 // Is it a secure stack free request? - BEQ _tx_svc_secure_free // Yes, go there + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there - CMP r1, #3 // Is it a secure stack init request? - BEQ _tx_svc_secure_init // Yes, go there + CMP r1, #3 // Is it a secure stack init request? + BEQ _tx_svc_secure_init // Yes, go there // Unknown SVC argument - just return BX lr _tx_svc_secure_alloc: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_free: - PUSH {r0,lr} // Save SP and EXC_RETURN - LDM r0, {r0-r3} // Load function parameters from stack + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free - POP {r12,lr} // Restore SP and EXC_RETURN - STR r0,[r12] // Store function return value + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value BX lr _tx_svc_secure_init: - PUSH {r0,lr} // Save SP and EXC_RETURN + PUSH {r0,lr} // Save SP and EXC_RETURN BL _tx_thread_secure_mode_stack_initialize - POP {r12,lr} // Restore SP and EXC_RETURN + POP {r12,lr} // Restore SP and EXC_RETURN BX lr #endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE @@ -339,5 +339,4 @@ _tx_svc_secure_init: _tx_vfp_access: VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - END diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c index ab9fdedc..f48ff16d 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c @@ -304,7 +304,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -389,7 +389,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s index 817746bb..35923943 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s @@ -1,82 +1,80 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to allocate a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* stack_size Size of secure stack to */ -;/* allocate */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { EXPORT _tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 1 - CMP r3, #0 ; If interrupts enabled, just return + CMP r3, #0 // If interrupts enabled, just return BEQ _alloc_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOV r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled BX lr - END diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s index 204b40c2..851f3621 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s @@ -1,78 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_free Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to free a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 2 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { EXPORT _tx_thread_secure_stack_free _tx_thread_secure_stack_free: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 2 - CMP r3, #0 ; If interrupts enabled, just return + CMP r3, #0 // If interrupts enabled, just return BEQ _free_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOV r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled BX lr diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_build.s b/ports/cortex_m33/iar/src/tx_thread_stack_build.s index e891b8ff..d4131978 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m33/iar/src/tx_thread_stack_build.s @@ -1,137 +1,135 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M33/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M33 should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - BIC r2, r2, #0x7 ; Align frame for 8-byte alignment - SUB r2, r2, #68 ; Subtract frame size + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE - LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode #else - LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP #endif - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r4 - STR r3, [r2, #8] ; Store initial r5 - STR r3, [r2, #12] ; Store initial r6 - STR r3, [r2, #16] ; Store initial r7 - STR r3, [r2, #20] ; Store initial r8 - STR r3, [r2, #24] ; Store initial r9 - STR r3, [r2, #28] ; Store initial r10 - STR r3, [r2, #32] ; Store initial r11 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - MOV r3, #0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c index 27ac5c42..5c643784 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,7 +75,6 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c index 328103b2..0ad24a46 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s index 2f0c2c4e..2b8aea89 100644 --- a/ports/cortex_m33/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -1,87 +1,91 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - MOV r0, #0x10000000 ; Load PENDSVSET bit - MOV r1, #0xE000E000 ; Load NVIC base - STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports/cortex_m33/iar/src/tx_timer_interrupt.s b/ports/cortex_m33/iar/src/tx_timer_interrupt.s index bed202d4..f13e9f0f 100644 --- a/ports/cortex_m33/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m33/iar/src/tx_timer_interrupt.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock EXTERN _tx_timer_current_ptr @@ -33,224 +32,220 @@ EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_preempt_disable -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M33/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* the expiration functions are called. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { PUBLIC _tx_timer_interrupt _tx_timer_interrupt: -; -; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADD r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUB r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADD r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -; -; } -; + // } + __tx_timer_not_ts_expiration: -; - LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for - ; the 8-byte stack alignment -; -; } -; + + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } END diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..e67ebacc 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c index f8207c68..9f6ed6b9 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s index 7fbd5068..8576cae4 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit #endif @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_save.s b/ports/cortex_m4/ac5/src/tx_thread_context_save.s index b922b93f..4fded670 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_save.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter #endif @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_save _tx_thread_context_save -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s index a9e00641..e497ee29 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s @@ -25,7 +25,7 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr IMPORT _tx_thread_preempt_disable -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif @@ -124,7 +124,7 @@ PendSV_Handler __tx_ts_handler -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S index f19694aa..6e1fe7cf 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S index 932f84c4..15ad1292 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -23,7 +23,7 @@ .text .align 4 .syntax unified -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -70,7 +70,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index 4fb842db..d2e748af 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -23,7 +23,7 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -130,7 +130,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -204,7 +204,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -239,7 +239,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -249,7 +251,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S index 5fb71275..852d8302 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_save.S b/ports/cortex_m4/gnu/src/tx_thread_context_save.S index 08dafb44..1c8a2ebf 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_save.S @@ -67,7 +67,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index 9457c88e..2bf7656f 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -128,7 +128,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -202,7 +202,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -237,7 +237,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -247,7 +249,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m4/iar/src/tx_thread_context_restore.s b/ports/cortex_m4/iar/src/tx_thread_context_restore.s index 02aeae3d..0fa97b59 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_restore.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m4/iar/src/tx_thread_context_save.s b/ports/cortex_m4/iar/src/tx_thread_context_save.s index a2a6f84c..e8ea6166 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_save.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s index d33d2b15..78fd91d2 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s @@ -67,7 +67,7 @@ _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ #ifdef TX_PORT_USE_BASEPRI MRS r0, BASEPRI - LDR r1, =TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI MSR BASEPRI, r1 #else MRS r0, PRIMASK diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s index 1d48c61e..927fb3d5 100644 --- a/ports/cortex_m4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s @@ -124,7 +124,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s index b14f539c..48c7afbf 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit #endif @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_save.s b/ports/cortex_m7/ac5/src/tx_thread_context_save.s index 9600e9fb..1230e4e8 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_save.s @@ -20,7 +20,7 @@ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter #endif @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -69,7 +69,7 @@ EXPORT _tx_thread_context_save _tx_thread_context_save -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s index a7bfb59e..a09eadd2 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s @@ -25,7 +25,7 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr IMPORT _tx_thread_preempt_disable -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif @@ -124,7 +124,7 @@ PendSV_Handler __tx_ts_handler -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S index bb4ec403..341e8a16 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S index efe70556..62d8b329 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -23,7 +23,7 @@ .text .align 4 .syntax unified -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif /**************************************************************************/ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -70,7 +70,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index 86f9a7a8..b8ca4f1b 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -23,7 +23,7 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -130,7 +130,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -204,7 +204,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -239,7 +239,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -249,7 +251,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index d3f50e9f..888d5442 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S @@ -19,7 +19,8 @@ /** */ /**************************************************************************/ /**************************************************************************/ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index 934fbe56..6111ffee 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S @@ -67,7 +67,7 @@ .thumb_func _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index 4b5c490f..e9872072 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -128,7 +128,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -202,7 +202,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -237,7 +237,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -247,7 +249,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/cortex_m7/iar/src/tx_thread_context_restore.s b/ports/cortex_m7/iar/src/tx_thread_context_restore.s index ce482b46..2ebc5f54 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_restore.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function diff --git a/ports/cortex_m7/iar/src/tx_thread_context_save.s b/ports/cortex_m7/iar/src/tx_thread_context_save.s index f0f0dd33..b98aaa74 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_save.s @@ -66,7 +66,7 @@ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s index 518879c2..4cf0a2dd 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s @@ -67,7 +67,7 @@ _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ #ifdef TX_PORT_USE_BASEPRI MRS r0, BASEPRI - LDR r1, =TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI MSR BASEPRI, r1 #else MRS r0, PRIMASK diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s index b23be3d4..65893cb8 100644 --- a/ports/cortex_m7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s @@ -124,7 +124,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -198,7 +198,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -233,7 +233,9 @@ __tx_ts_wait: CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} #endif #ifdef TX_ENABLE_WFI @@ -243,7 +245,9 @@ __tx_ts_wait: #endif #ifdef TX_LOW_POWER + PUSH {r0-r3} BL tx_low_power_exit // Exit low power mode + POP {r0-r3} #endif CPSIE i // Enable interrupts diff --git a/ports/rxv2/ccrx/readme_threadx.txt b/ports/rxv2/ccrx/readme_threadx.txt index 1b00bc72..9aef587e 100644 --- a/ports/rxv2/ccrx/readme_threadx.txt +++ b/ports/rxv2/ccrx/readme_threadx.txt @@ -153,7 +153,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -xx-xx-xxxx Release 6.1.7 changes: +06-02-2021 Release 6.1.7 changes: readme_threadx.txt Updated instructions on how to use execution profile. 04-02-2021 Release 6.1.6 changes: diff --git a/ports/rxv2/iar/readme_threadx.txt b/ports/rxv2/iar/readme_threadx.txt index a31fb8da..dc84aea1 100644 --- a/ports/rxv2/iar/readme_threadx.txt +++ b/ports/rxv2/iar/readme_threadx.txt @@ -146,7 +146,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -xx-xx-xxxx Release 6.1.7 changes: +06-02-2021 Release 6.1.7 changes: readme_threadx.txt Updated instructions on how to use execution profile. 04-02-2021 Release 6.1.6 changes: |