diff options
Diffstat (limited to 'ports_module/cortex-m4/ac6')
10 files changed, 100 insertions, 138 deletions
diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 5dda196d..5d533b5b 100644 --- a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -46,7 +46,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,6 +80,8 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) @@ -105,6 +107,13 @@ _tx_initialize_low_level: LDR r1, =vector_table // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address + /* Enable the cycle count register. */ + +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -112,14 +121,7 @@ _tx_initialize_low_level: LDR r1, [r1] // Pickup reset stack pointer STR r1, [r0] // Save system stack pointer - /* Enable the cycle count register. */ - - LDR r0, =0xE0001000 // Build address of DWT register - LDR r1, [r0] // Pickup the current value - ORR r1, r1, #1 // Set the CYCCNTENA bit - STR r1, [r0] // Enable the cycle count register - - /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES diff --git a/ports_module/cortex-m4/ac6/inc/txm_module_port.h b/ports_module/cortex-m4/ac6/inc/txm_module_port.h index 26b99ba7..c504163b 100644 --- a/ports_module/cortex-m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex-m4/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -96,16 +98,6 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif -/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) - * to reflect your system memory attributes (cache, shareable, memory type). */ -/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 -/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 -/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -160,9 +152,9 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -214,18 +206,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ - ULONG stack_available; \ - __asm("MOV %0, SP" : "=r"(stack_available)); \ - stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ - if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ - (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ - { \ - return(TX_SIZE_ERROR); \ - } - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -340,6 +320,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC6 Version 6.1.2 *"; #endif diff --git a/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S index 455e86b5..639c4208 100644 --- a/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S @@ -2,6 +2,7 @@ /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ +/* This software is licensed under the Microsoft Software License */ /* Terms for Microsoft Azure RTOS. Full text of the license can be */ /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ /* and in the root directory of this software. */ @@ -19,11 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - .global __use_two_region_memory .global __scatterload - .eabi_attribute Tag_ABI_PCS_RO_data, 1 .eabi_attribute Tag_ABI_PCS_R9_use, 1 .eabi_attribute Tag_ABI_PCS_RW_data, 2 @@ -34,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_initialize Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,6 +63,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S index f6b24290..7420808c 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified @@ -29,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -38,10 +37,6 @@ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ /* */ /* INPUT */ /* */ @@ -53,7 +48,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* None */ /* */ /* CALLED BY */ /* */ @@ -64,6 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S index b5f1d070..79938754 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified @@ -29,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -38,9 +37,6 @@ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ /* */ /* INPUT */ /* */ @@ -63,6 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S index d8bde055..10d5f0b2 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -59,6 +59,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -66,15 +68,9 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: - - // Pickup current interrupt lockout posture. - - MRS r1, PRIMASK // Pickup current interrupt lockout - - // Apply the new interrupt posture. - - MSR PRIMASK, r0 // Apply the new interrupt lockout - MOV r0, r1 // Transfer old to return register - BX lr // Return to caller + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S index 0bf01024..41d4b503 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S @@ -23,7 +23,6 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr .global _tx_thread_preempt_disable .global _txm_module_manager_memory_fault_handler .global _txm_module_manager_memory_fault_info @@ -40,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,6 +73,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), arrange */ +/* code to fix link error when */ +/* VFP is enabled, resulting */ +/* in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -94,7 +97,7 @@ _tx_thread_schedule: /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ -#ifdef __ARMVFP__ +#ifdef __ARM_FP MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -126,6 +129,7 @@ __tx_wait_here: /* Memory Exception Handler. */ + .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -194,7 +198,7 @@ UsageFault_Handler: // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR -#ifdef __ARMVFP__ +#ifdef __ARM_FP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit @@ -204,9 +208,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts @@ -229,9 +231,10 @@ UsageFault_Handler: /* Generic context PendSV handler. */ .global PendSV_Handler + .global __tx_PendSVHandler + .syntax unified .thumb_func PendSV_Handler: - .global __tx_PendSVHandler .thumb_func __tx_PendSVHandler: @@ -240,9 +243,7 @@ __tx_PendSVHandler: __tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function @@ -264,7 +265,7 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers -#ifdef __ARMVFP__ +#ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers @@ -295,16 +296,42 @@ __tx_ts_new: CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -316,9 +343,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread entry function to indicate the thread is executing. */ - PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 @@ -345,16 +370,16 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block - LDM r0!,{r2-r9} // Load MPU regions 0-3 - STM r1,{r2-r9} // Store MPU regions 0-3 - LDM r0!,{r2-r9} // Load MPU regions 4-7 - STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU skip_mpu_setup: LDMIA r12!, {LR} // Pickup LR -#ifdef __ARMVFP__ +#ifdef __ARM_FP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers @@ -367,36 +392,6 @@ _skip_vfp_restore: BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait: - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready: - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread - /* SVC Handler. */ @@ -550,20 +545,16 @@ _txm_module_user_mode_exit: NOP // } -#ifdef TX_ENABLE_FPU_SUPPORT - +#ifdef __ARM_FP + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: .global tx_thread_fpu_enable .thumb_func tx_thread_fpu_enable: /* Automatic VPF logic is supported, this function is present only for backward compatibility purposes and therefore simply returns. */ - BX LR // Return to caller - .global tx_thread_fpu_disable - .thumb_func -tx_thread_fpu_disable: - /* Automatic VPF logic is supported, this function is present only for - backward compatibility purposes and therefore simply returns. */ BX LR // Return to caller -#endif +#endif diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S index 1f006f32..ca5be793 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified @@ -29,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -62,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -96,7 +97,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - BIC r2, r2, #0x7 // Align frame + BIC r2, r2, #0x7 // Align frame for 8-byte alignment SUB r2, r2, #68 // Subtract frame size LDR r3, =0xFFFFFFFD // Build initial LR value STR r3, [r2, #0] // Save on the stack diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S index 0fceccd6..8ef8f9fd 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -31,7 +30,6 @@ .global _tx_thread_time_slice .global _tx_timer_expiration_process - .text .align 4 .syntax unified @@ -40,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -50,8 +48,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -75,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -83,8 +82,7 @@ .thumb_func _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -176,7 +174,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -192,7 +189,6 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 73c5793c..4d8f8fc0 100644 --- a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -23,13 +23,12 @@ .text .align 4 .syntax unified - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC6 */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,7 +74,7 @@ _txm_module_manager_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: - Stack Top: + Stack Top: LR Interrupted LR (LR at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 @@ -111,7 +112,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block @@ -138,4 +139,3 @@ _txm_module_manager_thread_stack_build: STR r2, [r0, #8] // Save stack pointer in thread's control block BX lr // Return to caller // } - |