diff options
Diffstat (limited to 'ports_module/cortex-m4/gnu')
15 files changed, 1078 insertions, 1086 deletions
diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx.bat index 7d3e2b9b..e8aa0a1d 100644 --- a/ports_module/cortex-m4/gnu/example_build/build_threadx.bat +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx.bat @@ -1,230 +1,230 @@ del tx.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_schedule.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_system_return.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_context_save.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_context_restore.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_interrupt_control.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_timer_interrupt.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_search.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_high_level.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_kernel_enter.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_kernel_setup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_receive.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_send_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_ceiling_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_cleanup.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_put_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_entry_exit_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_identify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_initialize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_preemption_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_priority_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_relinquish.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_reset.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_sleep.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_analyze.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_error_handler.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_error_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_preempt_check.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_resume.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_terminate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_time_slice.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_time_slice_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_timeout.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_wait_abort.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_time_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_time_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_timer_activate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_timer_change.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_timer_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_timer_deactivate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc 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..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat index bf4af9e6..3c672eb3 100644 --- a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat @@ -1,102 +1,102 @@ del txm.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c -arm-none-eabi-gcc -c -g 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-fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative 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-mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat index 8d24580f..92045b92 100644 --- a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat @@ -1,4 +1,4 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_simulator_startup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb cortexm_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb cortexm_crt0.S arm-none-eabi-ld -A cortex-m4 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat index 37e68d0d..5a71cf8c 100644 --- a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat @@ -1,5 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c arm-none-eabi-ld -A cortex-m4 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map diff --git a/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S index e7bac6a1..25a422d2 100644 --- a/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S @@ -27,12 +27,12 @@ .global _tx_timer_interrupt .global __main .global _vectors - .global __tx_NMIHandler @ NMI - .global __tx_BadHandler @ HardFault - .global __tx_DBGHandler @ Monitor - .global __tx_PendSVHandler @ PendSV - .global __tx_SysTickHandler @ SysTick - .global __tx_IntHandler @ Int 0 + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 SYSTEM_CLOCK = 6000000 SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @@ -45,7 +45,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M4/GNU */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,63 +79,72 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ -//VOID _tx_initialize_low_level(VOID) -//{ +// VOID _tx_initialize_low_level(VOID) +// { .global _tx_initialize_low_level .thumb_func _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ - LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ - STR r1, [r0] @ Setup first unused memory pointer + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =_vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ + +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =_vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer - /* Enable the cycle count register. */ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =_vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ - /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ - MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - MOV r1, #0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control /* Configure handler priorities. */ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF - + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF /* Return to caller. */ + BX lr -//} +// } /* Define shells for each of the unused vectors. */ diff --git a/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S index e2df9b29..a9413251 100644 --- a/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S @@ -21,7 +21,7 @@ __txm_module_preamble: .dc.l 0x02000007 // Module Properties where: // Bits 31-24: Compiler ID // 0 -> IAR - // 1 -> RVDS + // 1 -> ARM // 2 -> GNU // Bits 23-3: Reserved // Bit 2: 0 -> Disable shared/external memory access diff --git a/ports_module/cortex-m4/gnu/inc/txm_module_port.h b/ports_module/cortex-m4/gnu/inc/txm_module_port.h index 107b99f6..554a3aad 100644 --- a/ports_module/cortex-m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex-m4/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -150,9 +152,9 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -318,6 +320,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/GNU Version 6.1.2 *"; #endif diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S index 2101419a..e693ef46 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,87 +1,73 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_thread_system_stack_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_schedule - .global _tx_thread_preempt_disable - .global _tx_execution_isr_exit -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is only needed for legacy applications and it should */ -@/* not be called in any new development on a Cortex-M. */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_context_restore(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: -@ -@ /* Not needed for this port - just return! */ + /* Not needed for this port - just return! */ BX lr -@} +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S index 03fe07ce..9d8ad6a1 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S @@ -1,81 +1,74 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_execution_isr_enter -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is only needed for legacy applications and it should */ -@/* not be called in any new development on a Cortex-M. */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_context_save(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { .global _tx_thread_context_save .thumb_func _tx_thread_context_save: -@ -@ /* Not needed for this port - just return! */ + + /* Not needed for this port - just return! */ BX lr -@} +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 411db298..64a7a486 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,81 +1,76 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ - +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@/* UINT _tx_thread_interrupt_control(UINT new_posture) -{ */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller -@/* Pickup current interrupt lockout posture. */ - - MRS r1, PRIMASK @ Pickup current interrupt lockout - -@/* Apply the new interrupt posture. */ - - MSR PRIMASK, r0 @ Apply the new interrupt lockout - MOV r0, r1 @ Transfer old to return register - BX lr @ Return to caller - -@/* } */ +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S index c7181bcf..5af04818 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S @@ -23,7 +23,6 @@ .global _tx_thread_current_ptr .global _tx_thread_execute_ptr .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr .global _tx_execution_thread_enter .global _tx_execution_thread_exit .global _tx_thread_preempt_disable @@ -38,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,6 +71,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), arrange */ +/* code to fix link error when */ +/* VFP is enabled, resulting */ +/* in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -92,7 +95,7 @@ _tx_thread_schedule: /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ -#ifdef __ARMVFP__ +#ifdef __ARM_PCS_VFP MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -124,6 +127,7 @@ __tx_wait_here: /* Memory Exception Handler. */ + .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -192,7 +196,7 @@ UsageFault_Handler: // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR -#ifdef __ARMVFP__ +#ifdef __ARM_PCS_VFP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit @@ -202,9 +206,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts @@ -239,9 +241,7 @@ __tx_PendSVHandler: __tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function @@ -263,7 +263,7 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers -#ifdef __ARMVFP__ +#ifdef __ARM_PCS_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers @@ -294,16 +294,42 @@ __tx_ts_new: CPSID i // Disable interrupts LDR r1, [r2] // Is there another thread ready to execute? - CBZ r1, __tx_ts_wait // No, skip to the wait processing + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting - /* Yes, another thread is ready for else, make the current thread the new thread. */ + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ STR r1, [r0] // Setup the current thread pointer to the new thread CPSIE i // Enable interrupts /* Increment the thread run count. */ -__tx_ts_restore: LDR r7, [r1, #4] // Pickup the current thread run count LDR r4, =_tx_timer_time_slice // Build address of time-slice variable LDR r5, [r1, #24] // Pickup thread's current time-slice @@ -315,9 +341,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the thread entry function to indicate the thread is executing. */ - PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 @@ -353,7 +377,7 @@ __tx_ts_restore: STR r1, [r0] // Enable MPU skip_mpu_setup: LDMIA r12!, {LR} // Pickup LR -#ifdef __ARMVFP__ +#ifdef __ARM_PCS_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers @@ -366,36 +390,6 @@ _skip_vfp_restore: BX lr // Return to thread! - /* The following is the idle wait processing... in this case, no threads are ready for execution and the - system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts - are disabled to allow use of WFI for waiting for a thread to arrive. */ - -__tx_ts_wait: - CPSID i // Disable interrupts - LDR r1, [r2] // Pickup the next thread to execute pointer - STR r1, [r0] // Store it in the current pointer - CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - CPSIE i // Enable interrupts - B __tx_ts_wait // Loop to continue waiting - - /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are - already in the handler! */ - -__tx_ts_ready: - MOV r7, #0x08000000 // Build clear PendSV value - MOV r8, #0xE000E000 // Build base NVIC address - STR r7, [r8, #0xD04] // Clear any PendSV - - /* Re-enable interrupts and restore new thread. */ - - CPSIE i // Enable interrupts - B __tx_ts_restore // Restore the thread - /* SVC Handler. */ @@ -549,3 +543,17 @@ _txm_module_user_mode_exit: NOP NOP // } + +#ifdef __ARM_PCS_VFP + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + + BX LR // Return to caller + +#endif diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S index 91e51381..c2802386 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,135 +1,136 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function builds a stack frame on the supplied thread's stack. */ -@/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ -@/* thread_ptr Pointer to thread control blk */ -@/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { .global _tx_thread_stack_build .thumb_func _tx_thread_stack_build: -@ -@ -@ /* Build a fake interrupt frame. The form of the fake interrupt stack -@ on the Cortex-M4 should look like the following after it is built: -@ -@ Stack Top: -@ LR Interrupted LR (LR at time of PENDSV) -@ r4 Initial value for r4 -@ r5 Initial value for r5 -@ r6 Initial value for r6 -@ r7 Initial value for r7 -@ r8 Initial value for r8 -@ r9 Initial value for r9 -@ r10 Initial value for r10 -@ r11 Initial value for r11 -@ r0 Initial value for r0 (Hardware stack starts here!!) -@ r1 Initial value for r1 -@ r2 Initial value for r2 -@ r3 Initial value for r3 -@ r12 Initial value for r12 -@ lr Initial value for lr -@ pc Initial value for pc -@ xPSR Initial value for xPSR -@ -@ Stack Bottom: (higher memory address) */ -@ - LDR r2, [r0, #16] @ Pickup end of stack area - BIC r2, r2, #0x7 @ Align frame - SUB r2, r2, #68 @ Subtract frame size - LDR r3, =0xFFFFFFFD @ Build initial LR value - STR r3, [r2, #0] @ Save on the stack -@ -@ /* Actually build the stack frame. */ -@ - MOV r3, #0 @ Build initial register value - STR r3, [r2, #4] @ Store initial r4 - STR r3, [r2, #8] @ Store initial r5 - STR r3, [r2, #12] @ Store initial r6 - STR r3, [r2, #16] @ Store initial r7 - STR r3, [r2, #20] @ Store initial r8 - STR r3, [r2, #24] @ Store initial r9 - STR r3, [r2, #28] @ Store initial r10 - STR r3, [r2, #32] @ Store initial r11 -@ -@ /* Hardware stack follows. */ -@ - STR r3, [r2, #36] @ Store initial r0 - STR r3, [r2, #40] @ Store initial r1 - STR r3, [r2, #44] @ Store initial r2 - STR r3, [r2, #48] @ Store initial r3 - STR r3, [r2, #52] @ Store initial r12 - MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value - STR r3, [r2, #56] @ Store initial lr - STR r1, [r2, #60] @ Store initial pc - MOV r3, #0x01000000 @ Only T-bit need be set - STR r3, [r2, #64] @ Store initial xPSR -@ -@ /* Setup stack pointer. */ -@ thread_ptr -> tx_thread_stack_ptr = r2; -@ - STR r2, [r0, #8] @ Save stack pointer in thread's - @ control block - BX lr @ Return to caller -@} + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S index 32601837..2ffdaab4 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S @@ -1,88 +1,89 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@/* VOID _tx_thread_system_return(VOID) -@{ */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { .thumb_func .global _tx_thread_system_return _tx_thread_system_return: -@ -@ /* Return to real scheduler via PendSV. Note that this routine is often -@ replaced with in-line assembly in tx_port.h to improved performance. */ -@ - MOV r0, #0x10000000 @ Load PENDSVSET bit - MOV r1, #0xE000E000 @ Load NVIC base - STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR - MRS r0, IPSR @ Pickup IPSR - CMP r0, #0 @ Is it a thread returning? - BNE _isr_context @ If ISR, skip interrupt enable - MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK - CPSIE i @ Enable interrupts - MSR PRIMASK, r1 @ Restore original interrupt posture + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture _isr_context: - BX lr @ Return to caller + BX lr // Return to caller -@/* } */ +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S index 0691e893..50202fdb 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,26 +1,25 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Timer */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global _tx_timer_time_slice .global _tx_timer_system_clock .global _tx_timer_current_ptr @@ -30,228 +29,224 @@ .global _tx_timer_expired .global _tx_thread_time_slice .global _tx_timer_expiration_process -@ -@ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt Cortex-M4/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_timer_interrupt(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M4/GNU */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { .global _tx_timer_interrupt .thumb_func _tx_timer_interrupt: -@ -@ /* Upon entry to this routine, it is assumed that context save has already -@ been called, and therefore the compiler scratch registers are available -@ for use. */ -@ -@ /* Increment the system clock. */ -@ _tx_timer_system_clock++; -@ - LDR r1, =_tx_timer_system_clock @ Pickup address of system clock - LDR r0, [r1, #0] @ Pickup system clock - ADD r0, r0, #1 @ Increment system clock - STR r0, [r1, #0] @ Store new system clock -@ -@ /* Test for time-slice expiration. */ -@ if (_tx_timer_time_slice) -@ { -@ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice - LDR r2, [r3, #0] @ Pickup time-slice - CMP r2, #0 @ Is it non-active? - BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing -@ -@ /* Decrement the time_slice. */ -@ _tx_timer_time_slice--; -@ - SUB r2, r2, #1 @ Decrement the time-slice - STR r2, [r3, #0] @ Store new time-slice value -@ -@ /* Check for expiration. */ -@ if (__tx_timer_time_slice == 0) -@ - CMP r2, #0 @ Has it expired? - BNE __tx_timer_no_time_slice @ No, skip expiration processing -@ -@ /* Set the time-slice expired flag. */ -@ _tx_timer_expired_time_slice = TX_TRUE; -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag - MOV r0, #1 @ Build expired value - STR r0, [r3, #0] @ Set time-slice expiration flag -@ -@ } -@ + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -@ -@ /* Test for timer expiration. */ -@ if (*_tx_timer_current_ptr) -@ { -@ - LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address - LDR r0, [r1, #0] @ Pickup current timer - LDR r2, [r0, #0] @ Pickup timer list entry - CMP r2, #0 @ Is there anything in the list? - BEQ __tx_timer_no_timer @ No, just increment the timer -@ -@ /* Set expiration flag. */ -@ _tx_timer_expired = TX_TRUE; -@ - LDR r3, =_tx_timer_expired @ Pickup expiration flag address - MOV r2, #1 @ Build expired value - STR r2, [r3, #0] @ Set expired flag - B __tx_timer_done @ Finished timer processing -@ -@ } -@ else -@ { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -@ -@ /* No timer expired, increment the timer pointer. */ -@ _tx_timer_current_ptr++; -@ - ADD r0, r0, #4 @ Move to next timer -@ -@ /* Check for wrap-around. */ -@ if (_tx_timer_current_ptr == _tx_timer_list_end) -@ - LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end - LDR r2, [r3, #0] @ Pickup list end - CMP r0, r2 @ Are we at list end? - BNE __tx_timer_skip_wrap @ No, skip wrap-around logic -@ -@ /* Wrap to beginning of list. */ -@ _tx_timer_current_ptr = _tx_timer_list_start; -@ - LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start - LDR r0, [r3, #0] @ Set current pointer to list start -@ + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -@ - STR r0, [r1, #0] @ Store new current timer pointer -@ } -@ + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -@ -@ -@ /* See if anything has expired. */ -@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -@ { -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag - LDR r2, [r3, #0] @ Pickup time-slice expired flag - CMP r2, #0 @ Did a time-slice expire? - BNE __tx_something_expired @ If non-zero, time-slice expired - LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag - LDR r0, [r1, #0] @ Pickup timer expired flag - CMP r0, #0 @ Did a timer expire? - BEQ __tx_timer_nothing_expired @ No, nothing expired -@ + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -@ -@ - STMDB sp!, {r0, lr} @ Save the lr register on the stack - @ and save r0 just to keep 8-byte alignment -@ -@ /* Did a timer expire? */ -@ if (_tx_timer_expired) -@ { -@ - LDR r1, =_tx_timer_expired @ Pickup addr of expired flag - LDR r0, [r1, #0] @ Pickup timer expired flag - CMP r0, #0 @ Check for timer expiration - BEQ __tx_timer_dont_activate @ If not set, skip timer activation -@ -@ /* Process timer expiration. */ -@ _tx_timer_expiration_process(); -@ - BL _tx_timer_expiration_process @ Call the timer expiration handling routine -@ -@ } + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -@ -@ /* Did time slice expire? */ -@ if (_tx_timer_expired_time_slice) -@ { -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired - LDR r2, [r3, #0] @ Pickup the actual flag - CMP r2, #0 @ See if the flag is set - BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing -@ -@ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); -@ - BL _tx_thread_time_slice @ Call time-slice processing - LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag - LDR r1, [r0] @ Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic - LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address - LDR r1, [r0] @ Pickup the current thread pointer - LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address - LDR r3, [r2] @ Pickup the execute thread pointer - LDR r0, =0xE000ED04 @ Build address of control register - LDR r2, =0x10000000 @ Build value for PendSV bit - CMP r1, r3 @ Are they the same? - BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed - STR r2, [r0] @ Not the same, issue the PendSV for preemption + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -@ -@ } -@ + + // } + __tx_timer_not_ts_expiration: -@ - LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for - @ the 8-byte stack alignment -@ -@ } -@ + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB @ Complete all memory access - BX lr @ Return to caller -@ -@} + DSB // Complete all memory access + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 62f8f7d3..4eb822cf 100644 --- a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -23,13 +23,12 @@ .text .align 4 .syntax unified - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_stack_build Cortex-M4/MPU/GNU */ -/* 6.1 */ +/* 6.1.2 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +61,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.2 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,7 +74,7 @@ _txm_module_manager_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: - Stack Top: + Stack Top: LR Interrupted LR (LR at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 @@ -111,7 +112,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block @@ -137,3 +138,4 @@ _txm_module_manager_thread_stack_build: STR r2, [r0, #8] // Save stack pointer in thread's control block BX lr // Return to caller +// } |