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-rw-r--r--ports_module/cortex_m33/gnu/example_build/gcc_setup.s42
-rw-r--r--ports_module/cortex_m33/gnu/inc/tx_port.h2
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S15
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S15
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s)0
-rw-r--r--ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.S (renamed from ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s)0
12 files changed, 60 insertions, 14 deletions
diff --git a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s
index 4a729ffe..80ccb19b 100644
--- a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s
+++ b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s
@@ -1,4 +1,6 @@
+// Portions of this file were generated with AI assistance.
+
.text
.align 4
.syntax unified
@@ -71,6 +73,46 @@ got_setup_done:
mov r2, #0
bl crt0_memory_set
+ /* Apply the R_ARM_RELATIVE relocations that target the module data area. */
+
+ ldr r3, =__FLASH_segment_start__ // crt0_memory_copy used r3 as a scratch register
+ ldr r0, =__reldyn_load_start__
+ sub r0,r0,r3
+ add r0,r0,r5
+ ldr r1, =__reldyn_end__
+ sub r1,r1,r3
+ add r1,r1,r5
+
+new_reldyn_setup:
+ cmp r0, r1 // See if there are more relocation entries
+ beq reldyn_setup_done // No, done with the relocations
+ ldr r6, [r0] // Pickup the r_offset field
+ ldr r7, [r0, #4] // Pickup the r_info field
+ add r0, r0, #8 // Move to the next entry
+ uxtb r7, r7 // The relocation type is in the low byte
+ cmp r7, #23 // Is it R_ARM_RELATIVE?
+ bne new_reldyn_setup // No, only R_ARM_RELATIVE is supported
+ cmp r6, r4 // Does it target the code or the data area?
+ blt new_reldyn_setup // The code area is shared and read-only, skip it
+ sub r6, r6, r4 // Compute offset of data area
+ add r6, r6, r9 // Build the address of the word to relocate
+ ldr r7, [r6] // Pickup the link time address stored there
+ cmp r7, #0 // Is it 0?
+ beq new_reldyn_setup // Yes, just skip the adjustment
+ cmp r7, r4 // Is it in the code or data area?
+ blt reldyn_flash_area // If less than, it is a code address
+ sub r7, r7, r4 // Compute offset of data area
+ add r7, r7, r9 // Build address based on the loaded data address
+ b reldyn_built // Finished building address
+reldyn_flash_area:
+ sub r7, r7, r3 // Compute offset of code area
+ add r7, r7, r5 // Build address based on the loaded code address
+reldyn_built:
+ str r7, [r6] // Store the relocated address back
+ b new_reldyn_setup // Continue at the top of the loop
+reldyn_setup_done:
+
+
/* Setup heap - not recommended for Threadx but here for compatibility reasons */
diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h
index bf859fbc..14bc8a19 100644
--- a/ports_module/cortex_m33/gnu/inc/tx_port.h
+++ b/ports_module/cortex_m33/gnu/inc/tx_port.h
@@ -675,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
- "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.1.202602a *";
+ "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.2.202603 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S
index c89394c2..a75d4f11 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S
@@ -8,6 +8,7 @@
*
* SPDX-License-Identifier: MIT
**************************************************************************/
+// Portions of this file were generated with AI assistance.
/**************************************************************************/
@@ -84,25 +85,17 @@ _tx_initialize_low_level:
ADD r1, r1, #4 //
STR r1, [r0] // Setup first unused memory pointer
- /* Setup Vector Table Offset Register. */
- MOV r0, #0xE000E000 // Build address of NVIC registers
- LDR r1, =_vectors // Pickup address of vector table
- STR r1, [r0, #0xD08] // Set vector table address
-
/* Enable the cycle count register. */
LDR r0, =0xE0001000 // Build address of DWT register
LDR r1, [r0] // Pickup the current value
ORR r1, r1, #1 // Set the CYCCNTENA bit
STR r1, [r0] // Enable the cycle count register
- /* Set system stack pointer from vector value. */
- LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
- LDR r1, =_vectors // Pickup address of vector table
- LDR r1, [r1] // Pickup reset stack pointer
- STR r1, [r0] // Save system stack pointer
-
/* Configure SysTick. */
MOV r0, #0xE000E000 // Build address of NVIC registers
+ MOV r1, #0 // Build value for SysTick reset
+ STR r1, [r0, #0x10] // Reset SysTick Control
+ STR r1, [r0, #0x18] // Reset SysTick Counter Value
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] // Setup SysTick Reload Value
MOV r1, #0x7 // Build SysTick Control Enable Value
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.S
index 9ac66244..9ac66244 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.S
index 71d42cde..71d42cde 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.S
index b9083160..b9083160 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.S
index c27e7362..c27e7362 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.S
index 506ddf52..506ddf52 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S
index 16913f57..8b793638 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S
@@ -8,6 +8,7 @@
*
* SPDX-License-Identifier: MIT
**************************************************************************/
+// Portions of this file were generated with AI assistance.
/**************************************************************************/
@@ -204,7 +205,7 @@ BusFault_Handler:
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
#ifdef TX_PORT_USE_BASEPRI
- MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
+ MOV r0, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
@@ -242,7 +243,7 @@ __tx_ts_handler:
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#ifdef TX_PORT_USE_BASEPRI
- MOV r0, 0 // Disable BASEPRI masking (enable interrupts)
+ MOV r0, #0 // Disable BASEPRI masking (enable interrupts)
MSR BASEPRI, r0
#else
CPSIE i // Enable interrupts
@@ -333,9 +334,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
+#ifdef TX_PORT_USE_BASEPRI
+ CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
+ MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
+ MSR BASEPRI, r1 // is still able to wake the processor
+#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
+#ifdef TX_PORT_USE_BASEPRI
+ LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
+ MSR BASEPRI, r1
+ CPSIE i // Clear PRIMASK; a pending interrupt is taken here
+#endif
#endif
#ifdef TX_LOW_POWER
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.S
index 370a18da..370a18da 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.S
index 95d8678f..95d8678f 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.S
diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
index 6c3e0275..6c3e0275 100644
--- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s
+++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.S
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-25 10:00:19 +0000