diff options
Diffstat (limited to 'ports_module/cortex_m7')
22 files changed, 166 insertions, 102 deletions
diff --git a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S index 62d7eb93..fa360335 100644 --- a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -20,7 +21,6 @@ /**************************************************************************/ /**************************************************************************/ - IMPORT _tx_thread_system_stack_ptr IMPORT _tx_initialize_unused_memory IMPORT _tx_thread_context_save IMPORT _tx_thread_context_restore @@ -148,12 +148,6 @@ _tx_initialize_low_level ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =__tx_vectors // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register @@ -161,16 +155,12 @@ _tx_initialize_low_level // ORR r1, r1, #1 // Set the CYCCNTENA bit // STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =__tx_vectors // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index 70b6c5a9..9a009596 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s index 1810905a..3e6b6793 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -206,7 +208,7 @@ MemManage_Handler STR r1, [r0] // Store ICSR DSB // Wait for memory access to complete #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -238,7 +240,7 @@ __tx_ts_handler BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -318,9 +320,19 @@ __tx_ts_wait #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 2837a142..3ec0d153 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -21,7 +22,6 @@ /**************************************************************************/ - .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global _tx_timer_interrupt .global __main @@ -93,19 +93,6 @@ _tx_initialize_low_level: ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =vector_table // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - - /* Set system stack pointer from vector value. */ - - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =vector_table // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Enable the cycle count register. */ LDR r0, =0xE0001000 // Build address of DWT register @@ -116,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch index 7b783402..187beb06 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch @@ -155,7 +155,7 @@ <booleanAttribute key="VFS_ENABLED" value="true"/> <stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/> <stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/> - <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> 	<breakpoint ignorecount="0" threadenabled="no" core_list="" continue="no" verboseBreakpoints="yes" kind="SOURCEPOSITION"> 		<master_location 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debugFile="C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_txm_update/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c" hostFile="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_txm_update\ports_module\cortex-m7\ac6\example_build\sample_threadx_module\sample_threadx_module.c" line="247"/> 	</breakpoint> </breakpoints> "/> + <stringAttribute key="breakpoints" value="<?xml version="1.0" encoding="UTF-8"?> <breakpoints order="ALPHA"> </breakpoints> "/> <listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses"> <listEntry value="<Next Instruction>"/> <listEntry value=""/> diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 2df350e5..9eb0bdf5 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -21,7 +22,6 @@ /**************************************************************************/ - .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global _tx_timer_interrupt .global __main @@ -93,12 +93,6 @@ _tx_initialize_low_level: ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =vector_table // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register @@ -106,16 +100,12 @@ _tx_initialize_low_level: // ORR r1, r1, #1 // Set the CYCCNTENA bit // STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =vector_table // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index 70b6c5a9..9a009596 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index a3126bc7..958a739d 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -217,7 +218,7 @@ UsageFault_Handler: STR r1, [r0] // Store ICSR DSB // Wait for memory access to complete #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -252,7 +253,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -332,9 +333,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index 831c00e4..4071b1a1 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -81,10 +85,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat index c4ae437e..bb55bb6f 100644 --- a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat @@ -1,5 +1,5 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.s arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c -arm-none-eabi-ld -A cortex-m7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map +arm-none-eabi-ld -A cortex-m7 -T sample_threadx_module.ld -pie --no-dynamic-linker txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map diff --git a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s index 4a729ffe..80ccb19b 100644 --- a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s @@ -1,4 +1,6 @@ +// Portions of this file were generated with AI assistance. + .text .align 4 .syntax unified @@ -71,6 +73,46 @@ got_setup_done: mov r2, #0 bl crt0_memory_set + /* Apply the R_ARM_RELATIVE relocations that target the module data area. */ + + ldr r3, =__FLASH_segment_start__ // crt0_memory_copy used r3 as a scratch register + ldr r0, =__reldyn_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__reldyn_end__ + sub r1,r1,r3 + add r1,r1,r5 + +new_reldyn_setup: + cmp r0, r1 // See if there are more relocation entries + beq reldyn_setup_done // No, done with the relocations + ldr r6, [r0] // Pickup the r_offset field + ldr r7, [r0, #4] // Pickup the r_info field + add r0, r0, #8 // Move to the next entry + uxtb r7, r7 // The relocation type is in the low byte + cmp r7, #23 // Is it R_ARM_RELATIVE? + bne new_reldyn_setup // No, only R_ARM_RELATIVE is supported + cmp r6, r4 // Does it target the code or the data area? + blt new_reldyn_setup // The code area is shared and read-only, skip it + sub r6, r6, r4 // Compute offset of data area + add r6, r6, r9 // Build the address of the word to relocate + ldr r7, [r6] // Pickup the link time address stored there + cmp r7, #0 // Is it 0? + beq new_reldyn_setup // Yes, just skip the adjustment + cmp r7, r4 // Is it in the code or data area? + blt reldyn_flash_area // If less than, it is a code address + sub r7, r7, r4 // Compute offset of data area + add r7, r7, r9 // Build address based on the loaded data address + b reldyn_built // Finished building address +reldyn_flash_area: + sub r7, r7, r3 // Compute offset of code area + add r7, r7, r5 // Build address based on the loaded code address +reldyn_built: + str r7, [r6] // Store the relocated address back + b new_reldyn_setup // Continue at the top of the loop +reldyn_setup_done: + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld index 5fa4c680..f77bedda 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld @@ -206,5 +206,13 @@ SECTIONS __data_size__ = __heap_end__ - __RAM_segment_start__; + /* The dynamic linking metadata is not used by the module manager. Discarding + it keeps it out of the binary image produced from this ELF file. */ + + /DISCARD/ : + { + *(.dynamic) + } + } diff --git a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S index e9273cbd..7252f7af 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -21,12 +22,10 @@ /**************************************************************************/ - .global _tx_thread_system_stack_ptr .global _tx_initialize_unused_memory .global __RAM_segment_used_end__ .global _tx_timer_interrupt .global __main - .global _vectors .global __tx_NMIHandler // NMI .global __tx_BadHandler // HardFault .global __tx_DBGHandler // Monitor @@ -92,12 +91,6 @@ _tx_initialize_low_level: ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =_vectors // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register @@ -105,16 +98,12 @@ _tx_initialize_low_level: // ORR r1, r1, #1 // Set the CYCCNTENA bit // STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =_vectors // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index 70b6c5a9..9a009596 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index 571af2ee..0603be2f 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -215,7 +216,7 @@ UsageFault_Handler: STR r1, [r0] // Store ICSR DSB // Wait for memory access to complete #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -250,7 +251,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -330,9 +331,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index ce5a3f46..6eb5a72d 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -73,6 +75,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB #0xF // Ensure memory access is complete + ISB #0xF // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -81,10 +85,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB #0xF // Flush pipeline #endif _isr_context: BX lr // Return to caller diff --git a/ports_module/cortex_m7/iar/example_build/tx.ewp b/ports_module/cortex_m7/iar/example_build/tx.ewp index 7ff6209d..09ad5b2e 100644 --- a/ports_module/cortex_m7/iar/example_build/tx.ewp +++ b/ports_module/cortex_m7/iar/example_build/tx.ewp @@ -1054,7 +1054,7 @@ </option> <option> <name>IarchiveOutput</name> - <state>C:\Users\andrejm\work\git\AzureRTOS\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\tx.a</state> + <state>###Unitialized###</state> </option> </data> </settings> diff --git a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s index 2df2d19f..8c599aef 100644 --- a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ @@ -21,10 +22,8 @@ /**************************************************************************/ - EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt - EXTERN __vector_table EXTERN _tx_execution_isr_enter EXTERN _tx_execution_isr_exit @@ -87,12 +86,6 @@ _tx_initialize_low_level: LDR r1, =__tx_free_memory_start // Build first free address STR r1, [r0] // Setup first unused memory pointer - /* Setup Vector Table Offset Register. */ - - MOV r0, #0xE000E000 // Build address of NVIC registers - LDR r1, =__vector_table // Pickup address of vector table - STR r1, [r0, #0xD08] // Set vector table address - /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register @@ -100,16 +93,12 @@ _tx_initialize_low_level: // ORR r1, r1, #1 // Set the CYCCNTENA bit // STR r1, [r0] // Enable the cycle count register - /* Set system stack pointer from vector value. */ - - LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer - LDR r1, =__vector_table // Pickup address of vector table - LDR r1, [r1] // Pickup reset stack pointer - STR r1, [r0] // Save system stack pointer - /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index 70b6c5a9..9a009596 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -711,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.1.202602a *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.2.202603 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c index 238b485e..ab6c209c 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. /**************************************************************************/ /**************************************************************************/ @@ -270,7 +271,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -287,7 +288,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ @@ -678,7 +679,7 @@ TX_MUTEX *mutex_ptr; mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; /* Check for wrap-around on the next free mutex. */ - if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + if (__tx_iar_file_lock_next_free_mutex >= _MAX_FLOCK) { /* Yes, set the free index back to 0. */ @@ -695,7 +696,7 @@ TX_MUTEX *mutex_ptr; } /* Determine if a free mutex was found. */ - if (i >= _MAX_LOCK) + if (i >= _MAX_FLOCK) { /* Error! No more free mutexes! */ diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index d38c8df7..5e2a95ad 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -9,6 +9,8 @@ * SPDX-License-Identifier: MIT **************************************************************************/ +// Portions of this file were generated with AI assistance. + /**************************************************************************/ /**************************************************************************/ @@ -207,7 +209,7 @@ UsageFault_Handler: STR r1, [r0] // Store ICSR DSB // Wait for memory access to complete #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -239,7 +241,7 @@ __tx_ts_handler: BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR #ifdef TX_PORT_USE_BASEPRI - MOV r0, 0 // Disable BASEPRI masking (enable interrupts) + MOV r0, #0 // Disable BASEPRI masking (enable interrupts) MSR BASEPRI, r0 #else CPSIE i // Enable interrupts @@ -319,9 +321,19 @@ __tx_ts_wait: #endif #ifdef TX_ENABLE_WFI +#ifdef TX_PORT_USE_BASEPRI + CPSID i // Mask every interrupt with PRIMASK, which WFI ignores + MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it + MSR BASEPRI, r1 // is still able to wake the processor +#endif DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed +#ifdef TX_PORT_USE_BASEPRI + LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask + MSR BASEPRI, r1 + CPSIE i // Clear PRIMASK; a pending interrupt is taken here +#endif #endif #ifdef TX_LOW_POWER diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s index 0cef80c6..ab1f05ba 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s @@ -1,16 +1,19 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (c) 2026-present Eclipse ThreadX contributors - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ +;*************************************************************************** +;* Copyright (c) 2024 Microsoft Corporation +;* Copyright (c) 2026-present Eclipse ThreadX contributors +;* +;* This program and the accompanying materials are made available under the +;* terms of the MIT License which is available at +;* https://opensource.org/licenses/MIT. +;* +;* SPDX-License-Identifier: MIT +;************************************************************************** +; Portions of this file were generated with AI assistance. + + +;************************************************************************** -/**************************************************************************/ /**************************************************************************/ /** */ /** ThreadX Component */ @@ -70,6 +73,8 @@ _tx_thread_system_return: MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB SY // Ensure memory access is complete + ISB SY // Flush pipeline MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable @@ -78,10 +83,12 @@ _tx_thread_system_return: MOV r0, #0 MSR BASEPRI, r0 // Enable interrupts MSR BASEPRI, r1 // Restore original interrupt posture + ISB SY // Flush pipeline #else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture + ISB SY // Flush pipeline #endif _isr_context: BX lr // Return to caller |