diff options
Diffstat (limited to 'ports_module')
381 files changed, 8116 insertions, 7251 deletions
diff --git a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s index 9621aea4..ff3a5ad4 100644 --- a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -148,7 +148,7 @@ Reset_Vector ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -549,7 +549,7 @@ __tx_fiq_handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ diff --git a/ports_module/cortex_a7/ac5/inc/txm_module_port.h b/ports_module/cortex_a7/ac5/inc/txm_module_port.h index fd534dc7..a66673df 100644 --- a/ports_module/cortex_a7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_a7/ac5/inc/txm_module_port.h @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s index f0ea4f61..fa962a6e 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c index 7504c7fe..1a33f7cd 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -92,7 +92,7 @@ VOID __user_setup_stackheap(VOID){return;} /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s index f67f1f01..65e74ba0 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s @@ -94,7 +94,7 @@ DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s index a9df5df8..e7ae48e0 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s @@ -97,7 +97,7 @@ THUMB_MASK EQU 0x20 ; Thumb bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s index 212b51f2..0e06114e 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s @@ -80,7 +80,7 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index cc2842a6..7f70c73b 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 6209a2ab..471d4b90 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -69,7 +69,7 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) @@ -163,7 +163,7 @@ UINT pool_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance) @@ -224,7 +224,7 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index ad346533..98fe2ff1 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 4af6367b..ada540be 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c index eeeb0774..582ac55e 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c @@ -93,7 +93,7 @@ __align(1024) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGE /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 647efe2f..02ed0e58 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -66,7 +66,7 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) @@ -123,7 +123,7 @@ ULONG translation; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance) @@ -183,7 +183,7 @@ UINT i = 1; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) @@ -230,7 +230,7 @@ VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index ed02093e..1f936703 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -78,7 +78,7 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 66b6c4d0..55182b25 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -61,7 +61,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _txm_module_manager_user_mode_entry diff --git a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx index cb51db51..2614df9e 100644 --- a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx +++ b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx @@ -2947,6 +2947,18 @@ <RteFlg>0</RteFlg> <bShared>0</bShared> </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>232</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\module_manager\src\tx_thread_secure_stack_initialize.S</PathWithFileName> + <FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> </Group> <Group> diff --git a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx index 56fc195b..cdf3f904 100644 --- a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx +++ b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvprojx @@ -1538,6 +1538,11 @@ <FileType>1</FileType> <FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath> </File> + <File> + <FileName>tx_thread_secure_stack_initialize.S</FileName> + <FileType>2</FileType> + <FilePath>..\module_manager\src\tx_thread_secure_stack_initialize.S</FilePath> + </File> </Files> </Group> <Group> diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 4d3bdc0f..bc55de5c 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -300,8 +300,8 @@ UINT status; while(1) { /* Test external memory sharing. */ - *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - *(ULONG *)0x20040004 = 0x01010101; + // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + // *(ULONG *)0x20040004 = 0x01010101; /* Increment the thread counter. */ thread_2_counter++; diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 3ea33abb..81dc7f36 100644 --- a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -29,7 +29,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) STACK_SIZE = 0x00000400 HEAP_SIZE = 0x00000000 - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -96,8 +95,7 @@ _tx_initialize_low_level: LDR r1, =__Vectors // Pickup address of vector table STR r1, [r0] // Set vector table address -// /* Enable the cycle count register. */ -// + /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index 76a4444b..aa34ec45 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -68,7 +68,6 @@ #include <stdlib.h> #include <string.h> #include <arm_compat.h> -#include "ARMCM23_TZ.h" /* For intrinsic functions. */ /* Define ThreadX basic types for this port. */ diff --git a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S index b2989990..5a1efa6f 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S index fefeb7b0..2b45d9dc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S index 7a24fffd..16aae2b6 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S index d99f1713..ca010871 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S index b03ad941..64a5c8ca 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S index 2a39b955..67fe291e 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -21,6 +21,10 @@ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -71,29 +75,24 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -221,19 +220,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -246,18 +244,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -339,7 +337,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -379,6 +377,8 @@ _skip_secure_restore: CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup // Initialize loop to configure MPU registers + // Order doesn't matter, so txm_module_instance_mpu_registers[0] + // will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0. MOVS r3, #0x64 // Index of MPU register settings in thread control block ADD r0, r0, r3 // Build address of MPU register start in thread control block MOVS r5, #0 // Select region 0 @@ -416,7 +416,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ .section .text .balign 4 @@ -430,10 +429,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -554,14 +553,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -605,7 +604,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c index b4679878..8941a705 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Modified comment(s), and */ +/* changed name, execute in */ +/* handler mode, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -294,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -379,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index de7098e7..e43051dc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -66,7 +66,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_allocate + .global _tx_thread_secure_stack_allocate .global _tx_alloc_return .thumb_func .type _tx_thread_secure_stack_allocate, function @@ -80,7 +80,6 @@ _tx_alloc_return: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S index 837dba7e..110bf0f5 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -64,7 +64,7 @@ .balign 4 .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 - .global _tx_thread_secure_stack_free + .global _tx_thread_secure_stack_free .global _tx_free_return .thumb_func .type _tx_thread_secure_stack_free, function @@ -78,7 +78,6 @@ _tx_free_return: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S new file mode 100644 index 00000000..c2f9bf31 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to initialize a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* none */ +/* */ +/* OUTPUT */ +/* */ +/* none */ +/* */ +/* CALLS */ +/* */ +/* SVC 3 */ +/* */ +/* CALLED BY */ +/* */ +/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_initialize + .thumb_func +.type _tx_thread_secure_stack_initialize, function +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S index 5a95a14f..4b4f443d 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S index 175a9109..749b0fc1 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S index fdfcdcc5..81df88f7 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h index 976f32be..26a608a6 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S index 14d772fb..084635a3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs Interrupt Service Routines */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S index 25050678..cf58aabd 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,11 +47,11 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ -/* None */ +/* ISRs */ /* */ /* RELEASE HISTORY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S index 4f05f3ff..b80112b3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -68,11 +68,9 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S index 3a1fc9f6..2ee36199 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S index 696c227b..3812e0d3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S index 98caf079..c60919ff 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -71,29 +71,24 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -221,19 +216,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -246,18 +240,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -339,7 +333,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -418,7 +412,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ .section .text .balign 4 @@ -432,10 +425,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -556,14 +549,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -607,7 +600,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c index 72bc05f8..8f22bb90 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -61,8 +61,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ -/* 6.1.3 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -77,7 +77,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -94,27 +94,40 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), and */ -/* fixed M23 GCC build, */ -/* resulting in version 6.1.3 */ +/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* name, execute in handler */ +/* mode, disable optimization, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ -__attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +__attribute__((cmse_nonsecure_entry, optimize(0))) +UINT _tx_thread_secure_mode_stack_initialize(void) { - ULONG control; - - /* Set secure mode to use PSP. */ - asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ - control |= 2; /* Use PSP. */ - asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - asm volatile("MSR PSPLIM, %0" :: "r" (0)); - asm volatile("MSR PSP, %0" :: "r" (0)); - - return; +UINT status; +ULONG control; +ULONG ipsr; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ + control |= 2; /* Use PSP. */ + asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + status = TX_SUCCESS; + } + return status; } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1dfbc482..90427e36 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -80,7 +80,6 @@ _tx_alloc_return: BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _alloc_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S index cfe400fa..da5026d5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -55,7 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -78,7 +78,6 @@ _tx_free_return: BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts #else - // Executing in single mode - this function is not needed. MOVS r0, #0xFF // Feature not enabled #endif _free_return_interrupt_enabled: diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S index 704c5dfd..bd9fe738 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S index 7aa911b0..cf3536d5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S @@ -71,7 +71,7 @@ .thumb_func .type _tx_thread_system_return, function _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often + /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ LDR r0, =0x10000000 // Load PENDSVSET bit diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S index 0e2ea836..7b42d195 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -80,8 +79,7 @@ _tx_timer_interrupt: /* Increment the system clock. */ // _tx_timer_system_clock++; - MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock - MOVT r1, #:upper16:_tx_timer_system_clock + LDR r1, =_tx_timer_system_clock // Pickup address of system clock LDR r0, [r1, #0] // Pickup system clock ADDS r0, r0, #1 // Increment system clock STR r0, [r1, #0] // Store new system clock @@ -90,28 +88,27 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice - MOVT r3, #:upper16:_tx_timer_time_slice + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUBS r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOVW r0, #1 // Build expired value STR r0, [r3, #0] // Set time-slice expiration flag @@ -123,18 +120,16 @@ __tx_timer_no_time_slice: // if (*_tx_timer_current_ptr) // { - MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address - MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address LDR r0, [r1, #0] // Pickup current timer LDR r2, [r0, #0] // Pickup timer list entry CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; - MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address - MOVT r3, #:upper16:_tx_timer_expired + LDR r3, =_tx_timer_expired // Pickup expiration flag address MOVW r2, #1 // Build expired value STR r2, [r3, #0] // Set expired flag B __tx_timer_done // Finished timer processing @@ -144,25 +139,23 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADDS r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) - MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end - MOVT r3, #:upper16:_tx_timer_list_end + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; - MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start - MOVT r3, #:upper16:_tx_timer_list_start + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start __tx_timer_skip_wrap: @@ -172,18 +165,15 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag LDR r2, [r3, #0] // Pickup time-slice expired flag CBNZ r2, __tx_something_expired // Did a time-slice expire? // If non-zero, time-slice expired - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_nothing_expired // Did a timer expire? // No, nothing expired @@ -197,14 +187,13 @@ __tx_something_expired: // if (_tx_timer_expired) // { - MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag - MOVT r1, #:upper16:_tx_timer_expired + LDR r1, =_tx_timer_expired // Pickup addr of expired flag LDR r0, [r1, #0] // Pickup timer expired flag CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -215,28 +204,21 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired - MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR r2, [r3, #0] // Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing - MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag - MOVT r0, #:upper16:_tx_thread_preempt_disable - + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag LDR r1, [r0] // Is the preempt disable flag set? CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic - MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address - MOVT r0, #:upper16:_tx_thread_current_ptr - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r1, [r0] // Pickup the current thread pointer - MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address - MOVT r2, #:upper16:_tx_thread_execute_ptr - + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register LDR r2, =0x10000000 // Build value for PendSV bit @@ -248,8 +230,8 @@ __tx_timer_skip_time_slice: __tx_timer_not_ts_expiration: - POP {r0, r1} // Recover lr register (r0 is just there for - MOV lr, r1 // the 8-byte stack alignment + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment // } @@ -257,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s index 92a5f4d2..6f57db2f 100644 --- a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,135 +27,123 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -164,40 +151,48 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0, r1} MOV lr, r1 BX lr -; } - +// } PUBLIC HardFault_Handler HardFault_Handler: - ; A stack overflow will trigger a hardfault. - ; There is no CFSR in M23, so we will not try to - ; determine if the fault is caused by a stack overflow - ; or some other condition. + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. B HardFault_Handler diff --git a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s deleted file mode 100644 index 92a5f4d2..00000000 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s +++ /dev/null @@ -1,204 +0,0 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_initialize_unused_memory - EXTERN _tx_timer_interrupt - EXTERN __main - EXTERN __vector_table - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_stack_error_handler -; -; -SYSTEM_CLOCK EQU 96000000 -SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; - RSEG FREE_MEM:DATA - PUBLIC __tx_free_memory_start -__tx_free_memory_start - DS32 4 -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ - PUBLIC _tx_initialize_low_level -_tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; - CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - LDR r0, =0xE000ED08 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD18 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD1C ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - LDR r0, =0xE000E000 ; Build address of NVIC registers - LDR r2, =0xD20 ; - ADD r0, r0, r2 ; - STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; - BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; - PUBLIC __tx_BadHandler -__tx_BadHandler: - B __tx_BadHandler - - - PUBLIC __tx_IntHandler -__tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - - POP {r0, r1} - MOV lr, r1 - BX lr -; } - - - PUBLIC __tx_SysTickHandler - PUBLIC SysTick_Handler -SysTick_Handler: -__tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) - BL _tx_timer_interrupt - POP {r0, r1} - MOV lr, r1 - BX lr -; } - - - PUBLIC HardFault_Handler -HardFault_Handler: - ; A stack overflow will trigger a hardfault. - ; There is no CFSR in M23, so we will not try to - ; determine if the fault is caused by a stack overflow - ; or some other condition. - B HardFault_Handler - - - END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s index 48300c4d..81fa6815 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_exit SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s index f666d4a4..2ad3e476 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s @@ -1,72 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_execution_isr_enter SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is not needed for Cortex-M. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* None */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { PUBLIC _tx_thread_context_save _tx_thread_context_save: -; -; /* Return to interrupt processing. */ -; + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s index 83381d72..d9ee6e88 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,77 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s index 41ad894f..010d3331 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,76 +1,72 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ MRS r0, PRIMASK CPSID i BX lr -; -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s index dd1c2985..054d3d8e 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,75 +1,71 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: -; -; /* Restore previous interrupt lockout posture. */ -; + /* Restore previous interrupt lockout posture. */ MSR PRIMASK, r0 BX lr -; -;} +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s index 53bda596..e523070f 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -81,29 +81,24 @@ // { PUBLIC _tx_thread_schedule _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOVW r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - LDR r0, =0x10000000 // Load PENDSVSET bit LDR r1, =0xE000ED04 // Load ICSR address STR r0, [r1] // Set PENDSVBIT in ICSR @@ -222,19 +217,18 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, r1} // Recover LR - MOV lr, r1 + MOV lr, r1 // CPSIE i // Enable interrupts #endif - + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address - MOVW r3, #0 // Build NULL value LDR r1, [r0] // Pickup current thread pointer @@ -247,18 +241,18 @@ __tx_ts_handler: STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) SUBS r3, r3, #16 // Allocate stack space - STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) - MOV r4, r8 // - MOV r5, r9 // - MOV r6, r10 // - MOV r7, r11 // + STM r3!, {r4-r7} // Save r4-r7 (M4 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // Copy r8-r11 to multisave registers + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 SUBS r3, r3, #32 // Allocate stack space - STM r3!, {r4-r7} // + STM r3!, {r4-r7} // Save r8-r11 SUBS r3, r3, #20 // Allocate stack space - MOV r5, lr // - STR r5, [r3] // Save LR on the stack + MOV r5, lr // Copy lr to saveable register + STR r5, [r3] // Save lr on the stack STR r3, [r1, #8] // Save the thread stack pointer - + #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) // Save secure context LDR r5, =0xC4 // Secure stack index offset @@ -340,7 +334,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -419,7 +413,6 @@ skip_mpu_setup: BX lr // Return to thread! - /* SVC Handler. */ PUBLIC SVC_Handler SVC_Handler: @@ -427,10 +420,10 @@ SVC_Handler: MOVS r1, #0x04 TST r1, r0 // Determine return stack from EXC_RETURN bit 2 BEQ _tx_load_msp - MRS r0, PSP // Get PSP + MRS r0, PSP // Get PSP if return stack is PSP B _tx_get_svc _tx_load_msp: - MRS r0, MSP // Get MSP + MRS r0, MSP // Get MSP if return stack is MSP _tx_get_svc: LDR r1, [r0,#24] // Load saved PC from stack LDR r3, =-2 @@ -451,7 +444,7 @@ _tx_get_svc: /* At this point we have an SVC 3, which means we are entering the kernel from a module thread with user mode selected. */ - LDR r2, =_txm_module_priv // Load address of where we should have come from + LDR r2, =_txm_module_priv-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_entry? BEQ _tx_entry_continue // If no (not equal), then... BX lr // return from where we came. @@ -514,7 +507,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + LDR r2, =_txm_module_user_mode_exit-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_exit? BEQ _tx_exit_continue // If no (not equal), then... BX lr // return from where we came. @@ -551,14 +544,14 @@ _tx_exit_continue: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} // Get r0, r1 from kernel stack - STM r0!,{r1-r2} // Insert r0, r1 into thread stack - LDM r3!,{r1-r2} // Get r2, r3 from kernel stack - STM r0!,{r1-r2} // Insert r2, r3 into thread stack - LDM r3!,{r1-r2} // Get r12, lr from kernel stack - STM r0!,{r1-r2} // Insert r12, lr into thread stack - LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack - STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUBS r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -576,7 +569,7 @@ _tx_skip_kernel_stack_exit: #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) _tx_svc_secure_alloc: - LDR r2, =_tx_alloc_return // Load address of where we should have come from + LDR r2, =_tx_alloc_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? BEQ _tx_alloc_continue // If no (not equal), then... BX lr // return from where we came. @@ -590,7 +583,7 @@ _tx_alloc_continue: BX lr _tx_svc_secure_free: - LDR r2, =_tx_free_return // Load address of where we should have come from + LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? BEQ _tx_free_continue // If no (not equal), then... BX lr // return from where we came. @@ -602,7 +595,7 @@ _tx_free_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c index d7e96333..1bb31a36 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M23/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Modified comment(s), changed */ +/* name, execute in handler */ +/* mode, disable optimization, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -294,7 +308,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -379,7 +393,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 9ae3dcdb..b88e9f4c 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,82 +1,82 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to allocate a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* stack_size Size of secure stack to */ -;/* allocate */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { EXPORT _tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 1 - CMP r3, #0 ; If interrupts enabled, just return + EXPORT _tx_alloc_return +_tx_alloc_return: + CMP r3, #0 // If interrupts enabled, just return BEQ _alloc_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif -_alloc_return_interrupt_enabled +_alloc_return_interrupt_enabled: BX lr - END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s index b8e5bef8..f4606d46 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,79 +1,80 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_secure_stack_free Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function enters the SVC handler to free a secure stack. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Thread control block pointer */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* status Actual completion status */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 2 */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { EXPORT _tx_thread_secure_stack_free _tx_thread_secure_stack_free: #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) - MRS r3, PRIMASK ; Save interrupt mask - CPSIE i ; Enable interrupts for SVC call + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call SVC 2 - CMP r3, #0 ; If interrupts enabled, just return + EXPORT _tx_free_return +_tx_free_return: + CMP r3, #0 // If interrupts enabled, just return BEQ _free_return_interrupt_enabled - CPSID i ; Otherwise, disable interrupts + CPSID i // Otherwise, disable interrupts #else - MOV32 r0, #0xFF ; Feature not enabled + MOVS r0, #0xFF // Feature not enabled #endif -_free_return_interrupt_enabled +_free_return_interrupt_enabled: BX lr END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s index 6525df4a..204be424 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s @@ -1,138 +1,136 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M23 should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - MOVS r3, #0x7 ; - BICS r2, r2, r3 ; Align frame for 8-byte alignment - SUBS r2, r2, #68 ; Subtract frame size + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE - LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode #else - LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP #endif - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r8 - STR r3, [r2, #8] ; Store initial r9 - STR r3, [r2, #12] ; Store initial r10 - STR r3, [r2, #16] ; Store initial r11 - STR r3, [r2, #20] ; Store initial r4 - STR r3, [r2, #24] ; Store initial r5 - STR r3, [r2, #28] ; Store initial r6 - STR r3, [r2, #32] ; Store initial r7 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - LDR r3, =0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c index ef98240c..8e3cff23 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c index ffd78d08..75ad1f32 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s index 1afb41f6..4c977e88 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s @@ -1,87 +1,84 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - LDR r0, =0x10000000 ; Load PENDSVSET bit - LDR r1, =0xE000ED04 ; Load ICSR address - STR r0, [r1] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture _isr_context: - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s index 89e185b3..df397a64 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock EXTERN _tx_timer_current_ptr @@ -33,224 +32,220 @@ EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_preempt_disable -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M23/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* the expiration functions are called. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { PUBLIC _tx_timer_interrupt _tx_timer_interrupt: -; -; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADDS r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUBS r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADDS r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -; -; } -; + // } + __tx_timer_not_ts_expiration: -; - POP {r0, r1} ; Recover lr register (r0 is just there for - MOV lr, r1 ; the 8-byte stack alignment -; -; } -; + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 35482b6c..9e985efa 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c index 950e8ec0..c3ef9577 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S index 246c7010..a3ae9835 100644 --- a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S @@ -150,7 +150,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index 667db1e4..9c2bda5a 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -104,16 +104,6 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif -/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) - * to reflect your system memory attributes (cache, shareable, memory type). */ -/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 -/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 -/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -164,13 +154,13 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ +/* Define INLINE_DECLARE to inline for AC5 compiler. */ #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -337,7 +327,7 @@ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1.8 *"; #endif diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S index 80137e06..46343731 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.S @@ -1,97 +1,94 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + IMPORT __use_two_region_memory IMPORT __scatterload IMPORT txm_heap AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_initialize Cortex-M3/MPU/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function initializes the module c runtime. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* __scatterload Initialize C runtime */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _txm_module_thread_shell_entry Start module thread */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _txm_module_initialize(VOID) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_initialize(VOID) EXPORT _txm_module_initialize _txm_module_initialize - PUSH {r4-r12,lr} ; Save dregs and LR + PUSH {r4-r12,lr} // Save dregs and LR + + B __scatterload // Call ARM func to initialize variables - B __scatterload ; Call ARM func to initialize variables -; -;/* Override __rt_exit function. */ -; +/* Override __rt_exit function. */ + EXPORT __rt_exit __rt_exit - POP {r4-r12,lr} ; Restore dregs and LR - BX lr ; Return to caller -; -; -; + POP {r4-r12,lr} // Restore dregs and LR + BX lr // Return to caller + EXPORT __user_setup_stackheap - ; returns heap start address in R0 - ; returns heap end address in R2 - ; does not touch SP, it is already set up before the module runs + // returns heap start address in R0 + // returns heap end address in R2 + // does not touch SP, it is already set up before the module runs __user_setup_stackheap - LDR r1, _tx_heap_offset ; load heap offset - ADD r0, r9, r1 ; calculate heap base address - MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size - ADD r2, r2, r0 ; calculate heap end address + LDR r1, _tx_heap_offset // load heap offset + ADD r0, r9, r1 // calculate heap base address + MOV r2, #TXM_MODULE_HEAP_SIZE // load heap size + ADD r2, r2, r0 // calculate heap end address BX lr ALIGN 4 @@ -101,9 +98,9 @@ _tx_heap_offset IMPORT txm_heap [DATA] -; -; Dummy main function -; + +// Dummy main function + AREA section_main, CODE, READONLY, ALIGN=2 EXPORT main main diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c index fdd17ff4..0dc4f51e 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -90,7 +90,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S index 14b1da0e..1159ea66 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.S @@ -1,91 +1,83 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit - ENDIF -; -; +#endif + AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is only needed for legacy applications and it should */ -;/* not be called in any new development on a Cortex-M. */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { EXPORT _tx_thread_context_restore _tx_thread_context_restore - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR exit function to indicate an ISR is complete. */ -; - PUSH {r0,lr} ; Save ISR lr - BL _tx_execution_isr_exit ; Call the ISR exit function - POP {r0,lr} ; Restore ISR lr - ENDIF -; - POP {lr} + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr -;} +// } ALIGN LTORG END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S index ae21c768..d8ee75a4 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.S @@ -1,91 +1,85 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter - ENDIF -; -; +#endif + AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is only needed for legacy applications and it should */ -;/* not be called in any new development on a Cortex-M. */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { EXPORT _tx_thread_context_save _tx_thread_context_save - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR enter function to indicate an ISR is executing. */ -; - PUSH {r0, lr} ; Save ISR lr - BL _tx_execution_isr_enter ; Call the ISR enter function - POP {r0, lr} ; Recover ISR lr - ENDIF -; -; /* Return to interrupt processing. */ -; - BX lr ; Return to interrupt processing caller -;} + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + + BX lr +// } ALIGN LTORG END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S index 3c0f1768..4c5e1c33 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -1,76 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { EXPORT _tx_thread_interrupt_control _tx_thread_interrupt_control -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S index d66a11f0..88e6a864 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -1,75 +1,77 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { EXPORT _tx_thread_interrupt_disable _tx_thread_interrupt_disable -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr -; -;} +// } END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S index df65a539..22340c21 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -1,74 +1,75 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { EXPORT _tx_thread_interrupt_restore _tx_thread_interrupt_restore -; -; /* Restore previous interrupt lockout posture. */ -; + + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr -; -;} +// } END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S index 4194d69c..a749235a 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.S @@ -1,519 +1,494 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_thread_preempt_disable +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit - ENDIF - IMPORT _tx_thread_preempt_disable +#endif IMPORT _txm_module_manager_memory_fault_handler IMPORT _txm_module_manager_memory_fault_info - IMPORT _txm_module_priv - IMPORT _txm_module_user_mode_exit -; -; + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit + AREA ||.text||, CODE, READONLY THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M3/MPU/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_schedule(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { EXPORT _tx_thread_schedule _tx_thread_schedule -; -; /* This function should only ever be called on Cortex-M -; from the first schedule request. Subsequent scheduling occurs -; from the PendSV handling routines below. */ -; -; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; - MOV r0, #0 ; Build value for TX_FALSE - LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag - STR r0, [r2, #0] ; Clear preempt disable flag -; -; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ -; - IF :DEF: __ARMVFP__ - MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit - MSR CONTROL, r0 ; Setup new CONTROL register - ENDIF -; -; /* Enable memory fault registers. */ -; - LDR r0, =0xE000ED24 ; Build SHCSR address - LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; -; -; /* Enable interrupts */ -; + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ CPSIE i -; -; /* Enter the scheduler for the first time. */ -; - MOV r0, #0x10000000 ; Load PENDSVSET bit - MOV r1, #0xE000E000 ; Load NVIC base - STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - DSB ; Complete all memory accesses - ISB ; Flush pipeline -; /* Wait here for the PendSV to take place. */ + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ __tx_wait_here - B __tx_wait_here ; Wait for the PendSV to happen -;} -; + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ -; -; /* Memory Exception Handler. */ -; EXPORT MemManage_Handler MemManage_Handler -;{ - CPSID i ; Disable interrupts -; -; /* Now pickup and store all the fault related information. */ -; - LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct - LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - STR r1, [r12, #0] ; Save current thread pointer in fault info structure - LDR r0, =0xE000ED24 ; Build SHCSR address - LDR r1, [r0] ; Pickup SHCSR - STR r1, [r12, #8] ; Save SHCSR - LDR r0, =0xE000ED28 ; Build CFSR address - LDR r1, [r0] ; Pickup CFSR - STR r1, [r12, #12] ; Save CFSR - LDR r0, =0xE000ED34 ; Build MMFAR address - LDR r1, [r0] ; Pickup MMFAR - STR r1, [r12, #16] ; Save MMFAR - LDR r0, =0xE000ED38 ; Build BFAR address - LDR r1, [r0] ; Pickup BFAR - STR r1, [r12, #20] ; Save BFAR - MRS r0, CONTROL ; Pickup current CONTROL register - STR r0, [r12, #24] ; Save CONTROL - MRS r1, PSP ; Pickup thread stack pointer - STR r1, [r12, #28] ; Save thread stack pointer - LDR r0, [r1] ; Pickup saved r0 - STR r0, [r12, #32] ; Save r0 - LDR r0, [r1, #4] ; Pickup saved r1 - STR r0, [r12, #36] ; Save r1 - STR r2, [r12, #40] ; Save r2 - STR r3, [r12, #44] ; Save r3 - STR r4, [r12, #48] ; Save r4 - STR r5, [r12, #52] ; Save r5 - STR r6, [r12, #56] ; Save r6 - STR r7, [r12, #60] ; Save r7 - STR r8, [r12, #64] ; Save r8 - STR r9, [r12, #68] ; Save r9 - STR r10,[r12, #72] ; Save r10 - STR r11,[r12, #76] ; Save r11 - LDR r0, [r1, #16] ; Pickup saved r12 - STR r0, [r12, #80] ; Save r12 - LDR r0, [r1, #20] ; Pickup saved lr - STR r0, [r12, #84] ; Save lr - LDR r0, [r1, #24] ; Pickup instruction address at point of fault - STR r0, [r12, #4] ; Save point of fault - LDR r0, [r1, #28] ; Pickup xPSR - STR r0, [r12, #88] ; Save xPSR + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ - MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit - MSR CONTROL, r0 ; Setup new CONTROL register + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR - LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) - LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: - ; Bit 0 = 1 -> Instruction address violation - ; Bit 1 = 1 -> Load/store address violation - ; Bit 7 = 1 -> MMFAR is valid - STRB r1, [r0] ; Clear the MMFSR + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register - IF :DEF: __ARMVFP__ - LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address - LDR r1, [r0] ; Load FPCCR - BIC r1, r1, #1 ; Clear the lazy preservation active bit - STR r1, [r0] ; Store the value - ENDIF + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR - BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread exit function to indicate the thread is no longer executing. */ -; - CPSID i ; Disable interrupts - BL _tx_execution_thread_exit ; Call the thread exit function - CPSIE i ; Enable interrupts - ENDIF +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif - MOV r1, #0 ; Build NULL value - LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer - STR r1, [r0] ; Clear current thread pointer + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer - ; Return from MemManage_Handler exception - LDR r0, =0xE000ED04 ; Load ICSR - LDR r1, =0x10000000 ; Set PENDSVSET bit - STR r1, [r0] ; Store ICSR - DSB ; Wait for memory access to complete - CPSIE i ; Enable interrupts - MOV lr, #0xFFFFFFFD ; Load exception return code - BX lr ; Return from exception -;} + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ -; -; /* Generic context PendSV handler. */ -; EXPORT PendSV_Handler EXPORT __tx_PendSVHandler PendSV_Handler __tx_PendSVHandler -; -; /* Get current thread value and new thread pointer. */ -; + + /* Get current thread value and new thread pointer. */ + __tx_ts_handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread exit function to indicate the thread is no longer executing. */ -; - CPSID i ; Disable interrupts - PUSH {r0, lr} ; Save LR (and r0 just for alignment) - BL _tx_execution_thread_exit ; Call the thread exit function - POP {r0, lr} ; Recover LR - CPSIE i ; Enable interrupts - ENDIF - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - MOV r3, #0 ; Build NULL value - LDR r1, [r0] ; Pickup current thread pointer -; -; /* Determine if there is a current thread to finish preserving. */ -; - CBZ r1, __tx_ts_new ; If NULL, skip preservation -; -; /* Recover PSP and preserve current thread context. */ -; - STR r3, [r0] ; Set _tx_thread_current_ptr to NULL - MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) - STMDB r12!, {r4-r11} ; Save its remaining registers - IF :DEF: __ARMVFP__ - TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_save - VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers -_skip_vfp_save - ENDIF - MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable - STMDB r12!, {LR} ; Save LR on the stack -; -; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ -; - LDR r5, [r4] ; Pickup current time-slice - STR r12, [r1, #8] ; Save the thread stack pointer - CBZ r5, __tx_ts_new ; If not active, skip processing -; -; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ -; - STR r5, [r1, #24] ; Save current time-slice -; -; /* Clear the global time-slice. */ -; - STR r3, [r4] ; Clear time-slice -; -; /* Executing thread is now completely preserved!!! */ -; +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + __tx_ts_new -; -; /* Now we are looking for a new thread to execute! */ -; - CPSID i ; Disable interrupts - LDR r1, [r2] ; Is there another thread ready to execute? - CBZ r1, __tx_ts_wait ; No, skip to the wait processing -; -; /* Yes, another thread is ready for else, make the current thread the new thread. */ -; - STR r1, [r0] ; Setup the current thread pointer to the new thread - CPSIE i ; Enable interrupts -; -; /* Increment the thread run count. */ -; + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + __tx_ts_restore - LDR r7, [r1, #4] ; Pickup the current thread run count - MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable - LDR r5, [r1, #24] ; Pickup thread's current time-slice - ADD r7, r7, #1 ; Increment the thread run count - STR r7, [r1, #4] ; Store the new run count -; -; /* Setup global time-slice with thread's current time-slice. */ -; - STR r5, [r4] ; Setup global time-slice + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread entry function to indicate the thread is executing. */ -; - PUSH {r0, r1} ; Save r0 and r1 - BL _tx_execution_thread_enter ; Call the thread execution enter function - POP {r0, r1} ; Recover r0 and r1 - ENDIF -; -; /* Restore the thread context and PSP. */ -; - LDR r12, [r1, #8] ; Pickup thread's stack pointer + /* Setup global time-slice with thread's current time-slice. */ - MRS r5, CONTROL ; Pickup current CONTROL register - LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit - ORR r4, r4, r5 ; Build new CONTROL register - MSR CONTROL, r4 ; Setup new CONTROL register + STR r5, [r4] // Setup global time-slice - LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r3, #0 ; Build disable value - STR r3, [r0] ; Disable MPU - LDR r0, [r1, #0x90] ; Pickup the module instance pointer - CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] - CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup - LDR r1, =0xE000ED9C ; Build address of MPU base register +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif - ; Use alias registers to quickly load MPU - ADD r0, r0, #100 ; Build address of MPU register start in thread control block - LDM r0!,{r2-r9} ; Load MPU regions 0-3 - STM r1,{r2-r9} ; Store MPU regions 0-3 - LDM r0!,{r2-r9} ; Load MPU regions 4-7 - STM r1,{r2-r9} ; Store MPU regions 4-7 - LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r1, #5 ; Build enable value with background region enabled - STR r1, [r0] ; Enable MPU + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU skip_mpu_setup - LDMIA r12!, {LR} ; Pickup LR - IF :DEF: __ARMVFP__ - TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore - VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers -_skip_vfp_restore - ENDIF - LDMIA r12!, {r4-r11} ; Recover thread's registers - MSR PSP, r12 ; Setup the thread's stack pointer -; -; /* Return to thread. */ -; - BX lr ; Return to thread! -; -; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts -; are disabled to allow use of WFI for waiting for a thread to arrive. */ -; + LDMIA r12!, {LR} // Pickup LR + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + __tx_ts_wait - CPSID i ; Disable interrupts - LDR r1, [r2] ; Pickup the next thread to execute pointer - STR r1, [r0] ; Store it in the current pointer - CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! - IF :DEF:TX_ENABLE_WFI - DSB ; Ensure no outstanding memory transactions - WFI ; Wait for interrupt - ISB ; Ensure pipeline is flushed - ENDIF - CPSIE i ; Enable interrupts - B __tx_ts_wait ; Loop to continue waiting -; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are -; already in the handler! */ -; + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + __tx_ts_ready - MOV r7, #0x08000000 ; Build clear PendSV value - MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV -; -; /* Re-enable interrupts and restore new thread. */ -; - CPSIE i ; Enable interrupts - B __tx_ts_restore ; Restore the thread -;} + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread +// } + + + /* SVC Handler. */ -; -; /* SVC Handler. */ -; EXPORT SVC_Handler EXPORT __tx_SVCallHandler SVC_Handler __tx_SVCallHandler -;{ - MRS r0, PSP ; Pickup the PSP stack - LDR r1, [r0, #24] ; Pickup the point of interrupt - LDRB r2, [r1, #-2] ; Pickup the SVC parameter - ; - ; Determine which SVC trap we are processing - ; - CMP r2, #1 ; Is it the entry into ThreadX? - BNE _tx_thread_user_return ; No, return to user mode - ; - ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected - ; - LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode. - SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. - CMP r1, r2 ; Did we come from user_mode_entry? - IT NE ; If no (not equal), then... - BXNE lr ; return from where we came. + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode - LDR r3, [r0, #20] ; This is the saved LR - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - MOV r1, #0 ; Build clear value - STR r1, [r2, #0x98] ; Clear the current user mode selection for thread - STR r3, [r2, #0xA0] ; Save the original LR in thread control block + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ - ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r2, =_txm_module_priv // Subtract 1 because of THUMB mode. + SUB r2, r2, #1 // Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_enter - ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size - ENDIF + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer - ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} - MSR PSP, r0 ; Set kernel stack pointer + MSR PSP, r0 // Set kernel stack pointer _tx_skip_kernel_stack_enter - MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit - MSR CONTROL, r0 ; Setup new CONTROL register - BX lr ; Return to thread + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread _tx_thread_user_return - LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode. - SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. - CMP r1, r2 ; Did we come from user_mode_exit? - IT NE ; If no (not equal), then... - BXNE lr ; return from where we came + LDR r2, =_txm_module_user_mode_exit // Subtract 1 because of THUMB mode. + SUB r2, r2, #1 // Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - LDR r1, [r2, #0x9C] ; Pick up user mode - STR r1, [r2, #0x98] ; Set the current user mode selection for thread + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread - ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_exit - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size - ENDIF - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - LDR r1, [r2, #0x9C] ; Pick up user mode + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode _tx_skip_kernel_stack_exit - MRS r0, CONTROL ; Pickup current CONTROL register - ORR r0, r0, r1 ; OR in the user mode bit - MSR CONTROL, r0 ; Setup new CONTROL register - BX lr ; Return to thread -;} + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + ALIGN 4 END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S index 1382a9ba..11effa55 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.S @@ -1,133 +1,131 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { EXPORT _tx_thread_stack_build _tx_thread_stack_build -; -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M3 should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - BIC r2, r2, #0x7 ; Align frame for 8-byte alignment - SUB r2, r2, #68 ; Subtract frame size - LDR r3, =0xFFFFFFFD ; Build initial LR value - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r4 - STR r3, [r2, #8] ; Store initial r5 - STR r3, [r2, #12] ; Store initial r6 - STR r3, [r2, #16] ; Store initial r7 - STR r3, [r2, #20] ; Store initial r8 - STR r3, [r2, #24] ; Store initial r9 - STR r3, [r2, #28] ; Store initial r10 - STR r3, [r2, #32] ; Store initial r11 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - MOV r3, #0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S index c15ef851..0ab4ae36 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.S @@ -1,85 +1,91 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { EXPORT _tx_thread_system_return _tx_thread_system_return -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - MOV r0, #0x10000000 ; Load PENDSVSET bit - MOV r1, #0xE000E000 ; Load NVIC base - STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S index e80da8e2..12fef571 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.S @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock IMPORT _tx_timer_current_ptr @@ -33,227 +32,223 @@ IMPORT _tx_thread_preempt_disable IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr -; -; + AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M3/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-Mx/AC5 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { EXPORT _tx_timer_interrupt _tx_timer_interrupt -; -; /* Upon entry to this routine, it is assumed that context save has already -; been called, and therefore the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADD r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUB r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADD r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice -; -; } -; + + // } + __tx_timer_not_ts_expiration -; - LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for -; -; } -; + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } ALIGN LTORG END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index dffb6197..acd22562 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 7efbf2df..613cb082 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index c670a087..b435d107 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 2b757ddd..8a40b3ac 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 7d60aefc..cc0cbd5f 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S index aaefebd7..91d808e4 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,141 +1,138 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + AREA ||.text||, CODE, READONLY THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { EXPORT _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build -; -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - BIC r2, r2, #0x7 ; Align frame - SUB r2, r2, #68 ; Subtract frame size - LDR r3, =0xFFFFFFFD ; Build initial LR value - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r4 - STR r3, [r2, #8] ; Store initial r5 - STR r3, [r2, #12] ; Store initial r6 - STR r3, [r2, #16] ; Store initial r7 - STR r3, [r2, #20] ; Store initial r8 - STR r3, [r2, #28] ; Store initial r10 - STR r3, [r2, #32] ; Store initial r11 -; -; /* Hardware stack follows. */ -; - STR r0, [r2, #36] ; Store initial r0, which is the thread control block - LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this - ; function with the actual, initial stack pointer. - STR r3, [r2, #40] ; Store initial r1, which is the module entry information. - LDR r3, [r3, #8] ; Pickup data base register from the module information - STR r3, [r2, #24] ; Store initial r9 (data base register) - MOV r3, #0 ; Clear r3 again + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - MOV r3, #0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's control block - BX lr ; Return to caller -;} - END + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + END diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S index 83c9bd4c..86620955 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -1,88 +1,88 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + IMPORT _txm_module_manager_kernel_dispatch IMPORT _tx_thread_current_ptr -; + AREA ||.text||, CODE, READONLY, ALIGN=5 THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/; -;VOID _txm_module_manager_user_mode_entry(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_user_mode_entry(VOID) +// { EXPORT _txm_module_manager_user_mode_entry _txm_module_manager_user_mode_entry - SVC 1 ; Enter kernel + SVC 1 // Enter kernel EXPORT _txm_module_priv _txm_module_priv - ; At this point, we are out of user mode. The original LR has been saved in the - ; thread control block. Simply call the kernel dispatch function. + // At this point, we are out of user mode. The original LR has been saved in the + // thread control block. Simply call the kernel dispatch function. BL _txm_module_manager_kernel_dispatch - ; Pickup the original LR value while still in privileged mode - LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r3, [r2] ; Pickup current thread pointer - LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + // Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call - SVC 2 ; Exit kernel and return to user mode + SVC 2 // Exit kernel and return to user mode EXPORT _txm_module_user_mode_exit _txm_module_user_mode_exit - BX lr ; Return to the caller -;} + BX lr // Return to the caller +// } ALIGN 32 END diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 90975e6c..82b9721c 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -94,21 +94,16 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif -/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) - * to reflect your system memory attributes (cache, shareable, memory type). */ -/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 -/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 -/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ -#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -159,13 +154,13 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to inline for ARM compiler. */ +/* Define INLINE_DECLARE to inline for AC6 compiler. */ #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -217,18 +212,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ - ULONG stack_available; \ - __asm("MOV %0, SP" : "=r"(stack_available)); \ - stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ - if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ - (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ - { \ - return(TX_SIZE_ERROR); \ - } - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -344,7 +327,7 @@ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1.8 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S index 455e86b5..cc4bdcc1 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S @@ -2,6 +2,7 @@ /* */ /* Copyright (c) Microsoft Corporation. All rights reserved. */ /* */ +/* This software is licensed under the Microsoft Software License */ /* Terms for Microsoft Azure RTOS. Full text of the license can be */ /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ /* and in the root directory of this software. */ @@ -19,11 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - .global __use_two_region_memory .global __scatterload - .eabi_attribute Tag_ABI_PCS_RO_data, 1 .eabi_attribute Tag_ABI_PCS_R9_use, 1 .eabi_attribute Tag_ABI_PCS_RW_data, 2 diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index 34ec131d..e6ebe65f 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -89,7 +89,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,14 +106,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index da83909f..17a79b0f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,9 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif .text .align 4 @@ -28,20 +31,16 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_context_restore Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ /* */ /* INPUT */ /* */ @@ -53,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -63,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index e48108d5..511ca82e 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -20,27 +20,26 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_context_save Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function is only needed for legacy applications and it should */ /* not be called in any new development on a Cortex-M. */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ /* */ /* INPUT */ /* */ @@ -52,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -62,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -70,6 +69,15 @@ .global _tx_thread_context_save .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index 7336051f..07d2a131 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -@/* _tx_thread_interrupt_control Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -66,15 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: - - // Pickup current interrupt lockout posture. - - MRS r1, PRIMASK // Pickup current interrupt lockout - - // Apply the new interrupt posture. - - MSR PRIMASK, r0 // Apply the new interrupt lockout - MOV r0, r1 // Transfer old to return register - BX lr // Return to caller - +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index b7615814..345ab227 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -20,18 +20,21 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit #endif - .text .align 4 .syntax unified @@ -73,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -84,7 +87,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -99,7 +102,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -188,10 +190,8 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts @@ -224,10 +224,8 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function @@ -294,10 +292,8 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ - PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 @@ -324,10 +320,10 @@ __tx_ts_restore: // Use alias registers to quickly load MPU ADD r0, r0, #100 // Build address of MPU register start in thread control block - LDM r0!,{r2-r9} // Load MPU regions 0-3 - STM r1,{r2-r9} // Store MPU regions 0-3 - LDM r0!,{r2-r9} // Load MPU regions 4-7 - STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions LDR r0, =0xE000ED94 // Build MPU control reg address MOV r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU @@ -349,11 +345,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting @@ -369,6 +379,7 @@ __tx_ts_ready: CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } /* SVC Handler. */ @@ -393,6 +404,7 @@ __tx_SVCallHandler: the kernel from a module thread with user mode selected. */ LDR r2, =_txm_module_priv // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -425,14 +437,14 @@ __tx_SVCallHandler: /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} MSR PSP, r0 // Set kernel stack pointer @@ -444,6 +456,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -471,14 +484,14 @@ _tx_thread_user_return: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -493,10 +506,10 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch - .align 5 + .align 5 .syntax unified // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index 548fe34a..d50f9243 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text .align 4 .syntax unified @@ -28,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_stack_build Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -70,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: @@ -96,7 +94,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - BIC r2, r2, #0x7 // Align frame + BIC r2, r2, #0x7 // Align frame for 8-byte alignment SUB r2, r2, #68 // Subtract frame size LDR r3, =0xFFFFFFFD // Build initial LR value STR r3, [r2, #0] // Save on the stack diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index 1639bbf2..6560db62 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text 32 .align 4 .syntax unified @@ -28,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_thread_system_return Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -79,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index 2cbef75d..46f54da0 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,17 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process - + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -39,19 +37,18 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M3/AC6 */ -/* 6.1 */ +/* _tx_timer_interrupt Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -74,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -83,8 +80,7 @@ .thumb_func _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -176,7 +172,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -192,7 +187,6 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment @@ -253,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 59be7606..85f06b66 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 475fc5a2..0e57c7c1 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index c670a087..b435d107 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 5249a938..f83a982f 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index df21aab9..a2e4dfa1 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 98982a1f..9d0b5a06 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -23,7 +23,6 @@ .text .align 4 .syntax unified - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,8 +72,8 @@ _txm_module_manager_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: - Stack Top: - LR Interrupted LR (LR at time of PENDSV) + Stack Top: + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 @@ -111,7 +110,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block @@ -138,4 +137,3 @@ _txm_module_manager_thread_stack_build: STR r2, [r0, #8] // Save stack pointer in thread's control block BX lr // Return to caller // } - diff --git a/ports_module/cortex_m3/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex_m3/gnu/example_build/build_threadx_module_library.bat index d0bbae23..b8602074 100644 --- a/ports_module/cortex_m3/gnu/example_build/build_threadx_module_library.bat +++ b/ports_module/cortex_m3/gnu/example_build/build_threadx_module_library.bat @@ -1,102 +1,102 @@ del txm.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc 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-mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt 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-mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o diff --git a/ports_module/cortex_m3/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_m3/gnu/example_build/build_threadx_module_sample.bat index 75214cdf..a25f370b 100644 --- a/ports_module/cortex_m3/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_m3/gnu/example_build/build_threadx_module_sample.bat @@ -1,5 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c arm-none-eabi-ld -A cortex-m3 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld index a33fbfeb..30c66655 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld @@ -9,8 +9,8 @@ SECTIONS { __FLASH_segment_start__ = 0x00030000; __FLASH_segment_end__ = 0x00040000; - __RAM_segment_start__ = 0; - __RAM_segment_end__ = 0x8000; + __RAM_segment_start__ = 0x10000000; + __RAM_segment_end__ = 0x10008000; __HEAPSIZE__ = 128; @@ -136,7 +136,7 @@ SECTIONS } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - __code_size__ = __rodata_end__ - __FLASH_segment_start__; + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index e16ad79a..01102ffa 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -94,6 +94,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 768 @@ -153,9 +158,9 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -322,7 +327,7 @@ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/GNU Version 6.1 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/GNU Version 6.1.8 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c index a20983fa..87b73b9b 100644 --- a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S index d279e33e..e445e690 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,87 +1,82 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_thread_system_stack_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_schedule - .global _tx_thread_preempt_disable - .global _tx_execution_isr_exit -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is only needed for legacy applications and it should */ -@/* not be called in any new development on a Cortex-M. */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_context_restore(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: -@ -@ /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr -@} +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S index 357f633a..e4f2778a 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S @@ -1,81 +1,80 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ - .global _tx_thread_system_state - .global _tx_thread_current_ptr - .global _tx_execution_isr_enter -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is only needed for legacy applications and it should */ -@/* not be called in any new development on a Cortex-M. */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_context_save(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { .global _tx_thread_context_save .thumb_func _tx_thread_context_save: -@ -@ /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr -@} +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S index 22331e70..99e14c06 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,81 +1,79 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ - +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@/* UINT _tx_thread_interrupt_control(UINT new_posture) -{ */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: - -@/* Pickup current interrupt lockout posture. */ - - MRS r1, PRIMASK @ Pickup current interrupt lockout - -@/* Apply the new interrupt posture. */ - - MSR PRIMASK, r0 @ Apply the new interrupt lockout - MOV r0, r1 @ Transfer old to return register - BX lr @ Return to caller - -@/* } */ +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S index 643243d5..c0aaaec9 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S @@ -20,16 +20,18 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_system_stack_ptr - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info - + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif .text .align 4 .syntax unified @@ -71,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -82,7 +84,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -97,7 +99,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -186,10 +187,8 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts @@ -223,10 +222,8 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ - CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function @@ -293,10 +290,8 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ - PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 @@ -348,11 +343,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting @@ -368,6 +377,7 @@ __tx_ts_ready: CPSIE i // Enable interrupts B __tx_ts_restore // Restore the thread +// } /* SVC Handler. */ @@ -393,6 +403,7 @@ __tx_SVCallHandler: the kernel from a module thread with user mode selected. */ LDR r2, =_txm_module_priv // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -425,14 +436,14 @@ __tx_SVCallHandler: /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} MSR PSP, r0 // Set kernel stack pointer @@ -444,6 +455,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + // Subtract 1 because of THUMB mode. CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -471,14 +483,14 @@ _tx_thread_user_return: MRS r3, PSP // Pickup kernel stack pointer /* Copy kernel hardware stack to module thread stack. */ - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -493,7 +505,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S index 05a03d86..d0246c13 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,135 +1,133 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function builds a stack frame on the supplied thread's stack. */ -@/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ -@/* thread_ptr Pointer to thread control blk */ -@/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { .global _tx_thread_stack_build .thumb_func _tx_thread_stack_build: -@ -@ -@ /* Build a fake interrupt frame. The form of the fake interrupt stack -@ on the Cortex-M3 should look like the following after it is built: -@ -@ Stack Top: -@ LR Interrupted LR (LR at time of PENDSV) -@ r4 Initial value for r4 -@ r5 Initial value for r5 -@ r6 Initial value for r6 -@ r7 Initial value for r7 -@ r8 Initial value for r8 -@ r9 Initial value for r9 -@ r10 Initial value for r10 -@ r11 Initial value for r11 -@ r0 Initial value for r0 (Hardware stack starts here!!) -@ r1 Initial value for r1 -@ r2 Initial value for r2 -@ r3 Initial value for r3 -@ r12 Initial value for r12 -@ lr Initial value for lr -@ pc Initial value for pc -@ xPSR Initial value for xPSR -@ -@ Stack Bottom: (higher memory address) */ -@ - LDR r2, [r0, #16] @ Pickup end of stack area - BIC r2, r2, #0x7 @ Align frame - SUB r2, r2, #68 @ Subtract frame size - LDR r3, =0xFFFFFFFD @ Build initial LR value - STR r3, [r2, #0] @ Save on the stack -@ -@ /* Actually build the stack frame. */ -@ - MOV r3, #0 @ Build initial register value - STR r3, [r2, #4] @ Store initial r4 - STR r3, [r2, #8] @ Store initial r5 - STR r3, [r2, #12] @ Store initial r6 - STR r3, [r2, #16] @ Store initial r7 - STR r3, [r2, #20] @ Store initial r8 - STR r3, [r2, #24] @ Store initial r9 - STR r3, [r2, #28] @ Store initial r10 - STR r3, [r2, #32] @ Store initial r11 -@ -@ /* Hardware stack follows. */ -@ - STR r3, [r2, #36] @ Store initial r0 - STR r3, [r2, #40] @ Store initial r1 - STR r3, [r2, #44] @ Store initial r2 - STR r3, [r2, #48] @ Store initial r3 - STR r3, [r2, #52] @ Store initial r12 - MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value - STR r3, [r2, #56] @ Store initial lr - STR r1, [r2, #60] @ Store initial pc - MOV r3, #0x01000000 @ Only T-bit need be set - STR r3, [r2, #64] @ Store initial xPSR -@ -@ /* Setup stack pointer. */ -@ thread_ptr -> tx_thread_stack_ptr = r2; -@ - STR r2, [r0, #8] @ Save stack pointer in thread's - @ control block - BX lr @ Return to caller -@} + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S index 7804a65c..1f20e1a6 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S @@ -1,88 +1,93 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Thread */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .text 32 .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@/* VOID _tx_thread_system_return(VOID) -@{ */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { .thumb_func .global _tx_thread_system_return _tx_thread_system_return: -@ -@ /* Return to real scheduler via PendSV. Note that this routine is often -@ replaced with in-line assembly in tx_port.h to improved performance. */ -@ - MOV r0, #0x10000000 @ Load PENDSVSET bit - MOV r1, #0xE000E000 @ Load NVIC base - STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR - MRS r0, IPSR @ Pickup IPSR - CMP r0, #0 @ Is it a thread returning? - BNE _isr_context @ If ISR, skip interrupt enable - MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK - CPSIE i @ Enable interrupts - MSR PRIMASK, r1 @ Restore original interrupt posture -_isr_context: - BX lr @ Return to caller -@/* } */ + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +#endif +_isr_context: + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S index 39721ec6..9551a2b2 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,257 +1,250 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Timer */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@ - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process -@ -@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + .text .align 4 .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt Cortex-M3/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_timer_interrupt(VOID) -@{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-Mx/GNU */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { .global _tx_timer_interrupt .thumb_func _tx_timer_interrupt: -@ -@ /* Upon entry to this routine, it is assumed that context save has already -@ been called, and therefore the compiler scratch registers are available -@ for use. */ -@ -@ /* Increment the system clock. */ -@ _tx_timer_system_clock++; -@ - LDR r1, =_tx_timer_system_clock @ Pickup address of system clock - LDR r0, [r1, #0] @ Pickup system clock - ADD r0, r0, #1 @ Increment system clock - STR r0, [r1, #0] @ Store new system clock -@ -@ /* Test for time-slice expiration. */ -@ if (_tx_timer_time_slice) -@ { -@ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice - LDR r2, [r3, #0] @ Pickup time-slice - CMP r2, #0 @ Is it non-active? - BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing -@ -@ /* Decrement the time_slice. */ -@ _tx_timer_time_slice--; -@ - SUB r2, r2, #1 @ Decrement the time-slice - STR r2, [r3, #0] @ Store new time-slice value -@ -@ /* Check for expiration. */ -@ if (__tx_timer_time_slice == 0) -@ - CMP r2, #0 @ Has it expired? - BNE __tx_timer_no_time_slice @ No, skip expiration processing -@ -@ /* Set the time-slice expired flag. */ -@ _tx_timer_expired_time_slice = TX_TRUE; -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag - MOV r0, #1 @ Build expired value - STR r0, [r3, #0] @ Set time-slice expiration flag -@ -@ } -@ + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -@ -@ /* Test for timer expiration. */ -@ if (*_tx_timer_current_ptr) -@ { -@ - LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address - LDR r0, [r1, #0] @ Pickup current timer - LDR r2, [r0, #0] @ Pickup timer list entry - CMP r2, #0 @ Is there anything in the list? - BEQ __tx_timer_no_timer @ No, just increment the timer -@ -@ /* Set expiration flag. */ -@ _tx_timer_expired = TX_TRUE; -@ - LDR r3, =_tx_timer_expired @ Pickup expiration flag address - MOV r2, #1 @ Build expired value - STR r2, [r3, #0] @ Set expired flag - B __tx_timer_done @ Finished timer processing -@ -@ } -@ else -@ { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -@ -@ /* No timer expired, increment the timer pointer. */ -@ _tx_timer_current_ptr++; -@ - ADD r0, r0, #4 @ Move to next timer -@ -@ /* Check for wrap-around. */ -@ if (_tx_timer_current_ptr == _tx_timer_list_end) -@ - LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end - LDR r2, [r3, #0] @ Pickup list end - CMP r0, r2 @ Are we at list end? - BNE __tx_timer_skip_wrap @ No, skip wrap-around logic -@ -@ /* Wrap to beginning of list. */ -@ _tx_timer_current_ptr = _tx_timer_list_start; -@ - LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start - LDR r0, [r3, #0] @ Set current pointer to list start -@ + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -@ - STR r0, [r1, #0] @ Store new current timer pointer -@ } -@ + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -@ -@ -@ /* See if anything has expired. */ -@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -@ { -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag - LDR r2, [r3, #0] @ Pickup time-slice expired flag - CMP r2, #0 @ Did a time-slice expire? - BNE __tx_something_expired @ If non-zero, time-slice expired - LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag - LDR r0, [r1, #0] @ Pickup timer expired flag - CMP r0, #0 @ Did a timer expire? - BEQ __tx_timer_nothing_expired @ No, nothing expired -@ + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -@ -@ - STMDB sp!, {r0, lr} @ Save the lr register on the stack - @ and save r0 just to keep 8-byte alignment -@ -@ /* Did a timer expire? */ -@ if (_tx_timer_expired) -@ { -@ - LDR r1, =_tx_timer_expired @ Pickup addr of expired flag - LDR r0, [r1, #0] @ Pickup timer expired flag - CMP r0, #0 @ Check for timer expiration - BEQ __tx_timer_dont_activate @ If not set, skip timer activation -@ -@ /* Process timer expiration. */ -@ _tx_timer_expiration_process(); -@ - BL _tx_timer_expiration_process @ Call the timer expiration handling routine -@ -@ } + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -@ -@ /* Did time slice expire? */ -@ if (_tx_timer_expired_time_slice) -@ { -@ - LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired - LDR r2, [r3, #0] @ Pickup the actual flag - CMP r2, #0 @ See if the flag is set - BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing -@ -@ /* Time slice interrupted thread. */ -@ _tx_thread_time_slice(); -@ - BL _tx_thread_time_slice @ Call time-slice processing - LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag - LDR r1, [r0] @ Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic - LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address - LDR r1, [r0] @ Pickup the current thread pointer - LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address - LDR r3, [r2] @ Pickup the execute thread pointer - LDR r0, =0xE000ED04 @ Build address of control register - LDR r2, =0x10000000 @ Build value for PendSV bit - CMP r1, r3 @ Are they the same? - BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed - STR r2, [r0] @ Not the same, issue the PendSV for preemption + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -@ -@ } -@ + + // } + __tx_timer_not_ts_expiration: -@ - LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for - @ the 8-byte stack alignment -@ -@ } -@ + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB @ Complete all memory access - BX lr @ Return to caller -@ -@} + DSB // Complete all memory access + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 28486298..a4d86f6d 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 4647d857..22eca632 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 316b9cb9..39db82f1 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 75099528..9af12b84 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 24679cef..f302903c 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 9dff891d..d2d13132 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -23,7 +23,6 @@ .text .align 4 .syntax unified - /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -73,8 +72,8 @@ _txm_module_manager_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: - Stack Top: - LR Interrupted LR (LR at time of PENDSV) + Stack Top: + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 @@ -111,7 +110,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block @@ -137,3 +136,4 @@ _txm_module_manager_thread_stack_build: STR r2, [r0, #8] // Save stack pointer in thread's control block BX lr // Return to caller +// } diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index 04f97122..a2d7354b 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 04-02-2021 Scott Larson Modified comment(s) and */ /* added check for overflow, */ /* resulting in version 6.1.6 */ @@ -95,9 +95,14 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE -#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ @@ -154,9 +159,9 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total - entries, since ThreadX uses one for access to the kernel dispatch function. */ - +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M3 parts, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 #define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 @@ -323,7 +328,7 @@ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ -CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.1 *"; +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.1.8 *"; #endif diff --git a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c index bac4233a..40355375 100644 --- a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s index a999ea98..53c60fbc 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s @@ -96,6 +96,12 @@ PUBLIC _tx_misra_void_to_uchar_pointer_convert PUBLIC _tx_misra_void_to_ulong_pointer_convert PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_misra_control_get + PUBLIC _tx_misra_control_set +#ifdef __ARMVFP__ + PUBLIC _tx_misra_fpccr_get + PUBLIC _tx_misra_vfp_touch +#endif PUBLIC _tx_version_id @@ -980,7 +986,7 @@ _tx_misra_char_to_uchar_pointer_convert: BX LR ;; return -***********************************************************************************************/ +/***********************************************************************************************/ /***********************************************************************************************/ /** */ /** ULONG _tx_misra_ipsr_get(void); */ @@ -995,6 +1001,71 @@ _tx_misra_ipsr_get: BX LR ;; return +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_get: + MRS R0, CONTROL + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR ;; return + + +#ifdef __ARMVFP__ + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(2) + THUMB +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 ; Build FPCCR address + LDR r0, [r0] ; Load FPCCR value + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR ;; return + +#endif + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s index 9842f8ce..0a188df9 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s @@ -1,89 +1,78 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_execution_isr_exit -; -; SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is only needed for legacy applications and it should */ -;/* not be called in any new development on a Cortex-M. */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_restore(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR exit function to indicate an ISR is complete. */ -; - PUSH {r0,lr} ; Save ISR lr - BL _tx_execution_isr_exit ; Call the ISR exit function - POP {r0,lr} ; Restore ISR lr +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address #endif -; - POP {lr} + BX lr -; -;} +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s index 23462fdc..e71ae496 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s @@ -1,87 +1,80 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_execution_isr_enter -; -; SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is only needed for legacy applications and it should */ -;/* not be called in any new development on a Cortex-M. */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* [_tx_execution_isr_enter] Execution profiling ISR enter */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_context_save(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the ISR enter function to indicate an ISR is starting. */ -; - PUSH {r0, lr} ; Save return address - BL _tx_execution_isr_enter ; Call the ISR enter function - POP {r0, lr} ; Recover return address + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address #endif -; -; /* Context is already saved - just return! */ -; + + /* Context is already saved - just return. */ + BX lr -;} +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s index 2c8bf932..c0d9d095 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,77 +1,78 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_control(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr -; -;} +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s index af919f6f..86fcf188 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,76 +1,78 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts and returning */ -;/* the previous interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;UINT _tx_thread_interrupt_disable(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(VOID) +// { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: -; -; /* Return current interrupt lockout posture. */ -; + /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr -; -;} +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s index a10b571f..f9603de1 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,75 +1,75 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring the previous */ -;/* interrupt lockout posture. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* previous_posture Previous interrupt posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_interrupt_restore(UINT new_posture) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT previous_posture) +// { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: -; -; /* Restore previous interrupt lockout posture. */ -; + /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr -; -;} +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s index 7d212b73..ec87d06e 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s @@ -1,521 +1,524 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr EXTERN _tx_execution_thread_enter EXTERN _tx_execution_thread_exit EXTERN _tx_thread_preempt_disable EXTERN _txm_module_manager_memory_fault_handler EXTERN _txm_module_manager_memory_fault_info -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M3/MPU/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_schedule(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M3/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { PUBLIC _tx_thread_schedule _tx_thread_schedule: -; -; /* This function should only ever be called on Cortex-M -; from the first schedule request. Subsequent scheduling occurs -; from the PendSV handling routines below. */ -; -; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; - MOV r0, #0 ; Build value for TX_FALSE - LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag - STR r0, [r2, #0] ; Clear preempt disable flag -; -; /* Enable memory fault registers. */ -; - LDR r0, =0xE000ED24 ; Build SHCSR address - LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; -; -; /* Enable interrupts */ -; + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ CPSIE i -; -; /* Enter the scheduler for the first time. */ -; - MOV r0, #0x10000000 ; Load PENDSVSET bit - MOV r1, #0xE000E000 ; Load NVIC base - STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - DSB ; Complete all memory accesses - ISB ; Flush pipeline -; /* Wait here for the PendSV to take place. */ + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ __tx_wait_here: - B __tx_wait_here ; Wait for the PendSV to happen -;} -; + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ -; -; /* Memory Exception Handler. */ -; PUBLIC MemManage_Handler PUBLIC BusFault_Handler PUBLIC UsageFault_Handler MemManage_Handler: BusFault_Handler: UsageFault_Handler: -;{ - CPSID i ; Disable interrupts -; -; /* Now pickup and store all the fault related information. */ -; - LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct - LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - STR r1, [r12, #0] ; Save current thread pointer in fault info structure - LDR r0, =0xE000ED24 ; Build SHCSR address - LDR r1, [r0] ; Pickup SHCSR - STR r1, [r12, #8] ; Save SHCSR - LDR r0, =0xE000ED28 ; Build CFSR address - LDR r1, [r0] ; Pickup CFSR - STR r1, [r12, #12] ; Save CFSR - LDR r0, =0xE000ED34 ; Build MMFAR address - LDR r1, [r0] ; Pickup MMFAR - STR r1, [r12, #16] ; Save MMFAR - LDR r0, =0xE000ED38 ; Build BFAR address - LDR r1, [r0] ; Pickup BFAR - STR r1, [r12, #20] ; Save BFAR - MRS r0, CONTROL ; Pickup current CONTROL register - STR r0, [r12, #24] ; Save CONTROL - MRS r1, PSP ; Pickup thread stack pointer - STR r1, [r12, #28] ; Save thread stack pointer - LDR r0, [r1] ; Pickup saved r0 - STR r0, [r12, #32] ; Save r0 - LDR r0, [r1, #4] ; Pickup saved r1 - STR r0, [r12, #36] ; Save r1 - STR r2, [r12, #40] ; Save r2 - STR r3, [r12, #44] ; Save r3 - STR r4, [r12, #48] ; Save r4 - STR r5, [r12, #52] ; Save r5 - STR r6, [r12, #56] ; Save r6 - STR r7, [r12, #60] ; Save r7 - STR r8, [r12, #64] ; Save r8 - STR r9, [r12, #68] ; Save r9 - STR r10,[r12, #72] ; Save r10 - STR r11,[r12, #76] ; Save r11 - LDR r0, [r1, #16] ; Pickup saved r12 - STR r0, [r12, #80] ; Save r12 - LDR r0, [r1, #20] ; Pickup saved lr - STR r0, [r12, #84] ; Save lr - LDR r0, [r1, #24] ; Pickup instruction address at point of fault - STR r0, [r12, #4] ; Save point of fault - LDR r0, [r1, #28] ; Pickup xPSR - STR r0, [r12, #88] ; Save xPSR - MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit - MSR CONTROL, r0 ; Setup new CONTROL register + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register - LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) - LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: - ; Bit 0 = 1 -> Instruction address violation - ; Bit 1 = 1 -> Load/store address violation - ; Bit 7 = 1 -> MMFAR is valid - STRB r1, [r0] ; Clear the MMFSR + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR - BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread exit function to indicate the thread is no longer executing. */ -; - CPSID i ; Disable interrupts - BL _tx_execution_thread_exit ; Call the thread exit function - CPSIE i ; Enable interrupts +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts #endif - MOV r1, #0 ; Build NULL value - LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer - STR r1, [r0] ; Clear current thread pointer + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer - ; Return from MemManage_Handler exception - LDR r0, =0xE000ED04 ; Load ICSR - LDR r1, =0x10000000 ; Set PENDSVSET bit - STR r1, [r0] ; Store ICSR - DSB ; Wait for memory access to complete - CPSIE i ; Enable interrupts - MOV lr, #0xFFFFFFFD ; Load exception return code - BX lr ; Return from exception -;} + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ -; -; /* Generic context PendSV handler. */ -; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: -; -; /* Get current thread value and new thread pointer. */ -; + + /* Get current thread value and new thread pointer. */ + __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread exit function to indicate the thread is no longer executing. */ -; - CPSID i ; Disable interrupts - PUSH {r0, lr} ; Save LR (and r0 just for alignment) - BL _tx_execution_thread_exit ; Call the thread exit function - POP {r0, lr} ; Recover LR - CPSIE i ; Enable interrupts +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts #endif - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - MOV r3, #0 ; Build NULL value - LDR r1, [r0] ; Pickup current thread pointer -; -; /* Determine if there is a current thread to finish preserving. */ -; - CBZ r1, __tx_ts_new ; If NULL, skip preservation -; -; /* Recover PSP and preserve current thread context. */ -; - STR r3, [r0] ; Set _tx_thread_current_ptr to NULL - MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) - STMDB r12!, {r4-r11} ; Save its remaining registers - MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable - STMDB r12!, {LR} ; Save LR on the stack -; -; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ -; - LDR r5, [r4] ; Pickup current time-slice - STR r12, [r1, #8] ; Save the thread stack pointer - CBZ r5, __tx_ts_new ; If not active, skip processing -; -; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ -; - STR r5, [r1, #24] ; Save current time-slice -; -; /* Clear the global time-slice. */ -; - STR r3, [r4] ; Clear time-slice -; -; -; /* Executing thread is now completely preserved!!! */ -; + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + __tx_ts_new: -; -; /* Now we are looking for a new thread to execute! */ -; - CPSID i ; Disable interrupts - LDR r1, [r2] ; Is there another thread ready to execute? - CBZ r1, __tx_ts_wait ; No, skip to the wait processing -; -; /* Yes, another thread is ready for else, make the current thread the new thread. */ -; - STR r1, [r0] ; Setup the current thread pointer to the new thread - CPSIE i ; Enable interrupts -; -; /* Increment the thread run count. */ -; + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + __tx_ts_restore: - LDR r7, [r1, #4] ; Pickup the current thread run count - MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable - LDR r5, [r1, #24] ; Pickup thread's current time-slice - ADD r7, r7, #1 ; Increment the thread run count - STR r7, [r1, #4] ; Store the new run count -; -; /* Setup global time-slice with thread's current time-slice. */ -; - STR r5, [r4] ; Setup global time-slice + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -; -; /* Call the thread entry function to indicate the thread is executing. */ -; - PUSH {r0, r1} ; Save r0 and r1 - BL _tx_execution_thread_enter ; Call the thread execution enter function - POP {r0, r1} ; Recover r0 and r1 + STR r5, [r4] // Setup global time-slice + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 #endif -; -; /* Restore the thread context and PSP. */ -; - LDR r12, [r1, #8] ; Pickup thread's stack pointer - MRS r5, CONTROL ; Pickup current CONTROL register - LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit - ORR r4, r4, r5 ; Build new CONTROL register - MSR CONTROL, r4 ; Setup new CONTROL register + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer - LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r3, #0 ; Build disable value - STR r3, [r0] ; Disable MPU - LDR r0, [r1, #0x90] ; Pickup the module instance pointer - CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] - CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup - LDR r1, =0xE000ED9C ; Build address of MPU base register + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register - ; Use alias registers to quickly load MPU - ADD r0, r0, #100 ; Build address of MPU register start in thread control block - LDM r0!,{r2-r9} ; Load first four MPU regions - STM r1,{r2-r9} ; Store first four MPU regions - LDM r0,{r2-r9} ; Load second four MPU regions - STM r1,{r2-r9} ; Store second four MPU regions - LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r1, #5 ; Build enable value with background region enabled - STR r1, [r0] ; Enable MPU + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU skip_mpu_setup: - LDMIA r12!, {LR} ; Pickup LR - LDMIA r12!, {r4-r11} ; Recover thread's registers - MSR PSP, r12 ; Setup the thread's stack pointer -; -; /* Return to thread. */ -; - BX lr ; Return to thread! -; -; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts -; are disabled to allow use of WFI for waiting for a thread to arrive. */ -; + LDMIA r12!, {LR} // Pickup LR + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + __tx_ts_wait: - CPSID i ; Disable interrupts - LDR r1, [r2] ; Pickup the next thread to execute pointer - STR r1, [r0] ; Store it in the current pointer - CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI - DSB ; Ensure no outstanding memory transactions - WFI ; Wait for interrupt - ISB ; Ensure pipeline is flushed + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed #endif - CPSIE i ; Enable interrupts - B __tx_ts_wait ; Loop to continue waiting -; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are -; already in the handler! */ -; + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + __tx_ts_ready: - MOV r7, #0x08000000 ; Build clear PendSV value - MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV -; -; /* Re-enable interrupts and restore new thread. */ -; - CPSIE i ; Enable interrupts - B __tx_ts_restore ; Restore the thread -;} + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread +// } + + + /* SVC Handler. */ -; -; /* SVC Handler. */ -; PUBLIC SVC_Handler PUBLIC __tx_SVCallHandler SVC_Handler: __tx_SVCallHandler: -;{ - MRS r0, PSP ; Pickup the PSP stack - LDR r1, [r0, #24] ; Pickup the point of interrupt - LDRB r2, [r1, #-2] ; Pickup the SVC parameter - ; - ; Determine which SVC trap we are processing - ; - CMP r2, #1 ; Is it the entry into ThreadX? - BNE _tx_thread_user_return ; No, return to user mode - ; - ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected - ; - LDR r2, =_txm_module_priv-1 ; Subtract 1 because of THUMB mode. - CMP r1, r2 ; Did we come from user_mode_entry? - IT NE ; If no (not equal), then... - BXNE lr ; return from where we came. - LDR r3, [r0, #20] ; This is the saved LR - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - MOV r1, #0 ; Build clear value - STR r1, [r2, #0x98] ; Clear the current user mode selection for thread - STR r3, [r2, #0xA0] ; Save the original LR in thread control block + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ - ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r2, =_txm_module_priv-1 // Load address of where we should have come from + // Subtract 1 because of THUMB mode. + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_enter - ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end #ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size #endif - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer - ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} - LDMDB r3!,{r1-r2} - STMDB r0!,{r1-r2} + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} + LDMDB r3!, {r1-r2} + STMDB r0!, {r1-r2} - MSR PSP, r0 ; Set kernel stack pointer + MSR PSP, r0 // Set kernel stack pointer _tx_skip_kernel_stack_enter: - MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit - MSR CONTROL, r0 ; Setup new CONTROL register - BX lr ; Return to thread + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. - CMP r1, r2 ; Did we come from user_mode_exit? - IT NE ; If no (not equal), then... - BXNE lr ; return from where we came + LDR r2, =_txm_module_user_mode_exit-1 // Load address of where we should have come from + // Subtract 1 because of THUMB mode. + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - LDR r1, [r2, #0x9C] ; Pick up user mode - STR r1, [r2, #0x98] ; Set the current user mode selection for thread + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread - ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_exit #ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size #endif - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - LDM r3!,{r1-r2} - STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + LDM r3!, {r1-r2} + STM r0!, {r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer - LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r2, [r1] ; Pickup current thread pointer - LDR r1, [r2, #0x9C] ; Pick up user mode + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode _tx_skip_kernel_stack_exit: - MRS r0, CONTROL ; Pickup current CONTROL register - ORR r0, r0, r1 ; OR in the user mode bit - MSR CONTROL, r0 ; Setup new CONTROL register - BX lr ; Return to thread -;} + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ -; -; /* Kernel entry function from user mode. */ -; EXTERN _txm_module_manager_kernel_dispatch -; SECTION `.text`:CODE:NOROOT(5) THUMB ALIGNROM 5 -;VOID _txm_module_manager_user_mode_entry(VOID) -;{ +// VOID _txm_module_manager_user_mode_entry(VOID) +// { PUBLIC _txm_module_manager_user_mode_entry _txm_module_manager_user_mode_entry: - SVC 1 ; Enter kernel + SVC 1 // Enter kernel _txm_module_priv: - ; At this point, we are out of user mode. The original LR has been saved in the - ; thread control block. Simply call the kernel dispatch function. + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ BL _txm_module_manager_kernel_dispatch - ; Pickup the original LR value while still in privileged mode - LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r3, [r2] ; Pickup current thread pointer - LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call - SVC 2 ; Exit kernel and return to user mode + SVC 2 // Exit kernel and return to user mode _txm_module_user_mode_exit: - BX lr ; Return to the caller + BX lr // Return to the caller NOP NOP NOP NOP -;} +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s index e5f23bc5..dcc82bf6 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s @@ -1,134 +1,132 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: -; -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - BIC r2, r2, #0x7 ; Align frame for 8-byte alignment - SUB r2, r2, #68 ; Subtract frame size - LDR r3, =0xFFFFFFFD ; Build initial LR value - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r4 - STR r3, [r2, #8] ; Store initial r5 - STR r3, [r2, #12] ; Store initial r6 - STR r3, [r2, #16] ; Store initial r7 - STR r3, [r2, #20] ; Store initial r8 - STR r3, [r2, #24] ; Store initial r9 - STR r3, [r2, #28] ; Store initial r10 - STR r3, [r2, #32] ; Store initial r11 -; -; /* Hardware stack follows. */ -; - STR r3, [r2, #36] ; Store initial r0 - STR r3, [r2, #40] ; Store initial r1 - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - MOV r3, #0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block - BX lr ; Return to caller -;} + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s index 38fb892b..4c5cb6fb 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s @@ -1,87 +1,92 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_thread_system_return(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: -; -; /* Return to real scheduler via PendSV. Note that this routine is often -; replaced with in-line assembly in tx_port.h to improved performance. */ -; - MOV r0, #0x10000000 ; Load PENDSVSET bit - MOV r1, #0xE000E000 ; Load NVIC base - STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - MRS r0, IPSR ; Pickup IPSR - CMP r0, #0 ; Is it a thread returning? - BNE _isr_context ; If ISR, skip interrupt enable - MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK - CPSIE i ; Enable interrupts - MSR PRIMASK, r1 ; Restore original interrupt posture + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: - BX lr ; Return to caller -;} + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s index 58303af0..aa209956 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock EXTERN _tx_timer_current_ptr @@ -33,224 +32,221 @@ EXTERN _tx_thread_current_ptr EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_preempt_disable -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-M3/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* expiration functions are called. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_timer_interrupt(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-Mx/IAR */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* expiration functions are called. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { PUBLIC _tx_timer_interrupt _tx_timer_interrupt: -; -; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available -; for use. */ -; -; /* Increment the system clock. */ -; _tx_timer_system_clock++; -; - MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock - LDR r0, [r1, #0] ; Pickup system clock - ADD r0, r0, #1 ; Increment system clock - STR r0, [r1, #0] ; Store new system clock -; -; /* Test for time-slice expiration. */ -; if (_tx_timer_time_slice) -; { -; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice - LDR r2, [r3, #0] ; Pickup time-slice - CBZ r2, __tx_timer_no_time_slice ; Is it non-active? - ; Yes, skip time-slice processing -; -; /* Decrement the time_slice. */ -; _tx_timer_time_slice--; -; - SUB r2, r2, #1 ; Decrement the time-slice - STR r2, [r3, #0] ; Store new time-slice value -; -; /* Check for expiration. */ -; if (__tx_timer_time_slice == 0) -; - CBNZ r2, __tx_timer_no_time_slice ; Has it expired? -; -; /* Set the time-slice expired flag. */ -; _tx_timer_expired_time_slice = TX_TRUE; -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag - MOV r0, #1 ; Build expired value - STR r0, [r3, #0] ; Set time-slice expiration flag -; -; } -; + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + __tx_timer_no_time_slice: -; -; /* Test for timer expiration. */ -; if (*_tx_timer_current_ptr) -; { -; - MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address - LDR r0, [r1, #0] ; Pickup current timer - LDR r2, [r0, #0] ; Pickup timer list entry - CBZ r2, __tx_timer_no_timer ; Is there anything in the list? - ; No, just increment the timer -; -; /* Set expiration flag. */ -; _tx_timer_expired = TX_TRUE; -; - MOV32 r3, _tx_timer_expired ; Pickup expiration flag address - MOV r2, #1 ; Build expired value - STR r2, [r3, #0] ; Set expired flag - B __tx_timer_done ; Finished timer processing -; -; } -; else -; { + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { __tx_timer_no_timer: -; -; /* No timer expired, increment the timer pointer. */ -; _tx_timer_current_ptr++; -; - ADD r0, r0, #4 ; Move to next timer -; -; /* Check for wrap-around. */ -; if (_tx_timer_current_ptr == _tx_timer_list_end) -; - MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end - LDR r2, [r3, #0] ; Pickup list end - CMP r0, r2 ; Are we at list end? - BNE __tx_timer_skip_wrap ; No, skip wrap-around logic -; -; /* Wrap to beginning of list. */ -; _tx_timer_current_ptr = _tx_timer_list_start; -; - MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start - LDR r0, [r3, #0] ; Set current pointer to list start -; + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + __tx_timer_skip_wrap: -; - STR r0, [r1, #0] ; Store new current timer pointer -; } -; + + STR r0, [r1, #0] // Store new current timer pointer + // } + __tx_timer_done: -; -; -; /* See if anything has expired. */ -; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag - LDR r2, [r3, #0] ; Pickup time-slice expired flag - CBNZ r2, __tx_something_expired ; Did a time-slice expire? - ; If non-zero, time-slice expired - MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? - ; No, nothing expired -; + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + __tx_something_expired: -; -; - STMDB sp!, {r0, lr} ; Save the lr register on the stack - ; and save r0 just to keep 8-byte alignment -; -; /* Did a timer expire? */ -; if (_tx_timer_expired) -; { -; - MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag - LDR r0, [r1, #0] ; Pickup timer expired flag - CBZ r0, __tx_timer_dont_activate ; Check for timer expiration - ; If not set, skip timer activation -; -; /* Process timer expiration. */ -; _tx_timer_expiration_process(); -; - BL _tx_timer_expiration_process ; Call the timer expiration handling routine -; -; } + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } __tx_timer_dont_activate: -; -; /* Did time slice expire? */ -; if (_tx_timer_expired_time_slice) -; { -; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired - LDR r2, [r3, #0] ; Pickup the actual flag - CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set - ; No, skip time-slice processing -; -; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); - BL _tx_thread_time_slice ; Call time-slice processing - MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag - LDR r1, [r0] ; Is the preempt disable flag set? - CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r1, [r0] ; Pickup the current thread pointer - MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address - LDR r3, [r2] ; Pickup the execute thread pointer - MOV32 r0, 0xE000ED04 ; Build address of control register - MOV32 r2, 0x10000000 ; Build value for PendSV bit - CMP r1, r3 ; Are they the same? - BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed - STR r2, [r0] ; Not the same, issue the PendSV for preemption + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: -; -; } -; + + // } + __tx_timer_not_ts_expiration: -; - LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for - ; the 8-byte stack alignment -; -; } -; + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + __tx_timer_nothing_expired: - DSB ; Complete all memory access - BX lr ; Return to caller -; -;} + DSB // Complete all memory access + BX lr // Return to caller +// } END diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c index fab10684..173cd9ca 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 7eaa53df..2f6b20bd 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index e516ffc4..8fdeb79f 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index ac9d7dd7..8df56b6a 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 83aad68f..c51db309 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 2158c319..4c0a49ec 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,141 +1,138 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + SECTION `.text`:CODE:NOROOT(2) THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ -;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { PUBLIC _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build: -; -; -; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M should look like the following after it is built: -; -; Stack Top: -; LR Interrupted LR (LR at time of PENDSV) -; r4 Initial value for r4 -; r5 Initial value for r5 -; r6 Initial value for r6 -; r7 Initial value for r7 -; r8 Initial value for r8 -; r9 Initial value for r9 -; r10 Initial value for r10 -; r11 Initial value for r11 -; r0 Initial value for r0 (Hardware stack starts here!!) -; r1 Initial value for r1 -; r2 Initial value for r2 -; r3 Initial value for r3 -; r12 Initial value for r12 -; lr Initial value for lr -; pc Initial value for pc -; xPSR Initial value for xPSR -; -; Stack Bottom: (higher memory address) */ -; - LDR r2, [r0, #16] ; Pickup end of stack area - BIC r2, r2, #0x7 ; Align frame - SUB r2, r2, #68 ; Subtract frame size - LDR r3, =0xFFFFFFFD ; Build initial LR value - STR r3, [r2, #0] ; Save on the stack -; -; /* Actually build the stack frame. */ -; - MOV r3, #0 ; Build initial register value - STR r3, [r2, #4] ; Store initial r4 - STR r3, [r2, #8] ; Store initial r5 - STR r3, [r2, #12] ; Store initial r6 - STR r3, [r2, #16] ; Store initial r7 - STR r3, [r2, #20] ; Store initial r8 - STR r3, [r2, #28] ; Store initial r10 - STR r3, [r2, #32] ; Store initial r11 -; -; /* Hardware stack follows. */ -; - STR r0, [r2, #36] ; Store initial r0, which is the thread control block - LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this - ; function with the actual, initial stack pointer. - STR r3, [r2, #40] ; Store initial r1, which is the module entry information. - LDR r3, [r3, #8] ; Pickup data base register from the module information - STR r3, [r2, #24] ; Store initial r9 (data base register) - MOV r3, #0 ; Clear r3 again + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: - STR r3, [r2, #44] ; Store initial r2 - STR r3, [r2, #48] ; Store initial r3 - STR r3, [r2, #52] ; Store initial r12 - MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value - STR r3, [r2, #56] ; Store initial lr - STR r1, [r2, #60] ; Store initial pc - MOV r3, #0x01000000 ; Only T-bit need be set - STR r3, [r2, #64] ; Store initial xPSR -; -; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = r2; -; - STR r2, [r0, #8] ; Save stack pointer in thread's control block - BX lr ; Return to caller -;} - END + Stack Top: + lr Interrupted lr (lr at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + END diff --git a/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvoptx b/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvoptx index 145c7e5f..25c1033c 100644 --- a/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvoptx +++ b/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvoptx @@ -2947,6 +2947,18 @@ <RteFlg>0</RteFlg> <bShared>0</bShared> </File> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>232</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\module_manager\src\tx_thread_secure_stack_initialize.S</PathWithFileName> + <FilenameWithoutPath>tx_thread_secure_stack_initialize.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> </Group> <Group> diff --git a/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx b/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx index f3a174c5..a9b1b0d4 100644 --- a/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx +++ b/ports_module/cortex_m33/ac6/example_build/ThreadX_Library.uvprojx @@ -1538,6 +1538,11 @@ <FileType>1</FileType> <FilePath>..\module_manager\src\txm_module_manager_port_dispatch.c</FilePath> </File> + <File> + <FileName>tx_thread_secure_stack_initialize.S</FileName> + <FileType>2</FileType> + <FilePath>..\module_manager\src\tx_thread_secure_stack_initialize.S</FilePath> + </File> </Files> </Group> <Group> diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index a9f6004f..70f2d34b 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -47,11 +47,11 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ /* macro definition, */ /* resulting in version 6.1.6 */ -/* 06-02-2021 Bhupendra Naphade Modified comment(s), */ +/* 06-02-2021 Bhupendra Naphade Modified comment(s), */ /* added symbol to enable */ /* stack error handler, */ /* resulting in version 6.1.7 */ @@ -75,7 +75,6 @@ #include <stdlib.h> #include <string.h> #include <arm_compat.h> -#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ /* Define ThreadX basic types for this port. */ diff --git a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h index 5493af01..bcbd3cae 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S index 61f9e6ad..97f96024 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S index 5be18688..72727f6c 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S index ac26010f..ada8bdbb 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -68,11 +68,15 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S index 19d2da39..fb8b55dc 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 12-31-2020 Scott Larson Initial Version 6.1.3 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 @@ -70,8 +70,14 @@ .type _tx_thread_interrupt_disable, function _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S index 13ff2fcf..62c07c7c 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 12-31-2020 Scott Larson Initial Version 6.1.3 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 @@ -70,7 +70,11 @@ .type _tx_thread_interrupt_restore, function _tx_thread_interrupt_restore: /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 34a5b524..8ef9e2cb 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -21,6 +21,10 @@ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -77,37 +81,31 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOV r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARM_FP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -235,7 +233,7 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -346,7 +344,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -409,8 +407,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ - BX lr // Return to thread! @@ -425,8 +421,8 @@ _skip_vfp_restore: SVC_Handler: TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP - MRSNE r0, PSP // Get PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP LDR r1, [r0,#24] // Load saved PC from stack LDRB r2, [r1,#-2] // Load SVC number @@ -437,7 +433,7 @@ SVC_Handler: CMP r2, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE CMP r2, #3 // Is it the entry into ThreadX? @@ -529,6 +525,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -538,14 +555,14 @@ _tx_thread_user_return: ORREQ lr, lr, #0x10 // Else set bit, return with standard frame /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -586,11 +603,11 @@ _tx_svc_secure_free: POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch .align 5 diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c index bca57e2d..5089f39b 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c @@ -29,7 +29,7 @@ #define TX_SOURCE_CODE -#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ +#include "cmsis_compiler.h" /* For intrinsic functions. */ #include "tx_secure_interface.h" /* Interface for NS code. */ /* Minimum size of secure stack. */ @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M33/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,35 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Modified comment(s), and */ +/* changed name, execute in */ +/* handler mode, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -291,7 +305,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -376,7 +390,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S new file mode 100644 index 00000000..e7cd43e8 --- /dev/null +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to initialize a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* none */ +/* */ +/* OUTPUT */ +/* */ +/* none */ +/* */ +/* CALLS */ +/* */ +/* SVC 3 */ +/* */ +/* CALLED BY */ +/* */ +/* TX_INITIALIZE_KERNEL_ENTER_EXTENSION */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_secure_stack_initialize(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_initialize + .thumb_func +.type _tx_thread_secure_stack_initialize, function +_tx_thread_secure_stack_initialize: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + CPSIE i // Enable interrupts for SVC call + SVC 3 + CPSID i // Disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif + BX lr + .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S index ec548d5e..37018299 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S @@ -72,7 +72,7 @@ .type _tx_thread_stack_build, function _tx_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack - on the Cortex-M33 should look like the following after it is built: + on the Cortex-M should look like the following after it is built: Stack Top: LR Interrupted LR (LR at time of PENDSV) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c index 4c9449f3..4d3bbee7 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/AC6 */ -/* 6.1.3 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,12 +70,11 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c index 0a0527c6..d61a27b3 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/AC6 */ -/* 6.1.3 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S index e77e9333..3aa07ffc 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S @@ -75,14 +75,21 @@ _tx_thread_system_return: replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit - LDR r1, =0xE000E000 // Load NVIC base + MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller // } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S index 8ffde8f1..bcd29878 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 12-31-2020 Scott Larson Initial Version 6.1.3 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -74,8 +73,7 @@ .type _tx_timer_interrupt, function _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -92,22 +90,23 @@ _tx_timer_interrupt: LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUB r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOV r0, #1 // Build expired value @@ -127,8 +126,8 @@ __tx_timer_no_time_slice: CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; LDR r3, =_tx_timer_expired // Pickup expiration flag address MOV r2, #1 // Build expired value @@ -140,21 +139,21 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADD r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start @@ -166,7 +165,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -182,7 +180,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -194,8 +192,8 @@ __tx_something_expired: CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -211,8 +209,8 @@ __tx_timer_dont_activate: CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -223,17 +221,17 @@ __tx_timer_dont_activate: LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register - MOV r2, 0x10000000 // Build value for PendSV bit + LDR r2, =0x10000000 // Build value for PendSV bit CMP r1, r3 // Are they the same? BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment // } @@ -241,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index 6268cba9..aaddb639 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1.3 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c index 4e6a9ed9..2c73a8e6 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1.3 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index eebd313f..8cb93534 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_alignment_adjust Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index e5d9e887..67bc7196 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_external_memory_enable Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index e57e3555..0ed0c212 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_memory_fault_handler Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index ec08139a..88baa804 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_memory_fault_notify Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 4bd99c30..5ad546a3 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,7 +29,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* _txm_module_manager_mm_register_setup Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ @@ -123,7 +123,7 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* _txm_module_manager_inside_data_check Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 422b0826..977107d1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_port_dispatch Cortex-M33/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_port_dispatch Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 9d49531c..c385ff1b 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s index 0cf97109..b86c6ea3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* _tx_thread_schedule Thread scheduling routine */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_restore, function _tx_thread_context_restore: - /* Just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s index 29c21b85..5f180511 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s @@ -20,7 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -45,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -68,7 +70,14 @@ .thumb_func .type _tx_thread_context_save, function _tx_thread_context_save: - /* Return to interrupt processing. */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + BX lr // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s index bbe60f44..f0335e70 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -68,11 +68,15 @@ .thumb_func .type _tx_thread_interrupt_control, function _tx_thread_interrupt_control: - - /* Pickup current interrupt lockout posture. */ - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else + MRS r1, PRIMASK // Pickup current interrupt lockout + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register +#endif + BX lr // Return to caller // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s index 62ed1d07..eca0f5d4 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { .section .text .balign 4 @@ -70,8 +70,14 @@ .type _tx_thread_interrupt_disable, function _tx_thread_interrupt_disable: /* Return current interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s index e33ce2b0..a42b12d0 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -59,7 +59,7 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { .section .text .balign 4 @@ -70,7 +70,11 @@ .type _tx_thread_interrupt_restore, function _tx_thread_interrupt_restore: /* Restore previous interrupt lockout posture. */ +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index 2fd8725c..a23118c4 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -80,37 +80,31 @@ .thumb_func .type _tx_thread_schedule, function _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOV r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARM_PCS_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -238,7 +232,7 @@ BusFault_Handler: PendSV_Handler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -349,7 +343,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -412,8 +406,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ - BX lr // Return to thread! @@ -428,8 +420,8 @@ _skip_vfp_restore: SVC_Handler: TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 ITE EQ - MRSEQ r0, MSP // Get MSP - MRSNE r0, PSP // Get PSP + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP LDR r1, [r0,#24] // Load saved PC from stack LDRB r2, [r1,#-2] // Load SVC number @@ -440,7 +432,7 @@ SVC_Handler: CMP r2, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE CMP r2, #3 // Is it the entry into ThreadX? @@ -477,7 +469,6 @@ SVC_Handler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif - MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -533,6 +524,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -542,14 +554,14 @@ _tx_thread_user_return: ORREQ lr, lr, #0x10 // Else set bit, return with standard frame /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -590,7 +602,7 @@ _tx_svc_secure_free: POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE @@ -633,6 +645,8 @@ _txm_module_user_mode_exit: .thumb_func .type _tx_vfp_access, function _tx_vfp_access: +#if TX_ENABLE_FPU_SUPPORT VMOV.F32 s0, s0 // Simply access the VFP +#endif BX lr // Return to caller .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c index ed207338..9375062c 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c @@ -61,8 +61,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M33/GNU */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M33/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -77,14 +77,11 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ -/* __get_CONTROL Intrinsic to get CONTROL */ -/* __set_CONTROL Intrinsic to set CONTROL */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ @@ -97,24 +94,40 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Change name, execute in */ +/* handler mode, */ +/* disable optimizations, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ -__attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +__attribute__((cmse_nonsecure_entry, optimize(0))) +UINT _tx_thread_secure_mode_stack_initialize(void) { - ULONG control; - - /* Set secure mode to use PSP. */ - asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ - control |= 2; /* Use PSP. */ - asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - asm volatile("MSR PSPLIM, %0" :: "r" (0)); - asm volatile("MSR PSP, %0" :: "r" (0)); - - return; +UINT status; +ULONG control; +ULONG ipsr; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ + control |= 2; /* Use PSP. */ + asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + status = TX_SUCCESS; + } + return status; } @@ -147,12 +160,9 @@ void _tx_thread_secure_stack_initialize(void) /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ /* calloc Compiler's calloc function */ /* malloc Compiler's malloc function */ /* free Compiler's free() function */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ /* */ /* CALLED BY */ /* */ @@ -275,7 +285,6 @@ ULONG psplim_ns; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ /* free Compiler's free() function */ /* */ /* CALLED BY */ @@ -358,10 +367,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ -/* __get_PSP Intrinsic to get PSP */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ @@ -446,9 +452,7 @@ ULONG ipsr; /* */ /* CALLS */ /* */ -/* __get_IPSR Intrinsic to get IPSR */ -/* __set_PSPLIM Intrinsic to set PSP limit */ -/* __set_PSP Intrinsic to set PSP */ +/* None */ /* */ /* CALLED BY */ /* */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 333a95a3..f1143751 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -67,6 +67,7 @@ .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 .global _tx_thread_secure_stack_allocate + .global _tx_alloc_return .thumb_func .type _tx_thread_secure_stack_allocate, function _tx_thread_secure_stack_allocate: @@ -74,6 +75,7 @@ _tx_thread_secure_stack_allocate: MRS r3, PRIMASK // Save interrupt mask CPSIE i // Enable interrupts for SVC call SVC 1 +_tx_alloc_return: CMP r3, #0 // If interrupts enabled, just return BEQ _alloc_return_interrupt_enabled CPSID i // Otherwise, disable interrupts diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S index 5152414b..06f6611a 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -65,6 +65,7 @@ .syntax unified .eabi_attribute Tag_ABI_align_preserved, 1 .global _tx_thread_secure_stack_free + .global _tx_free_return .thumb_func .type _tx_thread_secure_stack_free, function _tx_thread_secure_stack_free: @@ -72,6 +73,7 @@ _tx_thread_secure_stack_free: MRS r3, PRIMASK // Save interrupt mask CPSIE i // Enable interrupts for SVC call SVC 2 +_tx_free_return: CMP r3, #0 // If interrupts enabled, just return BEQ _free_return_interrupt_enabled CPSID i // Otherwise, disable interrupts diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s index 5bda6d11..0e85e2a1 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s @@ -72,7 +72,7 @@ .type _tx_thread_stack_build, function _tx_thread_stack_build: /* Build a fake interrupt frame. The form of the fake interrupt stack - on the Cortex-M33 should look like the following after it is built: + on the Cortex-M should look like the following after it is built: Stack Top: LR Interrupted LR (LR at time of PENDSV) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c index 8d892e6c..4d3bbee7 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_handler.c @@ -38,7 +38,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/GNU */ +/* _tx_thread_stack_error_handler Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c index 6c2006ad..d61a27b3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_error_notify.c @@ -35,7 +35,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/GNU */ +/* _tx_thread_stack_error_notify Cortex-M33 */ /* 6.1 */ /* AUTHOR */ /* */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s index a053e85f..ed3b627b 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s @@ -75,14 +75,21 @@ _tx_thread_system_return: replaced with in-line assembly in tx_port.h to improved performance. */ MOV r0, #0x10000000 // Load PENDSVSET bit - LDR r1, =0xE000E000 // Load NVIC base + MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller // } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s index 5e5311a3..13deac48 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s @@ -36,8 +36,7 @@ /* This function processes the hardware timer interrupt. This */ /* processing includes incrementing the system clock and checking for */ /* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ +/* expiration functions are called. */ /* */ /* INPUT */ /* */ @@ -63,8 +62,8 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -/* VOID _tx_timer_interrupt(VOID) -{ */ +// VOID _tx_timer_interrupt(VOID) +// { .section .text .balign 4 .syntax unified @@ -74,8 +73,7 @@ .type _tx_timer_interrupt, function _tx_timer_interrupt: - /* Upon entry to this routine, it is assumed that context save has already - been called, and therefore the compiler scratch registers are available + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available for use. */ /* Increment the system clock. */ @@ -92,22 +90,23 @@ _tx_timer_interrupt: LDR r3, =_tx_timer_time_slice // Pickup address of time-slice LDR r2, [r3, #0] // Pickup time-slice - CBZ r2, __tx_timer_no_time_slice // Is it non-active? + CBZ r2, __tx_timer_no_time_slice // Is it non-active? // Yes, skip time-slice processing - /* Decrement the time_slice. */ - // _tx_timer_time_slice--; + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; SUB r2, r2, #1 // Decrement the time-slice STR r2, [r3, #0] // Store new time-slice value - /* Check for expiration. */ - // if (__tx_timer_time_slice == 0) + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing - /* Set the time-slice expired flag. */ - // _tx_timer_expired_time_slice = TX_TRUE; + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag MOV r0, #1 // Build expired value @@ -127,8 +126,8 @@ __tx_timer_no_time_slice: CBZ r2, __tx_timer_no_timer // Is there anything in the list? // No, just increment the timer - /* Set expiration flag. */ - // _tx_timer_expired = TX_TRUE; + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; LDR r3, =_tx_timer_expired // Pickup expiration flag address MOV r2, #1 // Build expired value @@ -140,21 +139,21 @@ __tx_timer_no_time_slice: // { __tx_timer_no_timer: - /* No timer expired, increment the timer pointer. */ - // _tx_timer_current_ptr++; + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; ADD r0, r0, #4 // Move to next timer - /* Check for wrap-around. */ - // if (_tx_timer_current_ptr == _tx_timer_list_end) + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) LDR r3, =_tx_timer_list_end // Pickup addr of timer list end LDR r2, [r3, #0] // Pickup list end CMP r0, r2 // Are we at list end? BNE __tx_timer_skip_wrap // No, skip wrap-around logic - /* Wrap to beginning of list. */ - // _tx_timer_current_ptr = _tx_timer_list_start; + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; LDR r3, =_tx_timer_list_start // Pickup addr of timer list start LDR r0, [r3, #0] // Set current pointer to list start @@ -166,7 +165,6 @@ __tx_timer_skip_wrap: __tx_timer_done: - /* See if anything has expired. */ // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) // { @@ -182,7 +180,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -194,8 +192,8 @@ __tx_something_expired: CBZ r0, __tx_timer_dont_activate // Check for timer expiration // If not set, skip timer activation - /* Process timer expiration. */ - // _tx_timer_expiration_process(); + /* Process timer expiration. */ + // _tx_timer_expiration_process(); BL _tx_timer_expiration_process // Call the timer expiration handling routine @@ -211,8 +209,8 @@ __tx_timer_dont_activate: CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set // No, skip time-slice processing - /* Time slice interrupted thread. */ - // _tx_thread_time_slice(); + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); BL _tx_thread_time_slice // Call time-slice processing LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag @@ -223,17 +221,17 @@ __tx_timer_dont_activate: LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address LDR r3, [r2] // Pickup the execute thread pointer LDR r0, =0xE000ED04 // Build address of control register - MOV r2, 0x10000000 // Build value for PendSV bit + LDR r2, =0x10000000 // Build value for PendSV bit CMP r1, r3 // Are they the same? BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment // } @@ -241,6 +239,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } .end diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..aaddb639 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c index f8207c68..2c73a8e6 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 1ad9a959..f9f47a1e 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* _txm_module_manager_alignment_adjust Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 9b2092a9..9ef10652 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* _txm_module_manager_external_memory_enable Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 945cf50d..2a2026d6 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_handler Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 1392d3aa..9a88f5df 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_notify Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 4bd99c30..5ad546a3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,7 +29,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* _txm_module_manager_mm_register_setup Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ @@ -123,7 +123,7 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* _txm_module_manager_inside_data_check Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c index a9945344..c84c30b2 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_port_dispatch Cortex-M33/GENERIC */ -/* 6.1.5 */ +/* _txm_module_manager_port_dispatch Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index bcbb0da3..46b9353e 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -27,8 +27,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* _txm_module_manager_thread_stack_build Cortex-M33/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ diff --git a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s index e58c20a1..1ba0a002 100644 --- a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s @@ -1,26 +1,25 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) Microsoft Corporation. All rights reserved. */ -;/* */ -;/* This software is licensed under the Microsoft Software License */ -;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -;/* and in the root directory of this software. */ -;/* */ -;/**************************************************************************/ -; -; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_timer_interrupt @@ -28,126 +27,112 @@ EXTERN __vector_table EXTERN _tx_thread_current_ptr EXTERN _tx_thread_stack_error_handler -; -; + SYSTEM_CLOCK EQU 96000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) -; -; + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start DS32 4 -; -; + SECTION `.text`:CODE:NOROOT(2) THUMB - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M33/IAR */ -;/* 6.0.1 */ -;/* AUTHOR */ -;/* */ -;/* Scott Larson, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* */ -;/**************************************************************************/ -;VOID _tx_initialize_low_level(VOID) -;{ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { PUBLIC _tx_initialize_low_level _tx_initialize_low_level: -; -; /* Disable interrupts during ThreadX initialization. */ -; + + /* Disable interrupts during ThreadX initialization. */ CPSID i -; -; /* Set base of available memory to end of non-initialised RAM area. */ -; - LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer - LDR r1, =__tx_free_memory_start ; Build first free address - STR r1, [r0] ; Setup first unused memory pointer -; -; /* Setup Vector Table Offset Register. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers - LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address -; -; /* Enable the cycle count register. */ -; -; LDR r0, =0xE0001000 ; Build address of DWT register -; LDR r1, [r0] ; Pickup the current value -; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register -; -; /* Set system stack pointer from vector value. */ -; - LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer - LDR r1, =__vector_table ; Pickup address of vector table - LDR r1, [r1] ; Pickup reset stack pointer - STR r1, [r0] ; Save system stack pointer -; -; /* Configure SysTick. */ -; - MOV r0, #0xE000E000 ; Build address of NVIC registers + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__tx_free_memory_start // Build first free address + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =__vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] ; Setup SysTick Reload Value - MOV r1, #0x7 ; Build SysTick Control Enable Value - STR r1, [r0, #0x10] ; Setup SysTick Control -; -; /* Configure handler priorities. */ -; - LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control - LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers - ; Note: SVC must be lowest priority, which is 0xFF + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF - LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers - ; Note: PnSV must be lowest priority, which is 0xFF -; -; /* Return to caller. */ -; + /* Return to caller. */ BX lr -;} -; -; -;/* Define shells for each of the unused vectors. */ -; +// } + + +/* Define shells for each of the unused vectors. */ + PUBLIC __tx_BadHandler __tx_BadHandler: B __tx_BadHandler @@ -155,30 +140,39 @@ __tx_BadHandler: PUBLIC __tx_IntHandler __tx_IntHandler: -; VOID InterruptHandler (VOID) -; { - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) - -; /* Do interrupt handler work here */ -; /* .... */ - +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + /* Do interrupt handler work here */ + /* .... */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC __tx_SysTickHandler PUBLIC SysTick_Handler SysTick_Handler: __tx_SysTickHandler: -; VOID TimerInterruptHandler (VOID) -; { -; - PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_enter // Call the ISR enter function +#endif BL _tx_timer_interrupt +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + BL _tx_execution_isr_exit // Call the ISR exit function +#endif POP {r0,lr} - BX LR -; } + BX lr +// } PUBLIC HardFault_Handler HardFault_Handler: @@ -187,55 +181,55 @@ HardFault_Handler: PUBLIC UsageFault_Handler UsageFault_Handler: - CPSID i ; Disable interrupts - ; Check for stack limit fault - LDR r0, =0xE000ED28 ; CFSR address - LDR r1,[r0] ; Pick up CFSR - TST r1, #0x00100000 ; Check for Stack Overflow + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow _unhandled_usage_loop - BEQ _unhandled_usage_loop ; If not stack overflow then loop - - ; Handle stack overflow - STR r1, [r0] ; Clear CFSR flag(s) - + BEQ _unhandled_usage_loop // If not stack overflow then loop + + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) + #ifdef __ARMVFP__ - LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address - LDR r1, [r0] ; Load FPCCR - BIC r1, r1, #1 ; Clear the lazy preservation active bit - STR r1, [r0] ; Store the value + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value #endif - - MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address - LDR r0,[r0] ; Pick up current thread pointer - PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) - BL _tx_thread_stack_error_handler ; Call ThreadX/user handler - POP {r0,lr} ; Restore LR and dummy reg - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - ; Call the thread exit function to indicate the thread is no longer executing. - PUSH {r0, lr} ; Save LR (and r0 just for alignment) - BL _tx_execution_thread_exit ; Call the thread exit function - POP {r0, lr} ; Recover LR + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR #endif - - MOV r1, #0 ; Build NULL value - LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer - STR r1, [r0] ; Clear current thread pointer - - ; Return from UsageFault_Handler exception - LDR r0, =0xE000ED04 ; Load ICSR - LDR r1, =0x10000000 ; Set PENDSVSET bit - STR r1, [r0] ; Store ICSR - DSB ; Wait for memory access to complete - CPSIE i ; Enable interrupts - BX lr ; Return from exception + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception PUBLIC __tx_NMIHandler __tx_NMIHandler: B __tx_NMIHandler - - + + PUBLIC __tx_DBGHandler __tx_DBGHandler: B __tx_DBGHandler diff --git a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h index c2779f40..0a2bdd67 100644 --- a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s index e6b64c8b..19f225d6 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s @@ -27,16 +27,15 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_context_restore Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is only needed for legacy applications and it should */ -/* not be called in any new development on a Cortex-M. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -58,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -66,7 +65,7 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function @@ -74,6 +73,5 @@ _tx_thread_context_restore: #endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s index 7df6a4f2..1e725265 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s @@ -27,16 +27,15 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_context_save Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is only needed for legacy applications and it should */ -/* not be called in any new development on a Cortex-M. */ +/* This function is not needed for Cortex-M. */ /* */ /* INPUT */ /* */ @@ -48,7 +47,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -66,15 +65,13 @@ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return. */ - BX lr // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s index 0086829d..45e5c5de 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_control Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,17 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s index c6853ed1..68421f0e 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_disable Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,19 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s index f4e46f8b..c590eb13 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_interrupt_restore Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,18 +57,19 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: - /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 861e2946..a584c2b7 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -41,8 +41,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Cortex-M33/MPU/IAR */ -/* 6.1.7 */ +/* _tx_thread_schedule Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -87,37 +87,31 @@ // { PUBLIC _tx_thread_schedule _tx_thread_schedule: - /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ - MOV r0, #0 // Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ - #ifdef __ARMVFP__ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register #endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ - MOV r0, #0x10000000 // Load PENDSVSET bit MOV r1, #0xE000E000 // Load NVIC base STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR @@ -234,12 +228,9 @@ BusFault_Handler: PUBLIC PendSV_Handler PendSV_Handler: - - /* Get current thread value and new thread pointer. */ - __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -350,7 +341,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -413,8 +404,6 @@ _skip_vfp_restore: LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer - /* Return to thread. */ - BX lr // Return to thread! @@ -435,7 +424,7 @@ SVC_Handler: CMP r2, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE CMP r2, #3 // Is it the entry into ThreadX? @@ -444,7 +433,7 @@ SVC_Handler: /* At this point we have an SVC 3, which means we are entering the kernel from a module thread with user mode selected. */ - LDR r2, =_txm_module_priv // Load address of where we should have come from + LDR r2, =_txm_module_priv-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_entry? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -501,7 +490,7 @@ _tx_skip_kernel_stack_enter: _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + LDR r2, =_txm_module_user_mode_exit-1 // Load address of where we should have come from CMP r1, r2 // Did we come from user_mode_exit? IT NE // If no (not equal), then... BXNE lr // return from where we came @@ -527,6 +516,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -536,14 +546,14 @@ _tx_thread_user_return: ORREQ lr, lr, #0x10 // Else set bit, return with standard frame /* Copy kernel hardware stack to module thread stack. */ - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} - LDM r3!, {r1-r2} - STM r0!, {r1-r2} + LDM r3!, {r1-r2} // Get r0, r1 from kernel stack + STM r0!, {r1-r2} // Insert r0, r1 into thread stack + LDM r3!, {r1-r2} // Get r2, r3 from kernel stack + STM r0!, {r1-r2} // Insert r2, r3 into thread stack + LDM r3!, {r1-r2} // Get r12, lr from kernel stack + STM r0!, {r1-r2} // Insert r12, lr into thread stack + LDM r3!, {r1-r2} // Get pc, xpsr from kernel stack + STM r0!, {r1-r2} // Insert pc, xpsr into thread stack SUB r0, r0, #32 // Subtract 32 to get back to top of stack MSR PSP, r0 // Set thread stack pointer @@ -560,7 +570,7 @@ _tx_skip_kernel_stack_exit: #if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) _tx_svc_secure_alloc: - LDR r2, =_tx_alloc_return // Load address of where we should have come from + LDR r2, =_tx_alloc_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -573,7 +583,7 @@ _tx_svc_secure_alloc: BX lr _tx_svc_secure_free: - LDR r2, =_tx_free_return // Load address of where we should have come from + LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. @@ -584,11 +594,11 @@ _tx_svc_secure_free: POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr -#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ EXTERN _txm_module_manager_kernel_dispatch SECTION `.text`:CODE:NOROOT(5) @@ -623,5 +633,4 @@ _txm_module_user_mode_exit: _tx_vfp_access: VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c index 844f8175..64006f59 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c @@ -62,8 +62,8 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ -/* 6.1.1 */ +/* _tx_thread_secure_mode_stack_initialize Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -78,7 +78,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* OUTPUT */ /* */ -/* None */ +/* status */ /* */ /* CALLS */ /* */ @@ -98,21 +98,34 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 10-16-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.1 */ +/* 08-02-2021 Scott Larson Change name, execute in */ +/* handler mode, */ +/* resulting in version 6.1.8 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) -void _tx_thread_secure_stack_initialize(void) +UINT _tx_thread_secure_mode_stack_initialize(void) { - - /* Set secure mode to use PSP. */ - __set_CONTROL(__get_CONTROL() | 2); - - /* Set process stack pointer and stack limit to 0 to throw exception when a thread - without a secure stack calls a secure function that tries to use secure stack. */ - __set_PSPLIM(0); - __set_PSP(0); - - return; +UINT status; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else + { + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + status = TX_SUCCESS; + } + return status; } @@ -291,7 +304,7 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) { UINT status; TX_THREAD_SECURE_STACK_INFO *info_ptr; - + status = TX_SUCCESS; /* Pickup stack info from thread. */ @@ -376,7 +389,7 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) { TX_THREAD_SECURE_STACK_INFO *info_ptr; ULONG sp; - + /* This function should be called from scheduler only. */ if (__get_IPSR() == 0) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 560d8f03..c718d34a 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - SECTION `.text`:CODE:NOROOT(2) THUMB /**************************************************************************/ @@ -82,5 +81,4 @@ _tx_alloc_return: #endif _alloc_return_interrupt_enabled BX lr - END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s index b962fc70..e1875b7c 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - SECTION `.text`:CODE:NOROOT(2) THUMB /**************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s index 5bf333d1..d4131978 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_stack_build Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,14 +59,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { PUBLIC _tx_thread_stack_build _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: @@ -94,7 +93,11 @@ _tx_thread_stack_build: LDR r2, [r0, #16] // Pickup end of stack area BIC r2, r2, #0x7 // Align frame for 8-byte alignment SUB r2, r2, #68 // Subtract frame size - LDR r3, =0xFFFFFFFD // Build initial LR value +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif STR r3, [r2, #0] // Save on the stack /* Actually build the stack frame. */ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c index 27ac5c42..4d3bbee7 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_handler.c @@ -28,8 +28,8 @@ #include "tx_api.h" #include "tx_thread.h" -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -38,8 +38,8 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_handler Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,12 +70,11 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { - #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR /* Is there a thread? */ if (thread_ptr) @@ -88,10 +87,7 @@ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) /* Determine if the application has registered an error handler. */ if (_tx_thread_application_stack_error_handler != TX_NULL) { - /* Yes, an error handler is present, simply call the application error handler. */ (_tx_thread_application_stack_error_handler)(thread_ptr); } - } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c index 328103b2..d61a27b3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_error_notify.c @@ -35,8 +35,8 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_error_notify Cortex-M33/IAR */ -/* 6.1 */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) @@ -76,7 +76,6 @@ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *threa TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ TX_DISABLE @@ -95,4 +94,3 @@ TX_INTERRUPT_SAVE_AREA /* Return success to caller. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s index 3a180138..2b8aea89 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_thread_system_return Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,14 +59,13 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { PUBLIC _tx_thread_system_return _tx_thread_system_return: - /* Return to real scheduler via PendSV. Note that this routine is often replaced with in-line assembly in tx_port.h to improved performance. */ @@ -76,11 +75,17 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s index c2dfae5c..f13e9f0f 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s @@ -39,8 +39,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M/IAR */ -/* 6.1.5 */ +/* _tx_timer_interrupt Cortex-M33/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -188,7 +188,7 @@ __tx_timer_done: __tx_something_expired: - STMDB sp!, {r0, lr} // Save the lr register on the stack + PUSH {r0, lr} // Save the lr register on the stack // and save r0 just to keep 8-byte alignment /* Did a timer expire? */ @@ -234,12 +234,11 @@ __tx_timer_dont_activate: BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed STR r2, [r0] // Not the same, issue the PendSV for preemption __tx_timer_skip_time_slice: - // } __tx_timer_not_ts_expiration: - LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + POP {r0, lr} // Recover lr register (r0 is just there for // the 8-byte stack alignment // } @@ -248,6 +247,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 3ff6fa68..aaddb639 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.1 */ +/* _tx_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) @@ -84,7 +84,6 @@ UINT status; /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -92,7 +91,6 @@ UINT status; /* Now check for invalid thread ID. */ else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) { - /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } @@ -111,7 +109,6 @@ UINT status; /* Determine if everything is okay. */ if (status == TX_SUCCESS) { - /* Call actual secure stack allocate function. */ status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); } @@ -120,4 +117,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c index f8207c68..2c73a8e6 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.1 */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) @@ -118,4 +118,3 @@ UINT status; return(status); #endif } - diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 19f65bfc..8cb93534 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_alignment_adjust Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_alignment_adjust Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c index dca26152..67bc7196 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -33,8 +33,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_external_memory_enable Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_external_memory_enable Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 0b974872..0ed0c212 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -45,8 +45,8 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_handler Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_handler Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 618a699e..88baa804 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -38,8 +38,8 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_memory_fault_notify Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_memory_fault_notify Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 4bd99c30..5ad546a3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,7 +29,7 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* _txm_module_manager_mm_register_setup Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ @@ -123,7 +123,7 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* _txm_module_manager_inside_data_check Cortex-M33 */ /* 6.1.6 */ /* AUTHOR */ /* */ diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c index 7c7e01ea..977107d1 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -30,8 +30,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_port_dispatch Cortex-M33/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_port_dispatch Cortex-M33 */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s index b10b9c97..d2d5e91b 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -26,8 +26,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_thread_stack_build Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_thread_stack_build Cortex-M33/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S index c06f4b07..15238789 100644 --- a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S @@ -135,8 +135,8 @@ Reset_Handler /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index b9d2ea5b..443935e7 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -40,11 +40,11 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* increase kernel stack size, */ /* resulting in version 6.1.2 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ +/* 04-02-2021 Scott Larson Modified comment(s), */ /* added check for overflow, */ /* resulting in version 6.1.6 */ /* */ @@ -107,6 +107,21 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif + /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S index e965b809..f3952da6 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c index 490b35db..33b1e5a5 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -90,7 +90,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -107,14 +107,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S index 65f7d711..1159ea66 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,14 +69,13 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0,lr} // Save ISR lr + PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0,lr} // Restore ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - POP {lr} BX lr // } ALIGN diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S index c05300fe..d8ee75a4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -71,16 +69,16 @@ EXPORT _tx_thread_context_save _tx_thread_context_save - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR enter function to indicate an ISR is executing. */ - PUSH {r0, lr} // Save ISR lr +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function - POP {r0, lr} // Recover ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - /* Return to interrupt processing. */ + /* Context is already saved - just return. */ - BX lr // Return to interrupt processing caller + BX lr // } ALIGN LTORG diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S index 3c574171..4c5e1c33 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -56,19 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { EXPORT _tx_thread_interrupt_control _tx_thread_interrupt_control +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S index cee8330d..88e6a864 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -56,21 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { EXPORT _tx_thread_interrupt_disable _tx_thread_interrupt_disable - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S index 9287a2e8..22340c21 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -56,20 +56,20 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { EXPORT _tx_thread_interrupt_restore _tx_thread_interrupt_restore /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S index 04b90b44..71275358 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.S @@ -23,15 +23,15 @@ IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit - ENDIF +#endif IMPORT _tx_thread_preempt_disable IMPORT _txm_module_manager_memory_fault_handler IMPORT _txm_module_manager_memory_fault_info - IMPORT _txm_module_priv - IMPORT _txm_module_user_mode_exit + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit AREA ||.text||, CODE, READONLY THUMB @@ -90,7 +90,7 @@ _tx_thread_schedule /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -98,22 +98,19 @@ _tx_thread_schedule LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register - ENDIF +#endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -135,7 +132,6 @@ __tx_wait_here EXPORT MemManage_Handler MemManage_Handler - CPSID i // Disable interrupts /* Now pickup and store all the fault related information. */ @@ -194,21 +190,21 @@ MemManage_Handler // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit - STR r1, [r0] // Store the value - ENDIF + STR r1, [r0] // Save FPCCR +#endif BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts - ENDIF +#endif MOV r1, #0 // Build NULL value LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer @@ -235,14 +231,14 @@ __tx_PendSVHandler __tx_ts_handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR CPSIE i // Enable interrupts - ENDIF +#endif LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address @@ -258,12 +254,12 @@ __tx_ts_handler STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers _skip_vfp_save - ENDIF +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -335,12 +331,12 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 - ENDIF +#endif /* Restore the thread context and PSP. */ @@ -372,12 +368,12 @@ __tx_ts_restore STR r1, [r0] // Enable MPU skip_mpu_setup LDMIA r12!, {LR} // Pickup LR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers _skip_vfp_restore - ENDIF +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -425,22 +421,26 @@ __tx_SVCallHandler /* Switch to the module thread's kernel stack */ LDR r0, [r2, #0xA8] // Load the module kernel stack end - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r1, [r2, #0xA4] // Load the module kernel stack start LDR r3, [r2, #0xAC] // Load the module kernel stack size STR r1, [r2, #12] // Set stack start STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __TARGET_FPU_VFP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __TARGET_FPU_VFP BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -478,21 +478,46 @@ _tx_thread_user_return TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_exit - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r0, [r2, #0xB4] // Load the module thread stack start LDR r1, [r2, #0xB8] // Load the module thread stack end LDR r3, [r2, #0xBC] // Load the module thread stack size STR r0, [r2, #12] // Set stack start STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif + +#ifdef __TARGET_FPU_VFP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __TARGET_FPU_VFP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -516,7 +541,7 @@ _tx_skip_kernel_stack_exit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP EXPORT tx_thread_fpu_enable tx_thread_fpu_enable EXPORT tx_thread_fpu_disable @@ -526,13 +551,13 @@ tx_thread_fpu_disable backward compatibility purposes and therefore simply returns. */ BX LR // Return to caller - + EXPORT _tx_vfp_access _tx_vfp_access VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - - ENDIF + +#endif ALIGN 4 END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S index 0ccd8d6f..11effa55 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S index fd7eec6b..0ab4ae36 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -77,11 +75,17 @@ _tx_thread_system_return MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S index b1a58dd9..12fef571 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.S @@ -39,11 +39,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M4/AC5 */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -73,9 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -113,6 +111,7 @@ _tx_timer_interrupt // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -249,7 +248,6 @@ __tx_timer_nothing_expired DSB // Complete all memory access BX lr // Return to caller - // } ALIGN LTORG diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 2f945552..f91a8fae 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 3eed0481..df025827 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 9efd8bdc..44c01f1e 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 43a782f1..e4d38642 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index b48dada5..6fa28af7 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S index 032975e2..62e944a1 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S index 83d6f960..f9b136a2 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c index 0f99ad4a..1c51577d 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -89,7 +89,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,14 +106,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S index 7420808c..17a79b0f 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif + .text .align 4 .syntax unified @@ -27,11 +31,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M4/AC6 */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -58,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S index 79938754..511ca82e 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S @@ -23,15 +23,18 @@ .text .align 4 .syntax unified +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M4/AC6 */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -68,6 +69,15 @@ .global _tx_thread_context_save .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S index 10d5f0b2..07d2a131 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M4/AC6 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -68,9 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S index 84f6ed47..ff2cd85a 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S @@ -20,17 +20,20 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit #endif - .text .align 4 .syntax unified @@ -90,7 +93,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -98,9 +101,8 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - #ifdef __ARM_FP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -113,7 +115,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -132,7 +133,6 @@ __tx_wait_here: /* Memory Exception Handler. */ - .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -210,7 +210,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -245,7 +245,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -345,7 +345,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -444,6 +444,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -496,6 +497,29 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __ARM_FP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -530,7 +554,7 @@ _tx_skip_kernel_stack_exit: /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch - .align 5 + .align 5 .syntax unified // VOID _txm_module_manager_user_mode_entry(VOID) // { @@ -558,12 +582,14 @@ _txm_module_user_mode_exit: // } #ifdef __ARM_FP - .global tx_thread_fpu_disable - .thumb_func -tx_thread_fpu_disable: + .global tx_thread_fpu_enable .thumb_func tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for backward compatibility purposes and therefore simply returns. */ diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S index ca5be793..d50f9243 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M4/AC6 */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S index 48f8bfd6..6560db62 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S @@ -20,7 +20,6 @@ /**************************************************************************/ /**************************************************************************/ - .text 32 .align 4 .syntax unified @@ -28,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M4/AC6 */ -/* 6.1 */ +/* _tx_thread_system_return Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -61,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -79,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S index 8ef8f9fd..46f54da0 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,15 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -37,11 +37,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M4/AC6 */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -71,9 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -249,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 10319892..09676039 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index d0f2240b..a8b7c14f 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 58c4a1be..6468b4cb 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 649b1ad2..f8689bb9 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 8861ab56..78427ab2 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4d8f8fc0..7812baf3 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -75,7 +75,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 @@ -112,7 +112,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block diff --git a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_library.bat index 3c672eb3..992028ec 100644 --- a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_library.bat +++ b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_library.bat @@ -1,102 +1,102 @@ del txm.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc 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..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o diff --git a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat index 5a71cf8c..f146d743 100644 --- a/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_m4/gnu/example_build/build_threadx_module_sample.bat @@ -1,5 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=vfpv4 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c arm-none-eabi-ld -A cortex-m4 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld index a33fbfeb..30c66655 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld @@ -9,8 +9,8 @@ SECTIONS { __FLASH_segment_start__ = 0x00030000; __FLASH_segment_end__ = 0x00040000; - __RAM_segment_start__ = 0; - __RAM_segment_end__ = 0x8000; + __RAM_segment_start__ = 0x10000000; + __RAM_segment_end__ = 0x10008000; __HEAPSIZE__ = 128; @@ -136,7 +136,7 @@ SECTIONS } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - __code_size__ = __rodata_end__ - __FLASH_segment_start__; + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c index 212cc5fe..36f6adb7 100644 --- a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S index e693ef46..e445e690 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif + .text .align 4 .syntax unified @@ -27,11 +31,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -58,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S index 9d8ad6a1..e4f2778a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +48,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -69,6 +67,14 @@ .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 64a7a486..99e14c06 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -68,9 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S index 8cfc88ad..8716a253 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S @@ -20,15 +20,18 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info - + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif .text .align 4 .syntax unified @@ -88,7 +91,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -96,7 +99,7 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ #ifdef __ARM_PCS_VFP MRS r0, CONTROL // Pickup current CONTROL register @@ -111,7 +114,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -130,7 +132,6 @@ __tx_wait_here: /* Memory Exception Handler. */ - .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -208,7 +209,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -243,7 +244,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -343,7 +344,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -443,6 +444,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -450,7 +452,7 @@ __tx_SVCallHandler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -495,6 +497,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -557,12 +580,14 @@ _txm_module_user_mode_exit: // } #ifdef __ARM_PCS_VFP - .global tx_thread_fpu_disable - .thumb_func -tx_thread_fpu_disable: + .global tx_thread_fpu_enable .thumb_func tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for backward compatibility purposes and therefore simply returns. */ diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S index c2802386..d0246c13 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S index 2ffdaab4..1f20e1a6 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -80,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S index 50202fdb..9551a2b2 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -20,15 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -37,11 +37,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M4/GNU */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -71,9 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -112,6 +110,7 @@ _tx_timer_interrupt: // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -248,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 7842572e..b6c79053 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 22bc194f..c5682545 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index c349ccc2..7ba3e553 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 44f6f74b..46ac8d8f 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 9869aa62..54e7c87a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 4eb822cf..4ddbe47a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -75,7 +75,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c index 3525846e..ac511f35 100644 --- a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s index b2535fe1..0a188df9 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,14 +66,13 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0, lr} // Save return address - BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0, lr} // Save return address + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address #endif - POP {lr} BX lr // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s index 7d33621f..e71ae496 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +48,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,25 +58,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ - PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return! */ + /* Context is already saved - just return. */ BX lr // } diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s index 342fe118..c0d9d095 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -57,19 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s index 19f49ba7..86fcf188 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -39,11 +39,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -57,21 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s index 51aac293..f9603de1 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -39,11 +39,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -57,20 +57,19 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: - /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s index d2d66f6c..a7efd980 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s @@ -86,7 +86,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -94,9 +94,8 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - #ifdef __ARMVFP__ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -109,7 +108,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -203,7 +201,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -235,7 +233,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -335,7 +333,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -433,6 +431,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -486,6 +485,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -517,7 +537,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ EXTERN _txm_module_manager_kernel_dispatch SECTION `.text`:CODE:NOROOT(5) @@ -547,8 +567,8 @@ _txm_module_user_mode_exit: NOP // } - #ifdef __ARMVFP__ + PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable @@ -560,5 +580,4 @@ tx_thread_fpu_disable: BX LR // Return to caller #endif - END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s index 8292b338..dcc82bf6 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -69,7 +67,6 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s index cdc6deab..4c5cb6fb 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -59,15 +59,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: /* Return to real scheduler via PendSV. Note that this routine is often @@ -79,11 +76,17 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s index 6f3ab6b0..aa209956 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s @@ -39,11 +39,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M4/IAR */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -73,9 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -113,6 +111,7 @@ _tx_timer_interrupt: // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -249,6 +248,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 27c1759d..514a9c6e 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 635b617b..674c7ce6 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 6b63fe46..98081a32 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 0e5b94c8..06905f05 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index d337bbaa..7fea500f 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -261,7 +261,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index dabb4224..d5fe691d 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -73,7 +73,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S index ddc22944..960842e3 100644 --- a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S @@ -135,8 +135,8 @@ Reset_Handler /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index 539a4f19..7475d6d6 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -211,7 +211,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT #else /* TXM_MODULE_MANAGER_8_MPU is defined */ /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + If TXM_MODULE_MANAGER_8_MPU is defined, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S index ed1e063c..fc9f21f2 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c index cb74cdd3..ffb82204 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -90,7 +90,7 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -107,14 +107,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S index e552ff25..1159ea66 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -71,14 +69,13 @@ EXPORT _tx_thread_context_restore _tx_thread_context_restore - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0,lr} // Save ISR lr + PUSH {r0, lr} // Save return address BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0,lr} // Restore ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - POP {lr} BX lr // } ALIGN diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S index cc20bbed..d8ee75a4 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.S @@ -20,9 +20,9 @@ /**************************************************************************/ /**************************************************************************/ - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter - ENDIF +#endif AREA ||.text||, CODE, READONLY PRESERVE8 @@ -30,11 +30,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -51,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -61,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -71,16 +69,16 @@ EXPORT _tx_thread_context_save _tx_thread_context_save - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* Call the ISR enter function to indicate an ISR is executing. */ - PUSH {r0, lr} // Save ISR lr +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function - POP {r0, lr} // Recover ISR lr - ENDIF + POP {r0, lr} // Recover return address +#endif - /* Return to interrupt processing. */ + /* Context is already saved - just return. */ - BX lr // Return to interrupt processing caller + BX lr // } ALIGN LTORG diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S index f5c0ecb4..4c5e1c33 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -56,19 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { EXPORT _tx_thread_interrupt_control _tx_thread_interrupt_control +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S index 3107c3fb..88e6a864 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_disable Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -56,21 +56,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { EXPORT _tx_thread_interrupt_disable _tx_thread_interrupt_disable - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S index 0b7bc852..22340c21 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_restore Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -38,11 +38,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -56,20 +56,20 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { EXPORT _tx_thread_interrupt_restore _tx_thread_interrupt_restore /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S index 31897e33..24ea67f8 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.S @@ -23,15 +23,15 @@ IMPORT _tx_thread_current_ptr IMPORT _tx_thread_execute_ptr IMPORT _tx_timer_time_slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit - ENDIF +#endif IMPORT _tx_thread_preempt_disable IMPORT _txm_module_manager_memory_fault_handler IMPORT _txm_module_manager_memory_fault_info - IMPORT _txm_module_priv - IMPORT _txm_module_user_mode_exit + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit AREA ||.text||, CODE, READONLY THUMB @@ -91,7 +91,7 @@ _tx_thread_schedule /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -99,22 +99,19 @@ _tx_thread_schedule LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register - ENDIF +#endif /* Enable memory fault registers. */ - LDR r0, =0xE000ED24 // Build SHCSR address LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -136,7 +133,6 @@ __tx_wait_here EXPORT MemManage_Handler MemManage_Handler - CPSID i // Disable interrupts /* Now pickup and store all the fault related information. */ @@ -195,21 +191,21 @@ MemManage_Handler // Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] // Clear the MMFSR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address LDR r1, [r0] // Load FPCCR BIC r1, r1, #1 // Clear the lazy preservation active bit - STR r1, [r0] // Store the value - ENDIF + STR r1, [r0] // Save FPCCR +#endif BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function CPSIE i // Enable interrupts - ENDIF +#endif MOV r1, #0 // Build NULL value LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer @@ -236,14 +232,14 @@ __tx_PendSVHandler __tx_ts_handler - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) BL _tx_execution_thread_exit // Call the thread exit function POP {r0, lr} // Recover LR CPSIE i // Enable interrupts - ENDIF +#endif LDR r0, =_tx_thread_current_ptr // Build current thread pointer address LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address @@ -259,12 +255,12 @@ __tx_ts_handler STR r3, [r0] // Set _tx_thread_current_ptr to NULL MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} // Save its remaining registers - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers _skip_vfp_save - ENDIF +#endif LDR r4, =_tx_timer_time_slice // Build address of time-slice variable STMDB r12!, {LR} // Save LR on the stack @@ -336,12 +332,12 @@ __tx_ts_restore STR r5, [r4] // Setup global time-slice - IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function POP {r0, r1} // Recover r0 and r1 - ENDIF +#endif /* Restore the thread context and PSP. */ @@ -384,12 +380,12 @@ __tx_ts_restore STR r1, [r0] // Enable MPU skip_mpu_setup LDMIA r12!, {LR} // Pickup LR - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP TST LR, #0x10 // Determine if the VFP extended frame is present BNE _skip_vfp_restore // If not, skip VFP restore VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers _skip_vfp_restore - ENDIF +#endif LDMIA r12!, {r4-r11} // Recover thread's registers MSR PSP, r12 // Setup the thread's stack pointer @@ -437,22 +433,26 @@ __tx_SVCallHandler /* Switch to the module thread's kernel stack */ LDR r0, [r2, #0xA8] // Load the module kernel stack end - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r1, [r2, #0xA4] // Load the module kernel stack start LDR r3, [r2, #0xAC] // Load the module kernel stack size STR r1, [r2, #12] // Set stack start STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif MRS r3, PSP // Pickup thread stack pointer +#ifdef __TARGET_FPU_VFP TST lr, #0x10 // Test for extended module stack ITT EQ ORREQ r3, r3, #1 // If so, set LSB in thread stack pointer to indicate extended frame ORREQ lr, lr, #0x10 // Set bit, return with standard frame +#endif STR r3, [r2, #0xB0] // Save thread stack pointer +#ifdef __TARGET_FPU_VFP BIC r3, #1 // Clear possibly OR'd bit - +#endif + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -490,21 +490,46 @@ _tx_thread_user_return TST r0, #2 // Check if memory protected BEQ _tx_skip_kernel_stack_exit - IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE LDR r0, [r2, #0xB4] // Load the module thread stack start LDR r1, [r2, #0xB8] // Load the module thread stack end LDR r3, [r2, #0xBC] // Load the module thread stack size STR r0, [r2, #12] // Set stack start STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size - ENDIF +#endif + +#ifdef __TARGET_FPU_VFP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer +#ifdef __TARGET_FPU_VFP TST r0, #1 // Is module stack extended? ITTE NE // If so... BICNE lr, #0x10 // Clear bit, return with extended frame BICNE r0, #1 // Clear bit that indicates extended module frame ORREQ lr, lr, #0x10 // Else set bit, return with standard frame +#endif /* Copy kernel hardware stack to module thread stack. */ LDM r3!, {r1-r2} @@ -528,7 +553,7 @@ _tx_skip_kernel_stack_exit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread - IF {TARGET_FPU_VFP} = {TRUE} +#ifdef __TARGET_FPU_VFP EXPORT tx_thread_fpu_enable tx_thread_fpu_enable EXPORT tx_thread_fpu_disable @@ -538,13 +563,13 @@ tx_thread_fpu_disable backward compatibility purposes and therefore simply returns. */ BX LR // Return to caller - + EXPORT _tx_vfp_access _tx_vfp_access VMOV.F32 s0, s0 // Simply access the VFP BX lr // Return to caller - - ENDIF + +#endif ALIGN 4 END diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S index 6c7a838b..11effa55 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S index c95ade89..0ab4ae36 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.S @@ -25,11 +25,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -77,11 +75,17 @@ _tx_thread_system_return MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S index db18f288..12fef571 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.S @@ -39,11 +39,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M7/AC5 */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/AC5 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -73,9 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -113,6 +111,7 @@ _tx_timer_interrupt // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -249,7 +248,6 @@ __tx_timer_nothing_expired DSB // Complete all memory access BX lr // Return to caller - // } ALIGN LTORG diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 59a8e0d0..1f650e6a 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index b41f07b7..7f4401c6 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 46cb2bcb..acecfef9 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 030bd5cc..fdae069b 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S index 7c169c55..fd99356d 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S index 4fbe496c..d9719c73 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c index 649973db..0aff1526 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -89,7 +89,7 @@ extern VOID _txm_module_initialize(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -106,14 +106,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the ARM C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S index d9a9bcf8..17a79b0f 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif + .text .align 4 .syntax unified @@ -27,11 +31,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -58,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S index f52442a2..511ca82e 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S @@ -23,15 +23,18 @@ .text .align 4 .syntax unified +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_enter +#endif /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +51,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,9 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -68,6 +69,15 @@ .global _tx_thread_context_save .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S index c45d6a86..07d2a131 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -68,9 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index a5e35116..d0117b6a 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -20,17 +20,20 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit #endif - .text .align 4 .syntax unified @@ -91,7 +94,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -99,9 +102,8 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - #ifdef __ARM_FP + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -114,7 +116,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -133,7 +134,6 @@ __tx_wait_here: /* Memory Exception Handler. */ - .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -211,7 +211,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -246,7 +246,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -346,7 +346,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -456,6 +456,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -508,6 +509,29 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + +#ifdef __ARM_FP + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -542,7 +566,7 @@ _tx_skip_kernel_stack_exit: /* Kernel entry function from user mode. */ .global _txm_module_manager_kernel_dispatch - .align 5 + .align 5 .syntax unified // VOID _txm_module_manager_user_mode_entry(VOID) // { @@ -570,12 +594,14 @@ _txm_module_user_mode_exit: // } #ifdef __ARM_FP - .global tx_thread_fpu_disable - .thumb_func -tx_thread_fpu_disable: + .global tx_thread_fpu_enable .thumb_func tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for backward compatibility purposes and therefore simply returns. */ diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S index 350c6858..d50f9243 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index 8a601034..6560db62 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -80,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S index 594d21ce..46f54da0 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -20,15 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -37,11 +37,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M7/AC6 */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/AC6 */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -71,9 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -112,6 +110,7 @@ _tx_timer_interrupt: // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -248,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index d2ac6914..8b6a8619 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 16c9b84b..23153624 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index aa0f502c..8118f5fd 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index ec9e6ba4..24265181 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 86bee185..b501733f 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -75,7 +75,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 @@ -112,7 +112,7 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #28] // Store initial r10 STR r3, [r2, #32] // Store initial r11 - /* Hardware stack follows. */ + /* Hardware stack follows. */ STR r0, [r2, #36] // Store initial r0, which is the thread control block diff --git a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_library.bat index a6660a86..fc07df75 100644 --- a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_library.bat +++ b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_library.bat @@ -1,103 +1,103 @@ del txm.a -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c -arm-none-eabi-gcc -c -g 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..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -mthumb -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_time_get.o txm_time_set.o arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o diff --git a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat index 91aee16b..c4ae437e 100644 --- a/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_m7/gnu/example_build/build_threadx_module_sample.bat @@ -1,5 +1,5 @@ -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S -arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-d16 -fpie -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c arm-none-eabi-ld -A cortex-m7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld index a33fbfeb..30c66655 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld @@ -9,8 +9,8 @@ SECTIONS { __FLASH_segment_start__ = 0x00030000; __FLASH_segment_end__ = 0x00040000; - __RAM_segment_start__ = 0; - __RAM_segment_end__ = 0x8000; + __RAM_segment_start__ = 0x10000000; + __RAM_segment_end__ = 0x10008000; __HEAPSIZE__ = 128; @@ -136,7 +136,7 @@ SECTIONS } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - __code_size__ = __rodata_end__ - __FLASH_segment_start__; + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index 8040d77c..04807d75 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -205,7 +205,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT #else /* TXM_MODULE_MANAGER_8_MPU is defined */ /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 diff --git a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c index c665ebc7..1157f057 100644 --- a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S index b36e091e..e445e690 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -20,6 +20,10 @@ /**************************************************************************/ /**************************************************************************/ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + .global _tx_execution_isr_exit +#endif + .text .align 4 .syntax unified @@ -27,11 +31,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +52,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_exit] Execution profiling ISR exit */ /* */ /* CALLED BY */ /* */ @@ -58,9 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,6 +70,13 @@ .global _tx_thread_context_restore .thumb_func _tx_thread_context_restore: - /* Not needed for this port - just return! */ + +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address +#endif + BX lr // } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S index fc56c7a5..e4f2778a 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +48,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) @@ -69,6 +67,14 @@ .thumb_func _tx_thread_context_save: - /* Not needed for this port - just return! */ +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) + /* Call the ISR enter function to indicate an ISR is starting. */ + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0, lr} // Recover return address +#endif + + /* Context is already saved - just return. */ + BX lr // } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S index 6d7ab8bf..99e14c06 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) @@ -68,9 +66,14 @@ .global _tx_thread_interrupt_control .thumb_func _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index 909d7449..99eb2544 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -20,15 +20,18 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit - .global _tx_thread_preempt_disable - .global _txm_module_manager_memory_fault_handler - .global _txm_module_manager_memory_fault_info - + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_LOW_POWER + .global tx_low_power_enter + .global tx_low_power_exit +#endif .text .align 4 .syntax unified @@ -89,7 +92,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -97,7 +100,7 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ #ifdef __ARM_PCS_VFP MRS r0, CONTROL // Pickup current CONTROL register @@ -112,7 +115,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -131,7 +133,6 @@ __tx_wait_here: /* Memory Exception Handler. */ - .global MemManage_Handler .global BusFault_Handler .global UsageFault_Handler @@ -209,7 +210,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -244,7 +245,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -344,7 +345,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -455,6 +456,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -462,7 +464,7 @@ __tx_SVCallHandler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -507,6 +509,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -569,12 +592,14 @@ _txm_module_user_mode_exit: // } #ifdef __ARM_PCS_VFP - .global tx_thread_fpu_disable - .thumb_func -tx_thread_fpu_disable: + .global tx_thread_fpu_enable .thumb_func tx_thread_fpu_enable: + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for backward compatibility purposes and therefore simply returns. */ diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S index a13a9c17..d0246c13 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -71,7 +69,6 @@ .thumb_func _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index 13b10a60..1f20e1a6 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -60,9 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) @@ -80,10 +78,16 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S index 9048a0e9..9551a2b2 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -20,15 +20,15 @@ /**************************************************************************/ /**************************************************************************/ - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process .text .align 4 @@ -37,11 +37,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M7/GNU */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/GNU */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -71,9 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -112,6 +110,7 @@ _tx_timer_interrupt: // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -248,5 +247,4 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 64efbff0..e5180b13 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 8d09a9e5..bdeb0af5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index e4fd949b..6aa8f56f 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 7460ad0c..c1ff8825 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index bd8df808..2cb58046 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -60,8 +60,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -75,7 +75,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 6659fc5f..309e29a7 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -207,7 +207,7 @@ typedef struct TXM_MODULE_MPU_INFO_STRUCT #else /* TXM_MODULE_MANAGER_8_MPU is defined */ /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M4 parts, there are 8 total entries. ThreadX uses one for access + On some Cortex-M7 parts, there are 8 total entries. ThreadX uses one for access to the kernel entry function, thus 7 remain for code and data protection. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 #define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 diff --git a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c index 25fe42c2..d0ca97e1 100644 --- a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s index 079c5e59..0a188df9 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_context_restore Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -58,9 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) @@ -68,14 +66,13 @@ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR exit function to indicate an ISR is complete. */ - PUSH {r0, lr} // Save return address - BL _tx_execution_isr_exit // Call the ISR exit function - POP {r0, lr} // Save return address + PUSH {r0, lr} // Save return address + BL _tx_execution_isr_exit // Call the ISR exit function + POP {r0, lr} // Recover return address #endif - POP {lr} BX lr // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s index 12dfc292..e71ae496 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s @@ -27,11 +27,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_save Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_context_save Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -48,7 +48,7 @@ /* */ /* CALLS */ /* */ -/* None */ +/* [_tx_execution_isr_enter] Execution profiling ISR enter */ /* */ /* CALLED BY */ /* */ @@ -58,25 +58,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { PUBLIC _tx_thread_context_save _tx_thread_context_save: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ - PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function POP {r0, lr} // Recover return address #endif - /* Context is already saved - just return! */ + /* Context is already saved - just return. */ BX lr // } diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s index 5d22c13c..c0d9d095 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_control Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_control Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -57,19 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Pickup current interrupt posture + MSR BASEPRI, r0 // Apply the new interrupt posture + MOV r0, r1 // Transfer old to return register +#else MRS r1, PRIMASK // Pickup current interrupt lockout MSR PRIMASK, r0 // Apply the new interrupt lockout MOV r0, r1 // Transfer old to return register +#endif BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s index efde50dd..86fcf188 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_disable Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -39,11 +39,11 @@ /* */ /* INPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* None */ /* */ /* OUTPUT */ /* */ -/* None */ +/* old_posture Old interrupt lockout posture */ /* */ /* CALLS */ /* */ @@ -57,21 +57,22 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(UINT new_posture) +// UINT _tx_thread_interrupt_disable(VOID) // { PUBLIC _tx_thread_interrupt_disable _tx_thread_interrupt_disable: - /* Return current interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MRS r0, BASEPRI + LDR r1, =TX_PORT_BASEPRI + MSR BASEPRI, r1 +#else MRS r0, PRIMASK CPSID i +#endif BX lr - // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s index da5af2f0..f9603de1 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_interrupt_restore Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -39,11 +39,11 @@ /* */ /* INPUT */ /* */ -/* None */ +/* previous_posture Previous interrupt posture */ /* */ /* OUTPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* None */ /* */ /* CALLS */ /* */ @@ -57,20 +57,19 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT new_posture) +// VOID _tx_thread_interrupt_restore(UINT previous_posture) // { PUBLIC _tx_thread_interrupt_restore _tx_thread_interrupt_restore: - /* Restore previous interrupt lockout posture. */ - +#ifdef TX_PORT_USE_BASEPRI + MSR BASEPRI, r0 +#else MSR PRIMASK, r0 +#endif BX lr - // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index 417ac9b5..5623c560 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -87,7 +87,7 @@ _tx_thread_schedule: /* This function should only ever be called on Cortex-M from the first schedule request. Subsequent scheduling occurs - from the PendSV handling routines below. */ + from the PendSV handling routine below. */ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ @@ -95,9 +95,8 @@ _tx_thread_schedule: LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag STR r0, [r2, #0] // Clear preempt disable flag - /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ - #ifdef __ARMVFP__ + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ MRS r0, CONTROL // Pickup current CONTROL register BIC r0, r0, #4 // Clear the FPCA bit MSR CONTROL, r0 // Setup new CONTROL register @@ -110,7 +109,6 @@ _tx_thread_schedule: STR r1, [r0] // /* Enable interrupts */ - CPSIE i /* Enter the scheduler for the first time. */ @@ -204,7 +202,7 @@ UsageFault_Handler: BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts BL _tx_execution_thread_exit // Call the thread exit function @@ -236,7 +234,7 @@ __tx_PendSVHandler: __tx_ts_handler: -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread exit function to indicate the thread is no longer executing. */ CPSID i // Disable interrupts PUSH {r0, lr} // Save LR (and r0 just for alignment) @@ -336,7 +334,7 @@ __tx_ts_restore: STR r5, [r4] // Setup global time-slice -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the thread entry function to indicate the thread is executing. */ PUSH {r0, r1} // Save r0 and r1 BL _tx_execution_thread_enter // Call the thread execution enter function @@ -445,6 +443,7 @@ __tx_SVCallHandler: STR r0, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + MRS r3, PSP // Pickup thread stack pointer TST lr, #0x10 // Test for extended module stack ITT EQ @@ -498,6 +497,27 @@ _tx_thread_user_return: STR r1, [r2, #16] // Set stack end STR r3, [r2, #20] // Set stack size #endif + + /* If lazy stacking is pending, check if it can be cleared. + if(LSPACT && tx_thread_module_stack_start < FPCAR && FPCAR < tx_thread_module_stack_end) + then clear LSPACT. */ + LDR r3, =0xE000EF34 // Address of FPCCR + LDR r3, [r3] // Load FPCCR + TST r3, #1 // Check if LSPACT is set + BEQ _tx_no_lazy_clear // if clear, move on + LDR r1, =0xE000EF38 // Address of FPCAR + LDR r1, [r1] // Load FPCAR + LDR r0, [r2, #0xA4] // Load kernel stack start + CMP r1, r0 // If FPCAR < start, move on + BLO _tx_no_lazy_clear + LDR r0, [r2, #0xA8] // Load kernel stack end + CMP r0, r1 // If end < FPCAR, move on + BLO _tx_no_lazy_clear + BIC r3, #1 // Clear LSPACT + LDR r1, =0xE000EF34 // Address of FPCCR + STR r3, [r1] // Save updated FPCCR +_tx_no_lazy_clear: + LDR r0, [r2, #0xB0] // Load the module thread stack pointer MRS r3, PSP // Pickup kernel stack pointer TST r0, #1 // Is module stack extended? @@ -529,7 +549,7 @@ _tx_skip_kernel_stack_exit: BX lr // Return to thread - /* Kernel entry function from user mode. */ + /* Kernel entry function from user mode. */ EXTERN _txm_module_manager_kernel_dispatch SECTION `.text`:CODE:NOROOT(5) @@ -559,8 +579,8 @@ _txm_module_user_mode_exit: NOP // } - #ifdef __ARMVFP__ + PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable @@ -572,5 +592,4 @@ tx_thread_fpu_disable: BX LR // Return to caller #endif - END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s index f9738ca7..dcc82bf6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_stack_build Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_stack_build Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -59,9 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -69,7 +67,6 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: - /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-M should look like the following after it is built: diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s index fca695be..4c5cb6fb 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s @@ -26,11 +26,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_system_return Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_thread_system_return Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -59,15 +59,12 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { PUBLIC _tx_thread_system_return -_tx_thread_system_return??rA: _tx_thread_system_return: /* Return to real scheduler via PendSV. Note that this routine is often @@ -79,11 +76,17 @@ _tx_thread_system_return: MRS r0, IPSR // Pickup IPSR CMP r0, #0 // Is it a thread returning? BNE _isr_context // If ISR, skip interrupt enable +#ifdef TX_PORT_USE_BASEPRI + MRS r1, BASEPRI // Thread context returning, pickup BASEPRI + MOV r0, #0 + MSR BASEPRI, r0 // Enable interrupts + MSR BASEPRI, r1 // Restore original interrupt posture +#else MRS r1, PRIMASK // Thread context returning, pickup PRIMASK CPSIE i // Enable interrupts MSR PRIMASK, r1 // Restore original interrupt posture +#endif _isr_context: BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s index 9a554857..aa209956 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s @@ -39,11 +39,11 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_timer_interrupt Cortex-M7/IAR */ -/* 6.1.2 */ +/* _tx_timer_interrupt Cortex-Mx/IAR */ +/* 6.1.8 */ /* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ +/* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -73,9 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ +/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ /* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) @@ -113,6 +111,7 @@ _tx_timer_interrupt: // if (__tx_timer_time_slice == 0) CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing /* Set the time-slice expired flag. */ // _tx_timer_expired_time_slice = TX_TRUE; @@ -249,6 +248,5 @@ __tx_timer_nothing_expired: DSB // Complete all memory access BX lr // Return to caller - // } END diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 6bc46d0d..ed5e20e2 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index c61dd2fd..bfd781f4 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index e7fe25de..db902739 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index f25f830a..97fda4f9 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -184,7 +184,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -238,8 +238,8 @@ UINT srd_bit_index; /* */ /* DESCRIPTION */ /* */ -/* This function sets up the MPU register definitions based on the */ -/* module's memory characteristics. */ +/* This function sets up the Cortex-M7 MPU register definitions based */ +/* on the module's memory characteristics. */ /* MPU layout for the Cortex-M7: */ /* Entry Description */ /* 0 Kernel mode entry */ diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 2c25e7fd..85fafbc3 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -59,8 +59,8 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ /* */ /**************************************************************************/ @@ -73,7 +73,7 @@ _txm_module_manager_thread_stack_build: on the Cortex-M should look like the following after it is built: Stack Top: - LR Interrupted LR (LR at time of PENDSV) + lr Interrupted lr (lr at time of PENDSV) r4 Initial value for r4 r5 Initial value for r5 r6 Initial value for r6 diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..96230fa2 --- /dev/null +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,477 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +#define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR +#define ABT_MODE 0x17 // ABT mode +#define SYS_MODE 0x1F // SYS mode + +#define GICI_BASE 0xAE000000 +#define ICCIAR_OFFSET 0x0000000C +#define ICCEOIR_OFFSET 0x00000010 + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + .global _tx_thread_fiq_context_save + .global _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + .global _tx_thread_irq_nesting_start + .global _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + .global _tx_thread_fiq_nesting_start + .global _tx_thread_fiq_nesting_end +#endif + .global _tx_timer_interrupt + .global __main + .global _tx_version_id + .global _tx_build_options + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-R4/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, "function" +_tx_initialize_low_level: + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r0, =Image$$SVC_STACK$$ZI$$Limit + LDR r1, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + STR r0, [r1] // Pickup system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r0, =Image$$DATA$$ZI$$Limit + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + STR r0, [r2, #0] // Save first free memory address + + /* Return to caller. */ + BX lr // Return to caller +/* } */ + + /* Define shells for each of the interrupt vectors. */ + + .global __tx_undefined + .type __tx_undefined, "function" +__tx_undefined: + B __tx_undefined // Undefined handler + +/*** Prefetch and abort handlers are used below for MPU fault handling + .global __tx_prefetch_handler + .type __tx_prefetch_handler, "function" +__tx_prefetch_handler: + B __tx_prefetch_handler // Prefetch exception handler + + .global __tx_abort_handler + .type __tx_abort_handler, "function" +__tx_abort_handler: + B __tx_abort_handler // Abort exception handler +*/ + + .global __tx_reserved_handler + .type __tx_reserved_handler, "function" +__tx_reserved_handler: + B __tx_reserved_handler // Reserved exception handler + + + .global __tx_irq_handler + .type __tx_irq_handler, "function" + .global __tx_irq_processing_return + .type __tx_irq_processing_return, "function" +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Acknowledge the interrupt. */ + LDR r1, =GICI_BASE // Load the base of the GIC + LDR r0, [r1, #ICCIAR_OFFSET] // Read ICCIAR (GIC CPU Interface register) + DSB // Ensure that interrupt acknowledge completes before re-enabling interrupts + PUSH {r0, r1} // Save the IRQ ID and the GIC base address on the stack + + /* Clear the timer interrupt. */ + LDR r0, =0xB0110000 // Load the base address of the timer + MOV r1, #1 // Setup value to write to the interrupt clear register - can be anything. + STR r1, [r0, #0x0C] // Clear the interrupt. 0x0C is the offset to the interrupt clear register. + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + BL _tx_timer_interrupt // Timer interrupt handler +_tx_not_timer_interrupt: + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + POP {r0, r1} // Restore the IRQ ID and GIC base address + STR r0, [r1, #ICCEOIR_OFFSET] // Write the IRQ ID to the End Of Interrupt register to clear the active bit + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + .global __tx_example_vectored_irq_handler + .type __tx_example_vectored_irq_handler, "function" +__tx_example_vectored_irq_handler: + + + /* Save initial context and call context save to prepare for + vectored ISR execution. */ + +/* + STMDB sp!, {r0-r3} // Save some scratch registers + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other scratch registers + BL _tx_thread_vectored_context_save // Vectored context save +*/ + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +/* +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +*/ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +/* +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +*/ + + /* Jump to context restore to restore system context. */ +/* + B _tx_thread_context_restore +*/ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .type __tx_fiq_handler, "function" +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .global __tx_fiq_processing_return + .type __tx_fiq_processing_return, "function" +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + .global __tx_fiq_handler + .type __tx_fiq_handler, "function" +__tx_fiq_handler: + B __tx_fiq_handler // FIQ interrupt handler +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles MPU exceptions and fills the */ +/* _txm_module_manager_memory_fault_info struct. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_memory_fault_handler */ +/* _tx_execution_thread_exit */ +/* _tx_thread_schedule */ +/* */ +/* CALLED BY */ +/* */ +/* MMU exceptions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +/******************************************************************** + MMU Exception Handling +********************************************************************/ + .global _tx_thread_system_state + .global _txm_module_manager_memory_fault_info + .global _tx_thread_current_ptr + .global _txm_module_manager_memory_fault_handler + .global _tx_thread_schedule + + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit + #endif + + + .arm /* Exception handler in ARM mode. */ + .align 3 + .global __tx_prefetch_handler + .global __tx_abort_handler + .type __tx_prefetch_handler, "function" + .type __tx_abort_handler, "function" + +__tx_prefetch_handler: +__tx_abort_handler: + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + // Now pickup and store all the fault related information + + // Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r3, #0] // Save current thread pointer + + MRC p15, 0, r0, c6, c0, 0 // Read DFAR + STR r0, [r3, #8] // Save DFAR + + CMP r0, #0 // Was it a data or instruction fault? + SUBEQ lr, lr, #4 // Adjust point of exception for instruction + SUBNE lr, lr, #8 // Adjust point of exception for data + STR lr, [r3, #4] // Save point of fault + + MRC p15, 0, r0, c5, c0, 0 // Read DFSR + STR r0, [r3, #12] // Save DFSR + MRC p15, 0, r0, c6, c0, 2 // Read IFAR + STR r0, [r3, #16] // Save IFAR + MRC p15, 0, r0, c5, c0, 1 // Read IFSR + STR r0, [r3, #20] // Save IFSR + MOV r0, #0 // Build zero register + MCR p15, 0, r0, c6, c0, 0 // Clear DFAR + MCR p15, 0, r0, c5, c0, 0 // Clear DFSR + MCR p15, 0, r0, c6, c0, 2 // Clear IFAR + MCR p15, 0, r0, c5, c0, 1 // Clear IFSR + + // Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] // Save r0 + STR r1, [r3, #32] // Save r1 + STR r2, [r3, #36] // Save r2 + POP {r0} + STR r0, [r3, #40] // Save r3 + STR r4, [r3, #44] // Save r4 + STR r5, [r3, #48] // Save r5 + STR r6, [r3, #52] // Save r6 + STR r7, [r3, #56] // Save r7 + STR r8, [r3, #60] // Save r8 + STR r9, [r3, #64] // Save r9 + STR r10,[r3, #68] // Save r10 + STR r11,[r3, #72] // Save r11 + STR r12,[r3, #76] // Save r12 + + CPS #SYS_MODE // Enter SYS mode + MOV r0, lr // Pickup lr + MOV r1, sp // Pickup sp + CPS #ABT_MODE // Back to ABT mode + STR r0, [r3, #80] // Save lr + STR r1, [r3, #24] // Save sp + MRS r0, SPSR // Pickup SPSR + STR r0, [r3, #84] // Save SPSR + ORR r0, r0, #SYS_MODE // Return into SYS mode + BIC r0, r0, #THUMB_MASK // Clear THUMB mode + MSR SPSR_c, r0 // Save SPSR + + // Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + BL _tx_execution_thread_exit // Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state // Pickup address of system state + LDR r1, [r0] // Pickup system state + SUB r1, r1, #1 // Decrement + STR r1, [r0] // Store new system state + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from exception + LDR lr, =_tx_thread_schedule // Load scheduler address + SUBS pc, lr, #0 // Return to scheduler +/******************************************************************** + End of MMU exception handling. +********************************************************************/ + + /* Reference build options and version ID to ensure they come in. */ + + LDR r2, =_tx_build_options // Pickup build options variable address + LDR r0, [r2, #0] // Pickup build options content + LDR r2, =_tx_version_id // Pickup version ID variable address + LDR r0, [r2, #0] // Pickup version ID content diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 4b2f6cb7..96230fa2 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -108,7 +108,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) @@ -355,7 +355,7 @@ __tx_fiq_handler: /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_r4/ac6/inc/txm_module_port.h b/ports_module/cortex_r4/ac6/inc/txm_module_port.h index 15f7ec88..4ea78729 100644 --- a/ports_module/cortex_r4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_r4/ac6/inc/txm_module_port.h @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S index 6ee089f2..f7fff787 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S @@ -80,7 +80,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top) */ diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c index 3415c85c..477f054d 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -93,7 +93,7 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S index d739d0e1..8f46cfaf 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S @@ -94,7 +94,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S index bd37aff2..f9799509 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S @@ -87,7 +87,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S index f3d4ac6c..7faf069c 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S @@ -83,7 +83,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 0b412241..77aa1a7c 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -132,7 +132,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index d58987c8..a7313179 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 29eab3c3..886de011 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 35ef0416..2404e2fd 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 0ac981b1..da5cdeb5 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -186,7 +186,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -280,7 +280,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 08d09003..f07b3111 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S index 88145fa2..7ca8a4fd 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ .text diff --git a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s index 2e9c4519..3371743c 100644 --- a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s @@ -107,7 +107,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -288,7 +288,7 @@ __tx_fiq_handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ diff --git a/ports_module/cortex_r4/iar/inc/txm_module_port.h b/ports_module/cortex_r4/iar/inc/txm_module_port.h index ecc2b290..cf504a45 100644 --- a/ports_module/cortex_r4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_r4/iar/inc/txm_module_port.h @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c index be6d16fd..299139a5 100644 --- a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -91,7 +91,7 @@ extern VOID __iar_data_init3(VOID); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s index 4c267979..69e9c979 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s @@ -76,7 +76,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s index ebd24a4e..cdb924e5 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s @@ -75,7 +75,7 @@ MODE_MASK EQU 0x1F ; Mode mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s index 8795214a..cdcc4305 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s @@ -62,7 +62,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 2500314b..68a6b244 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index c59fc069..31847373 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 4bc7c3aa..97cc393f 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -76,7 +76,7 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index c8244c2b..1ad3cf92 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -71,7 +71,7 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index cc59721d..b05180da 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -183,7 +183,7 @@ ULONG return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -276,7 +276,7 @@ UINT srd_bit_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 78b016c5..dd519475 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -64,7 +64,7 @@ CPSR_MASK DEFINE 0xBF ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s index a14ef099..52aefe0d 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -61,7 +61,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ PUBLIC _txm_module_manager_user_mode_entry |