diff options
Diffstat (limited to 'ports_module')
1062 files changed, 16509 insertions, 21515 deletions
diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject index a49dadd2..8a32c271 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject @@ -1,174 +1,174 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6"> - + <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.689426261" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/> - + <option id="com.arm.toolchain.v6.base.options.debug.level.1729514272" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.1388095870.857809581" name=""/> - + <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1944684744" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/> - + <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.259341383" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.option.cpu.96377009" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a35" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.defmac.1975445896" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols"> - + <listOptionValue builtIn="false" value="STANDALONE"/> - + </option> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1271571516" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/> - + </option> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1548640167" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.815952161" superClass="com.arm.tool.c.compiler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1091536604" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1962633763" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + </tool> - + <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1147447905" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.assembler.v6.base.option.cpu.269795998" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-a35" valueType="string"/> - + <option id="com.arm.tool.assembler.v6.base.options.debug.level.1521551718" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.defmac.281085002" name="Define macro (-D)" superClass="com.arm.tool.assembler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols"/> - + <inputType id="com.arm.tool.assembler.v6.base.input.1000911913" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1807144931" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"> - 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+ <option id="com.arm.tool.c.linker.option.totals.428431324" name="List total code and data sizes of output image (--info=totals)" superClass="com.arm.tool.c.linker.option.totals" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.redirectoutput.259431691" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx.map" valueType="string"/> - + <option id="com.arm.tool.c.linker.option.elim.532237314" name="List unused sections that are eliminated (--info=unused)" superClass="com.arm.tool.c.linker.option.elim" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.compress.1449950796" name="Print RW compression information (--info=compression)" superClass="com.arm.tool.c.linker.option.compress" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.stack.1835435506" name="List stack usage of global symbols (--info=stack)" superClass="com.arm.tool.c.linker.option.stack" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.inlineinfo.1898593362" name="List functions inlined by linker (--info=inline)" superClass="com.arm.tool.c.linker.option.inlineinfo" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.callgraph.1505673040" name="Generate call graph (--callgraph)" superClass="com.arm.tool.c.linker.option.callgraph" useByScannerDiscovery="false" value="true" valueType="boolean"/> - + <option id="com.arm.tool.c.linker.option.graphfile.1311318964" name="Callgraph file (--callgraph_file)" superClass="com.arm.tool.c.linker.option.graphfile" useByScannerDiscovery="false" value="callgraph" valueType="string"/> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1243987688" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h index 8e6f0acc..beaa9157 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c index 3bfb4a93..2cf1553b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c index 7b437b18..912ab2e4 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c index 8898ff39..736722fb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -87,42 +87,42 @@ UCHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ UCHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -250,11 +250,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -313,7 +313,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -366,7 +366,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S index de100e56..9f0fc211 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 857c2101..135cd934 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject index e75d0d0e..695952e7 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject @@ -1,220 +1,220 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 3a3f8159..3476367e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -148,7 +148,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -156,11 +156,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -169,7 +169,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -177,10 +177,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -189,7 +189,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -200,7 +200,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -210,7 +210,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -219,7 +219,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f05656c3..ad75e134 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .section Init - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject index 77c12df2..2f54811f 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,238 +1,238 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1927525577" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258"> - + <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1304794003" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.1502156310" superClass="com.arm.tool.c.compiler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1573521907" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072"> - + <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1807654698" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/> - + </tool> - + <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1808081220" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179"> - + <inputType id="com.arm.tool.assembler.v6.base.input.579682311" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.641966454" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108"/> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.616745103" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h index 8e6f0acc..beaa9157 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c index 3bfb4a93..2cf1553b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c index 7b437b18..912ab2e4 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index deb16ebe..54e58dba 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S index de100e56..9f0fc211 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index ebbc5ce3..47bd46e8 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/AC6 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/AC6 */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/tx/.cproject b/ports_module/cortex_a35/ac6/example_build/tx/.cproject index 51f626a6..be84e260 100644 --- a/ports_module/cortex_a35/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/tx/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915"> - 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+ <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6"> - + <option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.319260876" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-A35.AArch64.ARMv8.Neon.Crypto" valueType="string"/> - + <option id="com.arm.toolchain.v6.base.options.debug.level.287044124" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.174366982.1434986226" name=""/> - + <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.2017005160" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/> - 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+ </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.302832878" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1893346540" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="src_generic/tx_misra.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1209080418" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + </cproject> diff --git a/ports_module/cortex_a35/ac6/example_build/txm/.cproject b/ports_module/cortex_a35/ac6/example_build/txm/.cproject index dddf4382..b1d86a47 100644 --- a/ports_module/cortex_a35/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/txm/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6"> - 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+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_port}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_modules}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_module_manager}""/> - + </option> - + <option id="com.arm.tool.c.compiler.v6.base.options.debug.level.536480260" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.compiler.v6.base.option.flags.292072134" name="Other flags" superClass="com.arm.tool.c.compiler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.1961882835" superClass="com.arm.tool.c.compiler.v6.base.input"/> - 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+ <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.assembler.v6.base.option.flags.1542396439" name="Other flags" superClass="com.arm.tool.assembler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList"/> - + <inputType id="com.arm.tool.assembler.v6.base.input.1847017761" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index 92dc14f3..657ad451 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -59,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -119,19 +114,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +184,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,7 +198,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -243,11 +238,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -255,8 +250,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -283,8 +278,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -312,9 +307,9 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -385,8 +380,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/ac6/inc/txm_module_port.h b/ports_module/cortex_a35/ac6/inc/txm_module_port.h index 44009c55..cbe6b8e3 100644 --- a/ports_module/cortex_a35/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -278,6 +273,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S index c98ad715..2a04ce86 100644 --- a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c index e24e27be..adf4163f 100644 --- a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -122,7 +117,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S index 655674de..93c46c88 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { @@ -86,13 +81,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, #0] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, #0] // Store the counter + STR w2, [x3, #0] // Store the counter CMP w2, #0 // Was this the first interrupt? BEQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S index ce4fec26..b2d8af34 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -137,7 +132,7 @@ __tx_thread_not_nested_save: LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x1, #0] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -196,7 +191,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -209,8 +204,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c index b045bdab..aa96ffb0 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c index 80ef1e7e..2cf3ba17 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S index 0bb03ed4..60cf4982 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S index f5ee54a2..72742e7a 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S index 5ed509d8..42643576 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S index 1193fdca..f86f4212 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -76,15 +71,15 @@ _tx_thread_schedule: // Wait for a thread to execute. */ // do // { - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr #ifdef TX_ENABLE_WFI __tx_thread_schedule_loop: LDR x0, [x1, #0] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - BNE _tx_thread_schedule_thread // - WFI // + BNE _tx_thread_schedule_thread // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: #else @@ -96,7 +91,7 @@ __tx_thread_schedule_loop: // } // while(_tx_thread_execute_ptr == TX_NULL); - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ @@ -105,7 +100,7 @@ __tx_thread_schedule_loop: /* Setup the current thread pointer. */ // _tx_thread_current_ptr = _tx_thread_execute_ptr; - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, #0] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -119,7 +114,7 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S index 37c22e90..bacd87eb 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S index 4c5af0dc..e4cebb03 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S index 895b5a7d..bad45ccd 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -86,7 +81,7 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice LDR w2, [x3, #0] // Pickup time-slice CMP w2, #0 // Is it non-active? BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing @@ -203,7 +198,7 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR w2, [x3, #0] // Pickup the actual flag CMP w2, #0 // See if the flag is set BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 2a399a17..5cd9edd6 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index de09130c..8ecb5044 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35/ac6/readme_threadx.txt b/ports_module/cortex_a35/ac6/readme_threadx.txt index e8c6ce96..3c522c31 100644 --- a/ports_module/cortex_a35/ac6/readme_threadx.txt +++ b/ports_module/cortex_a35/ac6/readme_threadx.txt @@ -1,20 +1,20 @@ - Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 + Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Modules Projects -In order to build the ThreadX library and the ThreadX demonstration, first import +In order to build the ThreadX library and the ThreadX demonstration, first import the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and -'sample_thread_module_manager' projects (located in the "example_build" directory) +'sample_thread_module_manager' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. To bild the ThreadX Module library select the project "txm" and select the build button to produce the file txm.a. @@ -36,8 +36,8 @@ First build the ThreadX sample module project sample_thread_module by selecting clicking the build button. Next built the ThreadX Module Manager sample by selecting sample_threadx_module_manager and clicking the build button. -To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, -right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. +To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, +right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute the ThreadX demonstration. @@ -45,29 +45,29 @@ the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label -"start64". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -108,7 +108,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -194,14 +194,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -221,22 +221,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject index 7eb75c64..0bcc75f1 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject @@ -1,252 +1,252 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release" parent="com.arm.eclipse.build.config.v6.exe.release.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.exe.release.base.262471578." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6"> - + <targetPlatform id="com.arm.toolchain.v6.exe.release.base.var.arm_compiler_6-6.2039978271.1401365679" name=""/> - + <builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.152908166" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/> - + <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2113724202" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1064912621" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - + <inputType id="com.arm.tool.c.compiler.v6.base.input.274442412" superClass="com.arm.tool.c.compiler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.857388488" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.option.optlevel.703057645" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/> - + </tool> - + <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.494258017" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6"> - + <inputType id="com.arm.tool.assembler.v6.base.input.2016749997" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1332640632" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1069857726" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + </cproject> diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c index b0d22c40..61addaef 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c index 8898ff39..736722fb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -87,42 +87,42 @@ UCHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ UCHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -250,11 +250,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -313,7 +313,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -366,7 +366,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S index 67dd8a6a..b44806fe 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S index f4e6ea0a..55ec0f9f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject index 296685a7..50726e80 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s index 7c454996..e0569f71 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s @@ -17,7 +17,7 @@ _gcc_setup: ldr x9, =__RAM_segment_start__ /* Copy GOT table. */ - + ldr x0, =__got_load_start__ sub x0 ,x0, x3 add x0, x0, x5 @@ -51,7 +51,7 @@ got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr x0, =__data_load_start__ sub x0, x0, x3 add x0, x0, x5 @@ -62,9 +62,9 @@ got_setup_done: sub x2, x2, x4 add x2, x2, x9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr x0, =__bss_start__ sub x0, x0, x4 add x0, x0, x9 @@ -88,12 +88,12 @@ got_setup_done: str x2, [x0] add x0, x0, #4 str x1, [x0] - + ldr x30, [sp] // Restore other preserved registers add sp, sp, 16 ret // Return to caller - + /* Startup helper functions. */ @@ -126,4 +126,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c index 3a3f8159..3476367e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -148,7 +148,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -156,11 +156,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -169,7 +169,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -177,10 +177,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -189,7 +189,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -200,7 +200,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -210,7 +210,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -219,7 +219,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 042b59bf..d117a5df 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -110,7 +110,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -120,7 +120,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S index cce29ef8..bb0acb6f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,6 +1,6 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject index 79e120b4..b1950eb6 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,264 +1,264 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.exe.debug.base.515451048;com.arm.eclipse.build.config.v6.exe.debug.base.515451048.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include <stdint.h> diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c index b0d22c40..61addaef 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld index eec8f12b..3bf47736 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S index 67dd8a6a..b44806fe 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index f4e6ea0a..55ec0f9f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/tx/.cproject b/ports_module/cortex_a35/gnu/example_build/tx/.cproject index e3b8bf79..ce420cbc 100644 --- a/ports_module/cortex_a35/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/tx/.cproject @@ -1,258 +1,258 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - 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+ <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551;com.arm.eclipse.build.config.v6.lib.debug.base.1507005551.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index 55007b04..edf3ad66 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -59,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -119,19 +114,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +184,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,7 +198,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -243,11 +238,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -255,8 +250,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -283,8 +278,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -312,9 +307,9 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -385,8 +380,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/gnu/inc/txm_module_port.h b/ports_module/cortex_a35/gnu/inc/txm_module_port.h index 847f35c5..e5654cde 100644 --- a/ports_module/cortex_a35/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -278,6 +273,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c index 8ac207f0..922b9306 100644 --- a/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -122,7 +117,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S index 34b0db92..d1ef83ca 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { @@ -87,13 +82,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, #0] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, #0] // Store the counter + STR w2, [x3, #0] // Store the counter CMP w2, #0 // Was this the first interrupt? BEQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S index 349f04f3..c8b3312f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -137,7 +132,7 @@ __tx_thread_not_nested_save: LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x1, #0] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -196,7 +191,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -209,8 +204,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c index 1bf9d364..d586d241 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c index 76516b23..ead0c528 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S index f271084c..fe702a39 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S index 6c781d55..0add0b6f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S index 0ab1b0e3..74cc9266 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S index f39d341b..a94a70ef 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -76,15 +71,15 @@ _tx_thread_schedule: // Wait for a thread to execute. */ // do // { - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr #ifdef TX_ENABLE_WFI __tx_thread_schedule_loop: LDR x0, [x1, #0] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - BNE _tx_thread_schedule_thread // - WFI // + BNE _tx_thread_schedule_thread // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: #else @@ -96,7 +91,7 @@ __tx_thread_schedule_loop: // } // while(_tx_thread_execute_ptr == TX_NULL); - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ @@ -105,7 +100,7 @@ __tx_thread_schedule_loop: /* Setup the current thread pointer. */ // _tx_thread_current_ptr = _tx_thread_execute_ptr; - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, #0] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -119,7 +114,7 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S index d5febaad..2c1c8f5f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S index bd00e697..7e43ba48 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S index a0007548..a1eb57bd 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -86,7 +81,7 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice LDR w2, [x3, #0] // Pickup time-slice CMP w2, #0 // Is it non-active? BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing @@ -203,7 +198,7 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR w2, [x3, #0] // Pickup the actual flag CMP w2, #0 // See if the flag is set BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c index cc3296cf..903b30f7 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 983bd2a7..a9a50ec9 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35/gnu/readme_threadx.txt b/ports_module/cortex_a35/gnu/readme_threadx.txt index 13c2c9c0..c318db76 100644 --- a/ports_module/cortex_a35/gnu/readme_threadx.txt +++ b/ports_module/cortex_a35/gnu/readme_threadx.txt @@ -1,20 +1,20 @@ - Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 + Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 Using the ARM GNU Compiler & DS 1. Import the ThreadX Modules Projects -In order to build the ThreadX library and the ThreadX demonstration, first import +In order to build the ThreadX library and the ThreadX demonstration, first import the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and -'sample_thread_module_manager' projects (located in the "example_build" directory) +'sample_thread_module_manager' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. To bild the ThreadX Module library select the project "txm" and select the build button to produce the file txm.a. @@ -36,8 +36,8 @@ First build the ThreadX sample module project sample_thread_module by selecting clicking the build button. Next built the ThreadX Module Manager sample by selecting sample_threadx_module_manager and clicking the build button. -To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, -right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. +To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, +right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute the ThreadX demonstration. @@ -45,29 +45,29 @@ the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -108,7 +108,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -194,14 +194,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -221,22 +221,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject index 40b668c4..58ba80a5 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.4.1908576142" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject index c27fce90..e7a98e77 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject @@ -1,246 +1,246 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </tool> - + <tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.1573521907" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072"> - + <option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1807654698" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" valueType="enumerated"/> - + </tool> - + <tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1808081220" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179"> - + <inputType id="com.arm.tool.assembler.v6.base.input.579682311" superClass="com.arm.tool.assembler.v6.base.input"/> - + </tool> - + <tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.641966454" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108"/> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.616745103" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="startup_el3.S|startup_el2.S|startup_el1.S|startup_old.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx_module_manager.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat index 1288a328..1ed382ae 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject index b5457c00..d1e7ba11 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject @@ -1,242 +1,242 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject index 870444d0..d0d395d6 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject @@ -1,238 +1,238 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h index c26962fb..52693754 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -83,12 +75,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -129,7 +121,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -190,19 +182,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -260,7 +252,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -274,7 +266,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -314,11 +306,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -326,8 +318,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -354,8 +346,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -367,7 +359,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -397,14 +389,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT ULONG tx_thread_smp_protect_count; ULONG tx_thread_smp_protect_pad_0; ULONG tx_thread_smp_protect_pad_1; - ULONG tx_thread_smp_protect_pad_2; - ULONG tx_thread_smp_protect_pad_3; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -442,8 +434,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h index 6045dcc4..97930b4f 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -273,6 +268,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S index c98ad715..2a04ce86 100644 --- a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c index 54b8824f..4559ac0e 100644 --- a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S index 5968a993..4a9a6402 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S index a590c2ae..6eec8596 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S index 51aad705..1372dcb4 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -149,7 +144,7 @@ __tx_thread_not_nested_save: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -217,7 +212,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -230,8 +225,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c index cb234851..61a93ab7 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c index c91b579c..2eb5324a 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S index a60146cc..267c1b20 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S index 2c7d86d2..e6e5f545 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S index 44457d25..9d46f67d 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S index 42bede20..f1739339 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S index 600ecf28..a2e2bd3a 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S index 777a9981..898a8345 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S index 994fe41b..5dad61bd 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S index 8965f745..0664dde6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S index 4be71ceb..90bbe372 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function @@ -80,7 +75,7 @@ _tx_thread_smp_initialize_wait: ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif - /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release flag. */ LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag @@ -91,7 +86,7 @@ wait_for_initialize: BNE wait_for_initialize // Not equal, just spin here /* Save the system stack pointer for this core. */ - + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP SUB x1, x1, #15 // @@ -100,30 +95,30 @@ wait_for_initialize: /* Pickup the release cores flag. */ - + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag -wait_for_release: +wait_for_release: LDR w0, [x4, #0] // Pickup the flag CMP w0, #0 // Is it set? BEQ wait_for_release // Wait for the flag to be set - + /* Core 0 has released this core. */ - + /* Clear this core's system state variable. */ - + MOV x0, #0 // Build clear value STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero - + /* Now wait for core 0 to finish it's initialization. */ - + core_0_wait_loop: LDR w0, [x3, #0] // Pickup the current system state for core 0 CMP w0, #0 // Is it 0? BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization - + /* Initialization is complete, enter the scheduling loop! */ - - B _tx_thread_schedule // Enter the scheduling loop for this core + + B _tx_thread_schedule // Enter the scheduling loop for this core RET diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S index dba9a06e..f3e95723 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S index af49d3a0..4a48c56c 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S index aa24a4e4..002bf59d 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S index a0bbf64e..4b5bd9a2 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S index 5270aba3..880436ad 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S index db9a145a..cad938c9 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { @@ -156,13 +151,13 @@ __tx_thread_dont_save_ts: STR x4, [x5, x8, LSL #3] // Clear current thread pointer /* Set ready bit in thread control block. */ - + MOV x3, #1 // Build ready value - STR w3, [x6, #260] // Make the thread ready - DMB ISH // - + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ - + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag STR w4, [x1, #0] // Clear preempt disable flag diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S index cc5e12de..1319ea07 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -175,8 +170,8 @@ __tx_timer_dont_activate: BL _tx_thread_time_slice // Call time-slice processing /* Release inter-core protection. */ - - MOV x0, x28 // Pass the previous status register back + + MOV x0, x28 // Pass the previous status register back BL _tx_thread_smp_unprotect // Release protection LDP x29, x30, [sp], #16 // Recover x29, x30 diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c index dd472506..5cd9edd6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index fc474b6e..5ff9a1e6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35_smp/ac6/readme_threadx.txt b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt index 044d2235..aadf9da2 100644 --- a/ports_module/cortex_a35_smp/ac6/readme_threadx.txt +++ b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 + Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label -"start64". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -182,14 +182,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject index 9ff6439f..8a8670cc 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject @@ -1,246 +1,246 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269"> - 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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject index 296685a7..50726e80 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ <additionalInput kind="additionalinput" paths="$(LIBS)"/> - + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> - + </inputType> - + </tool> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.413208540" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.2066918847" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 042b59bf..d117a5df 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -110,7 +110,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -120,7 +120,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S index e41ac007..bb0acb6f 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,4 +1,4 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 // External references diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject index 572198b3..4d2057f9 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,268 +1,268 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.exe.debug.base.515451048;com.arm.eclipse.build.config.v6.exe.debug.base.515451048.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1331565505;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.301538030"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld index e9b12a82..1c6d45b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject index a38608a6..765c3509 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject @@ -1,288 +1,288 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - 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+ <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - 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+ <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551;com.arm.eclipse.build.config.v6.lib.debug.base.1507005551.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.948279352;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.846815502"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index 578fd6f5..bc694706 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -83,12 +75,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -129,7 +121,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -190,19 +182,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -260,7 +252,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -274,7 +266,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -314,11 +306,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -326,8 +318,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -354,8 +346,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -367,7 +359,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -397,14 +389,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT ULONG tx_thread_smp_protect_count; ULONG tx_thread_smp_protect_pad_0; ULONG tx_thread_smp_protect_pad_1; - ULONG tx_thread_smp_protect_pad_2; - ULONG tx_thread_smp_protect_pad_3; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -442,8 +434,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h index 5eeab1c5..99e7d056 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -273,6 +268,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c index 914d4292..ba56d9e3 100644 --- a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S index 68565f3f..be81c11d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S index 7ab0f5dc..b2b9240f 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S index a7c8a37d..ffb6e1d5 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -149,7 +144,7 @@ __tx_thread_not_nested_save: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -217,7 +212,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -230,8 +225,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c index 6ca98daf..c77c270d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c index e21e5478..803ed053 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S index 273e6c22..995f66c8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S index 73cc0a09..f0c10827 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S index 3d09ad89..39616622 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S index 84f4413e..7b8f660f 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S index 0879bea8..936d3e86 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S index 62888b74..2e78a55d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S index 25cf7a37..d741f8dc 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S index 63921407..7c6c1be9 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S index 2b518481..ef63c852 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function @@ -80,7 +75,7 @@ _tx_thread_smp_initialize_wait: ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif - /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release flag. */ LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag @@ -91,7 +86,7 @@ wait_for_initialize: BNE wait_for_initialize // Not equal, just spin here /* Save the system stack pointer for this core. */ - + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP SUB x1, x1, #15 // @@ -100,30 +95,30 @@ wait_for_initialize: /* Pickup the release cores flag. */ - + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag -wait_for_release: +wait_for_release: LDR w0, [x4, #0] // Pickup the flag CMP w0, #0 // Is it set? BEQ wait_for_release // Wait for the flag to be set - + /* Core 0 has released this core. */ - + /* Clear this core's system state variable. */ - + MOV x0, #0 // Build clear value STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero - + /* Now wait for core 0 to finish it's initialization. */ - + core_0_wait_loop: LDR w0, [x3, #0] // Pickup the current system state for core 0 CMP w0, #0 // Is it 0? BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization - + /* Initialization is complete, enter the scheduling loop! */ - - B _tx_thread_schedule // Enter the scheduling loop for this core + + B _tx_thread_schedule // Enter the scheduling loop for this core RET diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S index 8548b723..9a537e87 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S index b9a694a9..ebac9e58 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S index fdfbfa83..8fbc98f4 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S index 1ef48e74..3125dab8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S index efb65fa6..0f687fee 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S index 9e184023..a5e5f985 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { @@ -156,13 +151,13 @@ __tx_thread_dont_save_ts: STR x4, [x5, x8, LSL #3] // Clear current thread pointer /* Set ready bit in thread control block. */ - + MOV x3, #1 // Build ready value - STR w3, [x6, #260] // Make the thread ready - DMB ISH // - + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ - + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag STR w4, [x1, #0] // Clear preempt disable flag diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S index d774f388..ba8e8c59 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -175,8 +170,8 @@ __tx_timer_dont_activate: BL _tx_thread_time_slice // Call time-slice processing /* Release inter-core protection. */ - - MOV x0, x28 // Pass the previous status register back + + MOV x0, x28 // Pass the previous status register back BL _tx_thread_smp_unprotect // Release protection LDP x29, x30, [sp], #16 // Recover x29, x30 diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c index 2a399a17..5cd9edd6 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 835fef69..43d718e8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35_smp/gnu/readme_threadx.txt b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt index de17c068..dca3b84c 100644 --- a/ports_module/cortex_a35_smp/gnu/readme_threadx.txt +++ b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -182,14 +182,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c index fce2a3fa..f9ed56eb 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,25 +129,25 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ @@ -156,14 +156,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,7 +172,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -180,14 +180,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ UINT status; *(ULONG *) 0x90000000 = 0xdeadbeef; *(ULONG *) 0x90000FFC = 0xfeed0add; *(ULONG *) 0x90001000 = 0xfedcba01; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -300,11 +300,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -363,7 +363,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -416,7 +416,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c index 8b17e34a..ac3bbeb5 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -45,7 +45,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -57,8 +57,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - first_unused_memory, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -71,46 +71,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -118,7 +118,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/ac5/example_build/scatter.scat b/ports_module/cortex_a7/ac5/example_build/scatter.scat index a9e2d1d8..d30f6109 100644 --- a/ports_module/cortex_a7/ac5/example_build/scatter.scat +++ b/ports_module/cortex_a7/ac5/example_build/scatter.scat @@ -6,7 +6,7 @@ ; Using a scatter-file with ARM_LIB_STACKHEAP eliminates the need to set stack-limit or heap-base in the debugger. -SDRAM 0x80000000 +SDRAM 0x80000000 { VECTORS +0 { diff --git a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s index d9150dff..9bdd7ba4 100644 --- a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -109,45 +109,39 @@ Reset_Vector ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -335,7 +329,7 @@ GIC1_DIST_INTERFACE_BASE EQU 0x2C001000 ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -375,7 +369,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -383,15 +377,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler - + ; clear timer interrupt ldr r0, =0x1C110000 eor r1, r1, r1 @@ -399,11 +393,11 @@ __tx_irq_processing_return _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -413,7 +407,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -429,28 +423,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -459,7 +453,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -481,11 +475,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start @@ -509,43 +503,43 @@ __tx_fiq_handler B __tx_fiq_handler ; FIQ interrupt handler ENDIF - - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */ + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MMU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -561,7 +555,7 @@ __tx_fiq_handler EXTERN _txm_module_manager_memory_fault_handler EXTERN _tx_execution_thread_exit EXTERN _tx_thread_schedule - + EXPORT __tx_prefetch_handler EXPORT __tx_abort_handler __tx_prefetch_handler @@ -589,7 +583,7 @@ __tx_abort_handler STR r0, [r3, #16] ; Save IFAR MRC p15, 0, r0, c5, c0, 1 ; Read IFSR STR r0, [r3, #20] ; Save IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -606,7 +600,7 @@ __tx_abort_handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -618,7 +612,7 @@ __tx_abort_handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -633,11 +627,11 @@ __tx_abort_handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s index 168dad31..953a1d62 100644 --- a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s @@ -34,7 +34,7 @@ __txm_module_preamble ; 1 -> User mode execution (MMU protection) DCD _txm_module_thread_shell_entry - . + . ; Module Shell Entry Point DCD demo_module_start - . + . ; Module Start Thread Entry Point - DCD 0 ; Module Stop Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point DCD 1 ; Module Start/Stop Thread Priority DCD 2046 ; Module Start/Stop Thread Stack Size DCD _txm_module_callback_request_thread_entry - . + . ; Module Callback Thread Entry diff --git a/ports_module/cortex_a7/ac5/inc/tx_port.h b/ports_module/cortex_a7/ac5/inc/tx_port.h index 1d507b66..fd061c95 100644 --- a/ports_module/cortex_a7/ac5/inc/tx_port.h +++ b/ports_module/cortex_a7/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include <string.h> -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,11 +178,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -204,7 +196,7 @@ typedef unsigned short USHORT; VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -224,11 +216,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -236,8 +228,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -264,21 +256,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -298,7 +290,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -307,7 +299,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -343,8 +335,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/ac5/inc/txm_module_port.h b/ports_module/cortex_a7/ac5/inc/txm_module_port.h index 2f930ec9..1102a377 100644 --- a/ports_module/cortex_a7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_a7/ac5/inc/txm_module_port.h @@ -1,52 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -86,10 +81,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -296,7 +291,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -406,7 +401,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s index cb838377..1aff12b8 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -31,43 +31,37 @@ ; ; IMPORT __scatterload - + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_initialize Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function initializes the module c runtime. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* __scatterload Initialize C runtime */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _txm_module_thread_shell_entry Start module thread */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_initialize(VOID) @@ -75,16 +69,16 @@ EXPORT _txm_module_initialize _txm_module_initialize PUSH {r4-r12,lr} ; Save dregs and LR - + B __scatterload ; Call ARM func to initialize variables ;/* Override __rt_exit function. */ EXPORT __rt_exit __rt_exit - + POP {r4-r12,lr} ; Restore dregs and LR BX lr ; Return to caller ;} - + END diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c index f04a1808..4925fe47 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ VOID __user_setup_stackheap(VOID){return;} /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s index 92a2311a..515f2820 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -56,44 +56,38 @@ DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -123,13 +117,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -189,10 +183,10 @@ __tx_thread_preempt_restore LDMIA sp!, {r0-r3} ; Recover r0-r3 CPS #SYS_MODE ; Enter SYS mode STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack - + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + IF {TARGET_FPU_VFP} = {TRUE} LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -203,7 +197,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save ENDIF - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s index 3993d9f0..7c7be45c 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s index 44233091..0258ead2 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -208,7 +202,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -220,7 +214,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s index eb969c1d..7be8a46f 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s index 9062160c..8b2fc70b 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s index a1456bd1..a94ff890 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s index 0d422e49..c9d95a58 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s index 5653faf4..de174cb1 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s index e9f15cc6..c2c32842 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s index f458cb21..73a88636 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s index 2f1814f8..d4c1ca06 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s index be7a2ca7..994c6964 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -36,7 +36,7 @@ IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter ENDIF - + IRQ_MODE EQU 0xD2 ; IRQ mode USR_MODE EQU 0x10 ; USR mode SVC_MODE EQU 0x13 ; SVC mode @@ -48,7 +48,7 @@ ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask IMPORT _txm_system_mode_enter @@ -58,52 +58,46 @@ THUMB_MASK EQU 0x20 ; Thumb bit mask ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ EXPORT _tx_thread_schedule _tx_thread_schedule - + ; Enter the scheduler. SVC 0 @@ -138,7 +132,7 @@ __tx_swi_interrupt ; ; The service call is handled here ; - + CMP r0, #0 ; Is it a schedule request? BEQ _tx_handler_svc_schedule ; Yes, go there @@ -147,7 +141,7 @@ __tx_swi_interrupt CMP r0, #2 ; Is it a system mode exit request? BEQ _tx_handler_svc_super_exit ; Yes, go there - + LDR r2, =0x123456 CMP r0, r2 ; Is it an ARM request? BEQ _tx_handler_svc_arm ; Yes, go there @@ -161,14 +155,14 @@ _tx_handler_svc_unrecognized _tx_handler_svc_unrecognized_loop ; We should never get here B _tx_handler_svc_unrecognized_loop - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; At this point we have an SVC 1, which means we are entering the system mode to service a kernel call _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) - LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -178,7 +172,7 @@ _tx_handler_svc_super_enter LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) STR r1, [r2, #0x9C] ; Clear tx_thread_module_current_user_mode for thread - + ; Now we enter the system mode and return LDMFD sp!, {r0, r3} ; Get spsr from the stack BIC r0, r0, #MODE_MASK ; clear mode field @@ -198,16 +192,16 @@ _tx_handler_svc_super_enter LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end STRD r0, r1, [r2, #0x0C] ; Set stack start and end ENDIF - + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; At this point we have an SVC 2, which means we are exiting the system mode after servicing a kernel call _tx_handler_svc_super_exit ; Make sure that we have been called from the system mode exit location (security) - LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -237,19 +231,19 @@ _tx_handler_svc_super_exit STRD r0, r1, [r2, #0x0C] ; Set stack start and end ENDIF LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; just return LDMFD sp!, {r0, r3} ; Get spsr from the stack MSR SPSR_cxsf, r0 ; Restore the spsr LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -258,10 +252,10 @@ _tx_handler_svc_schedule LDMFD sp!, {r0, r3} ; Get spsr from stack MSR SPSR_cxsf, r0 ; Restore spsr - LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -317,7 +311,7 @@ __tx_thread_schedule_loop ; Determine if an interrupt frame or a synchronous task suspension frame is present. CPS #SYS_MODE ; Enter SYS mode - LDR sp, [r0, #8] ; Switch to thread stack pointer + LDR sp, [r0, #8] ; Switch to thread stack pointer LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR CPS #SVC_MODE ; Enter SVC mode @@ -347,7 +341,7 @@ __tx_thread_schedule_loop MOV r3, #14 ADD r1, r1, r2, LSL r3 MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value - + ; refresh TLB MOV r2, #0 DSB @@ -356,21 +350,21 @@ __tx_thread_schedule_loop MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor DSB ISB - + ;test address translation ;mcr p15, 0, r0, c7, c8, 0 - + _tx_skip_mmu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return - + MSR SPSR_cxsf, r5 ; Setup SPSR for return LDR r1, [r0, #8] ; Get thread SP LDR lr, [r1, #0x40] ; Get thread PC CPS #SYS_MODE ; Enter SYS mode - + IF {TARGET_FPU_VFP} = {TRUE} LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -384,7 +378,7 @@ _tx_skip_mmu_update CPS #SYS_MODE ; Enter SYS mode _tx_skip_interrupt_vfp_restore ENDIF - + LDMIA sp!, {r0-r12, lr} ; Restore registers ADD sp, sp, #4 ; Fix stack pointer CPS #SVC_MODE ; Enter SVC mode @@ -393,7 +387,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + IF {TARGET_FPU_VFP} = {TRUE} LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -404,12 +398,12 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore ENDIF - + LDMIA sp!, {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode MSR SPSR_cxsf, r2 ; Recover CPSR - MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr + MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr SUBS pc, lr, #0 ; Return to thread synchronously ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s index 03e24ca7..b85d1b77 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -42,44 +42,38 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -87,10 +81,10 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s index 01e93435..cfaf4f84 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s index 1e9a2f82..d52a9776 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s index ce94e6e0..0a2a68f6 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 3f32067d..dda03dfc 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,45 +26,39 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* Initial thread stack frame */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index f19534dd..4aa1b941 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index f5a8b293..00bb9075 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 1cd9f082..cd0535ae 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c index be7288d1..aa8244cf 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -51,48 +52,42 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; __align(16384) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ __align(1024) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ __align(1024) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -103,53 +98,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -167,98 +162,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; __asm("mcr p15, 0, cp15reg, c13, c0, 1"); __asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; __asm("mcr p15, 0, cp15reg, c2, c0, 0"); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; __asm("mcr p15, 0, cp15reg, c3, c0, 0"); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -268,7 +263,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -277,21 +272,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ __asm("mrc p15, 0, cp15reg, c1, c0, 0"); cp15reg |= 0x1; __asm("mcr p15, 0, cp15reg, c1, c0, 0"); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 4c5d7a09..bdaa548d 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 675b1db6..5ae43a7e 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -40,44 +40,38 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -88,7 +82,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 58da85b9..758c4125 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,60 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; IMPORT _tx_thread_current_ptr IMPORT _txm_module_manager_kernel_dispatch - - + + AREA ||.text||, CODE, READONLY, ALIGN=12 PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ EXPORT _txm_module_manager_user_mode_entry @@ -83,9 +77,9 @@ _txm_system_mode_exit BX lr ; Return to the caller NOP NOP - + ; Fill up 4kB page. ALIGN 4096 _txm_module_manager_user_mode_end - + END diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat index 8e6f8286..f0214cfc 100644 --- a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat @@ -3,4 +3,4 @@ arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -m arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module.c rem arm-none-eabi-gcc -g --elf --ro 0 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a rem arm-none-eabi-gcc -g -mcpu=cortex-a7 -T sample_threadx_module.ld -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork --specs=nosys.specs -e _txm_module_thread_shell_entry -o sample_threadx_module.out -Wl,-Map=sample_threadx_module.map gcc_setup.o txm_module_preamble.o sample_threadx_module.o txm.a -arm-none-eabi-ld -A cortex-a7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map
\ No newline at end of file +arm-none-eabi-ld -A cortex-a7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map
\ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S index 22a41727..d0eaeb79 100644 --- a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S +++ b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S @@ -22,7 +22,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -50,13 +50,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -67,9 +67,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -93,10 +93,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -130,4 +130,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/module_code.c b/ports_module/cortex_a7/gnu/example_build/module_code.c index 562ecea2..d380dfa9 100644 --- a/ports_module/cortex_a7/gnu/example_build/module_code.c +++ b/ports_module/cortex_a7/gnu/example_build/module_code.c @@ -4,7 +4,7 @@ /* */ /************************************************************************************************/ -/* +/* Input ELF file: .\sample_threadx_module.axf Output C Array file: .\module_code.c */ diff --git a/ports_module/cortex_a7/gnu/example_build/reset.S b/ports_module/cortex_a7/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports_module/cortex_a7/gnu/example_build/reset.S +++ b/ports_module/cortex_a7/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c index fce2a3fa..f9ed56eb 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,25 +129,25 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ @@ -156,14 +156,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,7 +172,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -180,14 +180,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ UINT status; *(ULONG *) 0x90000000 = 0xdeadbeef; *(ULONG *) 0x90000FFC = 0xfeed0add; *(ULONG *) 0x90001000 = 0xfedcba01; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -300,11 +300,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -363,7 +363,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -416,7 +416,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c index 8b17e34a..ac3bbeb5 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -45,7 +45,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -57,8 +57,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - first_unused_memory, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -71,46 +71,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -118,7 +118,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s index 6d1ceeff..0c267ac6 100644 --- a/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,18 +88,6 @@ THUMB_MASK = 0x20 // THUMB mode bit /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s index 7678628b..90c0c338 100644 --- a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s @@ -1,4 +1,4 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 /* Define common external references. */ @@ -28,7 +28,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry // Module Shell Entry Point .dc.l demo_module_start // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 2046 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry // Module Callback Thread Entry diff --git a/ports_module/cortex_a7/gnu/inc/tx_port.h b/ports_module/cortex_a7/gnu/inc/tx_port.h index 55400b6f..41040fa9 100644 --- a/ports_module/cortex_a7/gnu/inc/tx_port.h +++ b/ports_module/cortex_a7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,23 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -337,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/gnu/inc/txm_module_port.h b/ports_module/cortex_a7/gnu/inc/txm_module_port.h index a0a435b1..9cd5a280 100644 --- a/ports_module/cortex_a7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a7/gnu/inc/txm_module_port.h @@ -1,55 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/GNU */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/GNU */ /* 6.3.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -89,10 +81,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -299,7 +291,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -409,7 +401,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c index 5e22ff15..73a38340 100644 --- a/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -81,12 +82,6 @@ ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kern /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s index 8b55c21d..62b36534 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,21 +72,6 @@ SVC_MODE = 0x13 // SVC mode /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s index d29d464f..e124db7a 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s index 8876a873..a6f5cbeb 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,21 +75,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* CALLED BY */ /* */ /* FIQ ISR Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s index b6ac3bbf..2ce315f9 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,21 +68,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s index e2dbba7d..9938b4e6 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,18 +76,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s index 68cdb6ba..2be8b631 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s index 4d5c7442..15e244f1 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,18 +65,6 @@ FIQ_MASK = 0x040 /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s index 1fa006d8..7b6d8647 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,18 +58,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s index 725e4810..ba5fe5b6 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,18 +65,6 @@ FIQ_MASK = 0x040 /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s index 90573977..dfd8b554 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,18 +76,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s index 02be1d75..c87978e7 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s index 9faf80eb..54e2c768 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,16 +87,6 @@ FIQ_MASK = 0x040 /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s index d4dd01c7..f4f0717b 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,18 +74,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s index d2792904..fd8de227 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,21 +67,6 @@ SYS_MODE = 0x1F // SYS mode /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s index 27465bdf..ce0202d4 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,21 +67,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s index 8d70c67a..8c9b5186 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,18 +74,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c7178301..4641dcc8 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index fa79dc8a..bbb9013c 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 68bd8e44..303b17ce 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 7b6ea622..df6ca21e 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c index dcda0e1c..da8d0904 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -51,48 +52,42 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; __attribute__ ((aligned (16384))) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ __attribute__ ((aligned (1024))) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ __attribute__ ((aligned (1024))) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/GNU */ /* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ /* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -103,53 +98,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -167,98 +162,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; __asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); __asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; __asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; __asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -268,7 +263,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -277,21 +272,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); cp15reg |= 0x1; __asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 9a049056..60202970 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index d62f5cf8..e701846a 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,16 +68,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s index e84bb7f2..b9c59109 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .text .align 12 diff --git a/ports_module/cortex_a7/iar/example_build/cstartup.s b/ports_module/cortex_a7/iar/example_build/cstartup.s index 329decce..443be304 100644 --- a/ports_module/cortex_a7/iar/example_build/cstartup.s +++ b/ports_module/cortex_a7/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c index 0cad4a70..33a22445 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -128,42 +128,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -171,23 +171,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -241,7 +241,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -261,7 +261,7 @@ UINT status; /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -287,18 +287,18 @@ UINT status; /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -352,12 +352,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -410,7 +410,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf index bed79adf..69c8f600 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c index 9aa08e2f..b3a4f2f9 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -47,7 +47,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -59,8 +59,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_thread_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_thread_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -72,46 +72,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) 0x00100000); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -119,7 +119,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf index f076b002..ea39b4f5 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; //Module in 0x00100000-0x0013FFFF define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x200; define symbol __ICFEDIT_size_svcstack__ = 0x100; @@ -33,7 +33,7 @@ define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block PAGE_ALIGN with alignment = 4096 { section page_align }; +define block PAGE_ALIGN with alignment = 4096 { section page_align }; initialize by copy { readwrite }; initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application diff --git a/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s index 28ca3030..d3795786 100644 --- a/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0x1F ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,48 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -149,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -177,7 +168,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -185,17 +176,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -210,7 +201,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -229,22 +220,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -253,7 +244,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -277,11 +268,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start @@ -307,41 +298,41 @@ __tx_fiq_handler #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MMU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -389,7 +380,7 @@ __tx_abort_handler STR r0, [r3, #16] ; Save IFAR MRC p15, 0, r0, c5, c0, 1 ; Read IFSR STR r0, [r3, #20] ; Save IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -406,7 +397,7 @@ __tx_abort_handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -418,7 +409,7 @@ __tx_abort_handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -433,11 +424,11 @@ __tx_abort_handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s index 343d2a6b..4a42627b 100644 --- a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s @@ -26,7 +26,7 @@ __txm_module_preamble: DC32 0x6 ; Module Major Version DC32 0x1 ; Module Minor Version DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) + DC32 0x12345678 ; Module ID (application defined) DC32 0x00000001 ; Module Properties where: ; Bits 31-24: Compiler ID ; 0 -> IAR @@ -41,23 +41,23 @@ __txm_module_preamble: ; 1 -> User mode execution DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point DC32 1 ; Module Start/Stop Thread Priority DC32 1022 ; Module Start/Stop Thread Stack Size DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size DC32 ROPI$$Length ; Module Code Size DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 + DC32 0 ; Reserved 0 DC32 0 ; Reserved 1 DC32 0 ; Reserved 2 DC32 0 ; Reserved 3 DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 DC32 0 ; Reserved 9 DC32 0 ; Reserved 10 DC32 0 ; Reserved 11 diff --git a/ports_module/cortex_a7/iar/inc/tx_port.h b/ports_module/cortex_a7/iar/inc/tx_port.h index 3270eabe..fd21d57b 100644 --- a/ports_module/cortex_a7/iar/inc/tx_port.h +++ b/ports_module/cortex_a7/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ /* 6.3.0 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -65,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -82,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -118,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -133,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -190,7 +179,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_INLINE_INITIALIZATION #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -204,11 +193,11 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ @@ -239,7 +228,7 @@ ULONG _tx_misra_time_stamp_get(VOID); ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -259,11 +248,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -273,23 +262,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -322,20 +311,20 @@ void __iar_Initlocks(void); #ifndef TX_DISABLE_INLINE #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -393,7 +382,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); thread. */ void tx_thread_vfp_enable(void); -void tx_thread_vfp_disable(void); +void tx_thread_vfp_disable(void); /* Define the interrupt lockout macros for each ThreadX object. */ @@ -409,8 +398,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_a7/iar/inc/txm_module_port.h b/ports_module/cortex_a7/iar/inc/txm_module_port.h index 81a8eb17..247868ea 100644 --- a/ports_module/cortex_a7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_a7/iar/inc/txm_module_port.h @@ -1,48 +1,40 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/IAR */ /* 6.3.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ @@ -54,13 +46,13 @@ #ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in txm_module_user.h. The defines in this file may +/* Yes, include the user defines in txm_module_user.h. The defines in this file may alternately be defined on the command line. */ #include "txm_module_user.h" #endif -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -100,10 +92,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -310,7 +302,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -420,7 +412,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/iar Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/iar Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c index e34fdbea..cfe18ef1 100644 --- a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s index 2d4a1428..bf3c0e54 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; @@ -39,47 +39,38 @@ SYS_MODE EQU 0x1F ; SYS mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -183,7 +174,7 @@ restore_and_return_from_irq: ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s index 51d17e4d..139ae048 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,46 +29,37 @@ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s index 77425a1e..2e5370ec 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,7 +21,7 @@ SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -36,47 +36,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits EXTERN _tx_execution_isr_exit #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -108,13 +99,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; POP {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -125,7 +116,7 @@ _tx_thread_fiq_context_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -169,7 +160,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -181,7 +172,7 @@ __tx_thread_fiq_no_preempt_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -225,7 +216,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type PUSH {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -237,7 +228,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s index 36330436..925c5261 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -26,46 +26,37 @@ EXTERN _tx_execution_isr_enter #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -86,7 +77,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -101,7 +92,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -117,38 +108,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -161,7 +152,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -181,18 +172,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s index fe49fea3..d9e92fc4 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -24,57 +24,48 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -91,7 +82,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s index 75e6b0d7..bde34045 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -23,51 +23,42 @@ FIQ_DISABLE EQU 0x40 ; FIQ disable bit MODE_MASK EQU 0x1F ; Mode mask SYS_MODE_BITS EQU 0x1F ; System mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s index 94c42a69..1840fb85 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,45 +28,36 @@ FIQ_MASK EQU 0x40 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s index 1bbbe754..f965666f 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,44 +21,35 @@ -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) @@ -81,7 +72,7 @@ _tx_thread_interrupt_disable #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ #else - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ #endif BX lr ; Return to caller diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s index 65df8b7e..6292bbd6 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -25,45 +25,36 @@ IRQ_MASK EQU 0x80 ; Interrupt bit mask FIQ_MASK EQU 0x40 ; Interrupt bit mask #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s index cbee12f2..ac26b693 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -27,59 +27,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s index 96a7fed4..3c7a5ec1 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -26,51 +26,42 @@ MODE_MASK EQU 0x1F ; Mode mask SYS_MODE_BITS EQU 0x1F ; System mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s index 4b92a25b..3b446f04 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_execute_ptr @@ -26,7 +26,7 @@ #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) EXTERN _tx_execution_thread_enter #endif - + IRQ_MODE EQU 0xD2 ; IRQ mode USR_MODE EQU 0x10 ; USR mode SVC_MODE EQU 0x13 ; SVC mode @@ -38,7 +38,7 @@ IRQ_MASK EQU 0x80 ; Interrupt bit mask FIQ_MASK EQU 0x40 ; Interrupt bit mask #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask EXTERN _txm_system_mode_enter @@ -47,48 +47,39 @@ THUMB_MASK EQU 0x20 ; Thumb bit mask -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -161,11 +152,11 @@ _tx_handler_svc_unrecognized BKPT 0x0000 _tx_handler_svc_unrecognized_loop ; We should never get here B _tx_handler_svc_unrecognized_loop - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 1, which means we are entering + ; At this point we have an SVC 1, which means we are entering ; supervisor mode to service a kernel call. _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) @@ -213,7 +204,7 @@ _tx_handler_svc_super_enter ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -228,7 +219,7 @@ _tx_handler_svc_super_enter ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 2, which means we are exiting + ; At this point we have an SVC 2, which means we are exiting ; supervisor mode after servicing a kernel call. _tx_handler_svc_super_exit: ; Make sure that we have been called from the system mode exit location (security) @@ -266,14 +257,14 @@ _tx_handler_svc_super_exit: LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; Restore the registers and return #if defined(THUMB_MODE) POP {r0-r3, r12, lr} @@ -282,7 +273,7 @@ _tx_handler_svc_arm ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -303,8 +294,8 @@ _tx_handler_svc_schedule POP {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -407,10 +398,10 @@ __tx_thread_schedule_loop ; test address translation ;mcr p15, 0, r0, c7, c8, 0 - + _tx_skip_mmu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return @@ -442,7 +433,7 @@ _tx_skip_interrupt_vfp_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -453,7 +444,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -464,7 +455,7 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore #endif - + POP {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode @@ -475,7 +466,7 @@ _tx_skip_solicited_vfp_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -486,7 +477,7 @@ _tx_skip_solicited_vfp_restore ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; End SWI_Handler ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - + #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable #ifdef THUMB_MODE diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s index fc692efc..09cecfa8 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ SVC_MODE EQU 0x13 ; SVC mode SYS_MODE EQU 0x1F ; SYS mode @@ -31,47 +31,38 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR EXTERN _tx_thread_schedule -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -85,10 +76,10 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR #endif _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s index 6307c693..f22ca01c 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -23,50 +23,41 @@ EXTERN _tx_timer_time_slice EXTERN _tx_thread_schedule #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - EXTERN _tx_execution_thread_exit + EXTERN _tx_execution_thread_exit #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s index a4c6b041..dcd4ed95 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -25,46 +25,37 @@ EXTERN _tx_execution_isr_enter #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -127,7 +118,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -150,12 +141,12 @@ __tx_thread_not_nested_save #endif BX lr ; Return to caller - + __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s index fd2c46b9..8580a4c7 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -33,49 +33,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -105,7 +96,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -223,13 +214,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index e22cfc63..e8107c19 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,45 +26,39 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* Initial thread stack frame */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 08ab19f7..5361822c 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 94e6e502..46d39bee 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 32911033..c0a87261 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c index ad70a286..e76ae60a 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -52,50 +53,44 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ -#pragma data_alignment=1024 +#pragma data_alignment=1024 ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ -#pragma data_alignment=1024 +#pragma data_alignment=1024 ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -106,53 +101,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -170,98 +165,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -271,7 +266,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -280,21 +275,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); cp15reg |= 0x1; asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 1a394c05..3d477a4a 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index f0018aa0..cedcb217 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR @@ -29,47 +29,38 @@ CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ i CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -86,7 +77,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s index c3eb43da..f25a5ea0 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,57 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; EXTERN _txm_module_manager_kernel_dispatch - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* tx Cortex-A7/MMU/IAR */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* tx Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ RSEG .text:CODE:NOROOT(2) @@ -100,10 +91,10 @@ _txm_system_mode_exit BX lr ; Return to the caller NOP NOP - + ; Fill up 4kB page. SECTION page_align:CONST:ROOT(2) - + _txm_module_manager_user_mode_end - + END diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject index 22cf258d..8f5b0d96 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 0a4f183b..0c6c1e74 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject index 3f9e781c..7388640f 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject index d89095b9..e3141bd8 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index a9202a6e..dcc369ae 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject index 0516ff74..1f5d07d9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject @@ -1,166 +1,166 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ </toolChain> - + </folderInfo> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/example_build/txm/.cproject b/ports_module/cortex_m0+/ac6/example_build/txm/.cproject index 1cf6986c..0b56c6d7 100644 --- a/ports_module/cortex_m0+/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/ac6/inc/tx_port.h b/ports_module/cortex_m0+/ac6/inc/tx_port.h index c25eeac5..374db939 100644 --- a/ports_module/cortex_m0+/ac6/inc/tx_port.h +++ b/ports_module/cortex_m0+/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -110,7 +102,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -121,8 +113,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -151,7 +143,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -163,7 +155,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -202,11 +194,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -214,8 +206,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -268,13 +260,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -347,7 +339,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -375,7 +367,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -405,14 +397,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -431,9 +423,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -482,7 +474,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -516,8 +508,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h index 7eaf5a31..4ad075ee 100644 --- a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S index dab2dc35..9e439c1f 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c index 09e323c0..13f57b8d 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _txm_module_initialize(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S index a2021a26..28245b55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S index 24eeffb9..cfe953dc 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S index 6100ed57..43bc635a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S index 73d5a537..7a69a31e 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S index 656abc16..972a7ea5 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S index a1559844..bc9e27f8 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S index a3892f1e..c8960eaf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S index 0c426bfb..15035d55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S index d0825135..3195b970 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 7e04f022..5e8190ae 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject index 63be6be1..f92a30da 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject @@ -1,166 +1,166 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S index f5090533..445f77cf 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject index 9dc7b2bb..8ceaed84 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject @@ -1,178 +1,178 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s index f055d1c5..013e5825 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s @@ -16,7 +16,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -44,13 +44,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table adds r0, r0, #4 // Move to next entry - adds r1, r1, #4 // + adds r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -61,9 +61,9 @@ got_setup_done: subs r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ subs r0,r0,r4 add r0,r0,r9 @@ -87,12 +87,12 @@ got_setup_done: str r2, [r0] adds r0, r0, #4 str r1, [r0] - + /* Store other preserved registers. */ pop {r3-r7} mov lr, r8 bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -128,4 +128,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 1efc6ca1..96320525 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -130,7 +130,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -140,7 +140,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S index dec92093..8ea214ba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,8 +1,8 @@ .text .align 4 .syntax unified - .section .preamble - + .section .preamble, "ax" + // Define public symbols .global __txm_module_preamble .global __txm_module_preamble_two diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject index c243c1fd..d1a7a6cc 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,174 +1,174 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath=""> - + <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.1351701976" name="GCC 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi"> - + <targetPlatform binaryParser="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.1351701976.1801457245" name=""/> - + <builder buildPath="${workspace_loc:/sample_threadx_module_manager}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.629037601" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi.1023531190" name="GCC C Compiler 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi"> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.1348671717" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic_modules}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/> - + </option> - + <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.197992404" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/> - + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1565829921" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/> - 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+ </option> - + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags.2030235754" name="Other flags" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.flags" useByScannerDiscovery="false" value="-g -mcpu=cortex-m0plus -mthumb -ereset_handler -nostartfiles -g" valueType="string"/> - + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.removeunused.1345887013" name="Remove unused sections" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.option.removeunused" useByScannerDiscovery="false" value="false" valueType="boolean"/> - + <inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.31417068" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input"> - + <additionalInput kind="additionalinput" paths="$(LIBS)"/> - + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> - + </inputType> - + </tool> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi.1211424537" name="GCC C++ Linker 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi.433657468" name="GCC Archiver 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + <scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520;com.arm.eclipse.build.config.v6.exe.debug.base.1025296520.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi.1023531190;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.821451276"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </scannerConfigBuildInfo> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 283dc71a..f47155b8 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -72,8 +72,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -93,22 +93,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -117,11 +117,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 663c92ba..4928d596 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s index 60662fe3..452c8934 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word HardFaultException .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject index a1c0d7ab..4374ece6 100644 --- a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - 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+ <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath=""> - + <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.157019840" name="GCC 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi"> - + <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.157019840.1011349438" name=""/> - + <builder buildPath="${workspace_loc:/tx}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.1702635634" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi.107776602" name="GCC C Compiler 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi"> - 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+ <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi.914627011" name="GCC Archiver 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi"/> - + </toolChain> - + </folderInfo> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject index f04340b4..fcae5c35 100644 --- a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject @@ -1,168 +1,168 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath=""> - + <toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.652531184" name="GCC 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi"> - + <targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.var.gcc-10.2.1-arm-none-eabi.652531184.612061639" name=""/> - + <builder buildPath="${workspace_loc:/txm}/Debug" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.1413866003" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi.1267556721" name="GCC C Compiler 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-10.2.1-arm-none-eabi"> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath.973671624" name="Include paths (-I)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.includepath" useByScannerDiscovery="false" valueType="includePath"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_port}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_modules}""/> - + <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_module_manager}""/> - + </option> - + <option defaultValue="gnu.c.optimization.level.none" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1946000897" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/> - + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1486677946" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false"/> - + <option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu.896084173" name="CPU (-mcpu)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.cpu" useByScannerDiscovery="false" value="cortex-m0plus" valueType="string"/> - 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+ <additionalInput kind="additionalinput" paths="$(LIBS)"/> - + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> - + </inputType> - + </tool> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi.854576146" name="GCC C++ Linker 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-10.2.1-arm-none-eabi"/> - + <tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi.706397807" name="GCC Archiver 10.2.1 [arm-none-eabi]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-10.2.1-arm-none-eabi"/> - + </toolChain> - + </folderInfo> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m0+/gnu/inc/tx_port.h b/ports_module/cortex_m0+/gnu/inc/tx_port.h index f2cc8240..0c2e90e5 100644 --- a/ports_module/cortex_m0+/gnu/inc/tx_port.h +++ b/ports_module/cortex_m0+/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -125,7 +117,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -136,8 +128,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -166,7 +158,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -178,7 +170,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -217,19 +209,19 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -282,13 +274,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -361,7 +353,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -389,7 +381,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -419,14 +411,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -445,9 +437,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -496,7 +488,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -530,8 +522,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h index 46f2e60d..3ab998ae 100644 --- a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c index db33fd67..2bb3bf7e 100644 --- a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S index d68c6c76..dc04a44d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S index beea2c1b..abd44ea0 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S index 4523a729..9ca7b3c7 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S index e7c45568..f0584738 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S index 7230fa3f..2aaaac2d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S index 04d68a14..61865ee5 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S index 49c0a239..653a58a8 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S index 94b06b59..2c5c5274 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S index 4b7810ff..e1199f1c 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 726c6189..19fce081 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s index da53c200..3ae600b5 100644 --- a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c index 647dcced..a91c3b8c 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -105,7 +105,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -121,7 +121,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -133,42 +133,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -176,23 +176,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -295,19 +295,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)EXTERNAL_MEMORY = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c index e928709f..b944f46e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c @@ -67,11 +67,11 @@ int main() void tx_application_define(void *first_unused_memory) { -CHAR *pointer = (CHAR*)module_manager_stack; +CHAR *pointer = (CHAR*)module_manager_stack; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -91,22 +91,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) MODULE_CODE); - + /* Enable 128 byte read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -115,11 +115,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf index 5e6f652e..92334d1e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf @@ -18,8 +18,8 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/ports_module/cortex_m0+/iar/example_build/startup.s b/ports_module/cortex_m0+/iar/example_build/startup.s index 06de32fb..34ce08e8 100644 --- a/ports_module/cortex_m0+/iar/example_build/startup.s +++ b/ports_module/cortex_m0+/iar/example_build/startup.s @@ -6,10 +6,10 @@ ;* Description : STM32F2xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP -;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* - Configure he external SRAM mounted on STM322xG-EVAL board ;* to be used as data memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -72,86 +72,86 @@ __vector_table DC32 SysTick_Handler ; SysTick ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -164,7 +164,7 @@ __vector_table Reset_Handler CPSID i ; Disable interrupts LDR R0, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R0 + MSR MSP, R0 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code BX R0 @@ -215,47 +215,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -264,358 +264,358 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler END diff --git a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s index e26ea7f0..16404d63 100644 --- a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -40,11 +40,11 @@ ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; SECTION `.text`:CODE:NOROOT(2) @@ -83,12 +83,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ @@ -178,7 +172,7 @@ __tx_SysTickHandler: MOV lr, r1 BX lr ; } - + END - + diff --git a/ports_module/cortex_m0+/iar/inc/tx_port.h b/ports_module/cortex_m0+/iar/inc/tx_port.h index f41b5a6f..2f4abd56 100644 --- a/ports_module/cortex_m0+/iar/inc/tx_port.h +++ b/ports_module/cortex_m0+/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -129,7 +121,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -140,8 +132,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -180,7 +172,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -194,7 +186,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -230,10 +222,10 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID *tx_thread_module_reserved; #endif #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -255,11 +247,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, @@ -268,23 +260,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #ifdef TX_ENABLE_FPU_SUPPORT @@ -338,13 +330,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -417,7 +409,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -445,7 +437,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE /* @@ -479,14 +471,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -503,9 +495,9 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -566,8 +558,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m0+/iar/inc/txm_module_port.h b/ports_module/cortex_m0+/iar/inc/txm_module_port.h index 9d3ca242..8561f21e 100644 --- a/ports_module/cortex_m0+/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c index 6d4b4f52..8983b832 100644 --- a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s index ef9d5bea..236515eb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -106,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -1014,7 +1015,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR ;; return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1029,7 +1030,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR ;; return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -1046,8 +1047,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 ; Build FPCCR address LDR r0, [r0] ; Load FPCCR value BX LR ;; return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1061,10 +1062,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR ;; return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S index 1dd17d7c..229055e2 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S index 034a9c0a..3e9eebc7 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S index 7317efa0..434c52c6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S index bdca7a0a..3ee1d914 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S index db969358..d7342b28 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S index 4eeeff3e..517d337a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,20 +64,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* change handler name, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S index 925631ed..5ced33f6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S index 23a71b4a..b485e12b 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S index cc2680cd..5210c308 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S index cf911004..6271f32f 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt index 259a3e72..f07f042c 100644 --- a/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt +++ b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt @@ -2,7 +2,7 @@ # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] diff --git a/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 476361d7..66e03dff 100644 --- a/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h index 2572a044..26bc6b93 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -326,7 +326,7 @@ // <0=>Secure // <1=>Non-Secure // <i> Value for SCB->ICSR register bit STTNS -// <i> only for single SysTick implementation +// <i> only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c index cf78a4ed..a79cb61d 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -77,7 +77,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index a37b412e..40fc81c1 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c index a65b6880..04d857ff 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c index 9ff73190..25da24c8 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include <arm_cmse.h> #include <stdlib.h> #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x00040000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c index f3152890..ca7f0c56 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c @@ -24,7 +24,7 @@ * Title: Context Management for ARMv8-M TrustZone - Sample implementation * *---------------------------------------------------------------------------*/ - + #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // <h>System Configuration // ======================= - + // <o>Global Dynamic Memory size [bytes] <0-1073741824:8> // <i> Defines the combined global dynamic memory size. // <i> Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // <o>Kernel Tick Frequency [Hz] <1-1000000> // <i> Defines base time unit for delays and timeouts. // <i> Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // <e>Round-Robin Thread switching // <i> Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // <o>Round-Robin Timeout <1-1000> // <i> Defines how many ticks a thread will execute before a thread switch. // <i> Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // </e> - -// <o>ISR FIFO Queue + +// <o>ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // <q>Object Memory usage counters // <i> Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // </h> - + // <h>Thread Configuration // ======================= - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // <o>Number of user Threads <1-1000> // <i> Defines maximum number of user threads that can be active at the same time. // <i> Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // <o>Number of user Threads with default Stack size <0-1000> // <i> Defines maximum number of user threads with default stack size. // <i> Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // <i> Defines the combined stack size for user threads with user-provided stack size. // <i> Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // </e> - + // <o>Default Thread Stack size [bytes] <96-1073741824:8> // <i> Defines stack size for threads with zero stack size specified. // <i> Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // <o>Idle Thread Stack size [bytes] <72-1073741824:8> // <i> Defines stack size for Idle thread. // <i> Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // <o>Idle Thread TrustZone Module Identifier // <i> Defines TrustZone Thread Context Management Identifier. // <i> Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // <q>Stack overrun checking // <i> Enables stack overrun check at thread switch. // <i> Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // <q>Stack usage watermark // <i> Initializes thread stack with watermark pattern for analyzing stack usage. // <i> Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// <o>Processor mode for Thread execution -// <0=> Unprivileged mode + +// <o>Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // <i> Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // </h> - + // <h>Timer Configuration // ====================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // <o>Number of Timer objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // </e> - + // <o>Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // <o>Timer Thread Stack size [bytes] <0-1073741824:8> // <i> Defines stack size for Timer thread. // <i> May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // <o>Timer Thread TrustZone Module Identifier // <i> Defines TrustZone Thread Context Management Identifier. // <i> Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // <o>Timer Callback Queue entries <0-256> // <i> Number of concurrent active timer callback functions. // <i> May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // </h> - + // <h>Event Flags Configuration // ============================ - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // <o>Number of Event Flags objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // </e> - + // </h> - + // <h>Mutex Configuration // ====================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // <o>Number of Mutex objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // </e> - + // </h> - + // <h>Semaphore Configuration // ========================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // <o>Number of Semaphore objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // </e> - + // </h> - + // <h>Memory Pool Configuration // ============================ - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // <o>Number of Memory Pool objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // <o>Data Storage Memory size [bytes] <0-1073741824:8> // <i> Defines the combined data storage memory size. // <i> Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // </e> - + // </h> - + // <h>Message Queue Configuration // ============================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // <o>Number of Message Queue objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // <o>Data Storage Memory size [bytes] <0-1073741824:8> // <i> Defines the combined data storage memory size. // <i> Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // </e> - + // </h> - + // <h>Event Recorder Configuration // =============================== - + // <e>Global Initialization // <i> Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // <q>Start recording // <i> Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // <h>Global Event Filter Setup // <i> Initial recording level applied to all components. // <o.0>Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // <h>RTOS Event Filter Setup // <i> Recording levels for RTX components. // <i> Only applicable if events for the respective component are generated. - + // <h>Memory Management // <i> Recording level for Memory Management events. // <o.0>Error events @@ -374,10 +374,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // <h>Kernel // <i> Recording level for Kernel events. // <o.0>Error events @@ -385,10 +385,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // <h>Thread // <i> Recording level for Thread events. // <o.0>Error events @@ -396,10 +396,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // <h>Generic Wait // <i> Recording level for Generic Wait events. // <o.0>Error events @@ -407,10 +407,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // <h>Thread Flags // <i> Recording level for Thread Flags events. // <o.0>Error events @@ -418,10 +418,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // <h>Event Flags // <i> Recording level for Event Flags events. // <o.0>Error events @@ -429,10 +429,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // <h>Timer // <i> Recording level for Timer events. // <o.0>Error events @@ -440,10 +440,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // <h>Mutex // <i> Recording level for Mutex events. // <o.0>Error events @@ -451,10 +451,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // <h>Semaphore // <i> Recording level for Semaphore events. // <o.0>Error events @@ -462,10 +462,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // <h>Memory Pool // <i> Recording level for Memory Pool events. // <o.0>Error events @@ -473,10 +473,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // <h>Message Queue // <i> Recording level for Message Queue events. // <o.0>Error events @@ -484,87 +484,87 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // </h> - + // </e> - + // <h>RTOS Event Generation // <i> Enables event generation for RTX components (requires RTX source variant). - + // <q>Memory Management // <i> Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // <q>Kernel // <i> Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // <q>Thread // <i> Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // <q>Generic Wait // <i> Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // <q>Thread Flags // <i> Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // <q>Event Flags // <i> Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // <q>Timer // <i> Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // <q>Mutex // <i> Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // <q>Semaphore // <i> Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // <q>Memory Pool // <i> Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // <q>Message Queue // <i> Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // </h> - + // </h> - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct index 2b6482c7..219b6869 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -70,7 +70,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } - + SHARED_MEM SHARED_MEM_BASE SHARED_MEM_SIZE { sample_threadx_module_manager.o (sharedmem) } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 1cde6a79..35f9ceae 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 57fcc32f..50a40460 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -72,8 +72,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -87,9 +87,9 @@ void module_manager_entry(ULONG thread_input) { (void)thread_input; - + tx_thread_secure_stack_allocate(&module_manager, 256); - + /* Initialize the module manager. */ txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE); @@ -97,22 +97,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -121,11 +121,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h index 4470aa37..1d498227 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'sample_threadx_module' - * Target: 'FVP Simulation Model' + * Project: 'sample_threadx_module' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c index bc55de5c..cbf252e4 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -27,7 +27,7 @@ #define EXTERNAL_MEMORY (0x20040000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -108,7 +108,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -124,7 +124,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -136,42 +136,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -179,23 +179,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -239,21 +239,21 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + tx_thread_secure_stack_allocate(thread_0, 256); thread_0_counter = func1(thread_0_counter); tx_thread_secure_stack_free(thread_0); - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -302,18 +302,18 @@ UINT status; /* Test external memory sharing. */ // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; // *(ULONG *)0x20040004 = 0x01010101; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -372,7 +372,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -425,7 +425,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f6530c9f..302efdf2 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section RESET - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 98e29203..00d7b325 100644 --- a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,19 +81,19 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -116,21 +111,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -162,7 +157,7 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - + /* Do interrupt handler work here */ /* .... */ @@ -201,7 +196,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h index 74656ec0..0c7e0eba 100644 --- a/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'txm' - * Target: 'ThreadX Module Library' + * Project: 'txm' + * Target: 'ThreadX Module Library' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index 5686cdd3..30f56817 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,19 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -63,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -107,24 +95,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -380,12 +368,12 @@ static void _set_control(unsigned int _control) _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -527,9 +515,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -576,7 +564,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h index 1e26542c..9f38a588 100644 --- a/ports_module/cortex_m23/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,15 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -356,6 +348,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S index f0e6c764..82f6357d 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize @@ -107,7 +98,7 @@ __rt_entry: LDM r0,{r0-r1} BL __rt_lib_init // Call ARM func to initialize library POP {r0-r1} // Restore dregs and LR - MOV r12, r0 + MOV r12, r0 MOV lr, r1 POP {r0-r7} MOV r8, r0 diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c index 5603e5fc..0be91d63 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -89,16 +90,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -113,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -128,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S index 2b724e21..fac7b4bc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S index ba7ea70c..e1b624bd 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S index 9adce6f9..950717cd 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S index dceff9bc..6a8dafd0 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S index fd52f19e..9092edc1 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S index 896204dc..8e4df0c3 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -174,7 +162,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -416,7 +404,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -528,7 +516,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -609,7 +597,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c index baae59d8..0073bd47 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index 4560e059..8fd91971 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S index 7bec56b3..03476dd0 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index 2bb69e1b..3c5fdde6 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S index 302e4ad1..b8b83e12 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -95,7 +90,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S index c27056bb..22244f01 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S index 1b0dd93b..b8bef35a 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 3533a3f5..ef874245 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -93,7 +88,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S index a9413251..5f663569 100644 --- a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble @@ -32,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 6f122445..0f2de686 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,29 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* remove unneeded headers, */ -/* use builtins, added */ -/* ULONG64_DEFINED,updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Modified comment(s), */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -73,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -116,24 +94,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -405,9 +383,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -487,7 +465,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h index 66eb089d..63f683c1 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/gnu/inc/txm_module_port.h b/ports_module/cortex_m23/gnu/inc/txm_module_port.h index 1ace4fdf..04e72d0c 100644 --- a/ports_module/cortex_m23/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m23/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -346,6 +341,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c index 0d180985..b4e75378 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the GNU C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S index 4b4d3b62..d38525bf 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -87,20 +82,20 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address // /* Enable the cycle count register. */ // // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -118,21 +113,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -164,7 +159,7 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - + /* Do interrupt handler work here */ /* .... */ @@ -203,7 +198,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S index f0de20a2..2f9d7165 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S index c7dce4ea..f51cff71 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S index 7fcfa9f4..8bfbbd09 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S index addb7915..62b1a017 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S index 24174940..7ac71319 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S index dbeecb88..eea9818d 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,19 +54,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -170,7 +158,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -412,7 +400,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -524,7 +512,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -605,7 +593,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c index 4f757f90..44376c27 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1e322ad4..a569e07e 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S index 4b51958c..9a1e28c3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index 6cec7c52..ae66a5c5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S index b53609b0..0430d672 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -95,7 +90,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S index 85d38e4d..a09ad30d 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S index e1eef248..3bc77594 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index aa72b0be..99bfa470 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -93,7 +88,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c index 28299f6c..59aee1b9 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s index 69bd7e29..fb6a109f 100644 --- a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,13 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -100,7 +94,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -118,21 +112,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -191,7 +185,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 14d287ef..9f8547da 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,19 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -118,24 +106,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -452,7 +440,7 @@ __attribute__( ( always_inline ) ) static inline void __set_CONTROL(ULONG contro /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -610,7 +598,7 @@ extern void _tx_thread_secure_stack_initialize(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif /* Define the interrupt disable/restore macros for each compiler. */ @@ -707,7 +695,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h index 13cb4b44..ac4a99d4 100644 --- a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/iar/inc/txm_module_port.h b/ports_module/cortex_m23/iar/inc/txm_module_port.h index 2b5e7b3d..d394aaaf 100644 --- a/ports_module/cortex_m23/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m23/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -349,6 +344,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c index e0c84d32..1bcfe689 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s index 83ab38c9..11f3d018 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s index 8ea8a775..bb6b9d51 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s index 1e5e1973..5a74b366 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s index 375c9926..6b95841a 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s index 3768cfb3..c5a40257 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s index 5c7aafaa..f7f933e0 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -178,7 +165,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -413,7 +400,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -519,7 +506,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -600,7 +587,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c index 099097fb..9ce9ccc3 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s index bc935c8b..7c7dfacf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s index e99f7bf3..0701c03c 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 95f0c250..325a62bf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,17 +51,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s index bbb60ae6..71d25cec 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -90,7 +84,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s index f574ed35..91ef52c7 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s index 9dd72463..eadef8bf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,13 +68,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s index ed95928c..a60e86df 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -91,7 +85,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S index 951a71d8..057ccc9a 100644 --- a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -93,7 +93,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - + ; ; AREA ||.text||, CODE, READONLY @@ -111,45 +111,39 @@ Reset_Handler BX r0 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -162,24 +156,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -210,11 +204,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -230,19 +224,19 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler ; EXPORT __tx_SVCallHandler ;__tx_SVCallHandler -; B __tx_SVCallHandler +; B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -261,7 +255,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -280,5 +274,5 @@ _tx_execution_thread_exit ALIGN LTORG END - + diff --git a/ports_module/cortex_m3/ac5/inc/tx_port.h b/ports_module/cortex_m3/ac5/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/ac5/inc/tx_port.h +++ b/ports_module/cortex_m3/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s index 0c1a90c4..3e18af11 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c index 8884a54f..b1e803f9 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s index 23503273..d8c8d6dd 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s index 75a68861..3d59c966 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s index 050d349d..340ef0f6 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s index 01642018..86308572 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s index d5b937f6..917db4e4 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s index 7313d2ff..e698f259 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s index fa77e2d6..6639bdf8 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s index 53d48047..e10d05c6 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s index b87639de..68b30e98 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index f118dc53..d800c32a 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index fab47c06..d5f331f2 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject index 774d26ab..db508892 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject @@ -1,192 +1,192 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> - + </option> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"> - + <externalSettings containerId="tx;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier"> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + </storageModule> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 98d3abb0..72f44643 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject index 3c6f49d9..4f468747 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject index 08b7a614..109a9c00 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> - + </option> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 4331ef40..5f263cae 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/tx/.cproject b/ports_module/cortex_m3/ac6/example_build/tx/.cproject index 06929bd2..a91b3227 100644 --- a/ports_module/cortex_m3/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings> - + <externalSetting> - + <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - 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+ <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/> - + <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/> - + <entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/> - + <entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/> - + </externalSetting> - + </externalSettings> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m3/ac6/inc/tx_port.h b/ports_module/cortex_m3/ac6/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/ac6/inc/tx_port.h +++ b/ports_module/cortex_m3/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S index 6f184df2..882a7d1c 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index 45d8b720..518704d7 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index 949478b5..bc2b4752 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index f6a10399..22f46a26 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index dcc24d49..c2435528 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S index a1a0b459..37525e38 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S index bc5b910a..3c3e2473 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index ed1e99b2..56187f4c 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index d5cc0b49..31303ef8 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index e7471605..e1c5c2a2 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index ee13bef8..05d5c227 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index de5794dc..3d8485ce 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s b/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s +++ b/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m3/gnu/example_build/gcc_setup.s b/ports_module/cortex_m3/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m3/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m3/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S index e9c66cc0..edc1eef3 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ //VOID _tx_initialize_low_level(VOID) //{ @@ -91,14 +86,14 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer /* Setup Vector Table Offset Register. */ MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer @@ -110,7 +105,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 @ Build address of NVIC registers @@ -130,10 +125,10 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - + /* Return to caller. */ - BX lr + BX lr //} @@ -160,7 +155,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL <your C Function>.... */ @@ -196,7 +191,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S index 590991a6..b032a347 100644 --- a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m3/gnu/inc/tx_port.h b/ports_module/cortex_m3/gnu/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/gnu/inc/tx_port.h +++ b/ports_module/cortex_m3/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c index eec57f67..e8af97a9 100644 --- a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S index f36f0e79..1862bb58 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S index bcc690d0..ac76a239 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S index e7ea870e..a56149e3 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S index b0169c6d..dee2237f 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S index ef0298b4..bd00f5f7 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S index aeff0993..8336214b 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S index d78ebdc1..5b7d97c4 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S index 3fa0c7a2..9d9a32fc 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S index fc3e9db3..7f9a4359 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 068ed64a..d7141d93 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/iar/example_build/cstartup_M.s b/ports_module/cortex_m3/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m3/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m3/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx.c b/ports_module/cortex_m3/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c index ca18eea6..b7d88a09 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf index 5e6f652e..92334d1e 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf @@ -18,8 +18,8 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/ports_module/cortex_m3/iar/example_build/startup.s b/ports_module/cortex_m3/iar/example_build/startup.s index bbe8142b..2eb88dff 100644 --- a/ports_module/cortex_m3/iar/example_build/startup.s +++ b/ports_module/cortex_m3/iar/example_build/startup.s @@ -6,10 +6,10 @@ ;* Description : STM32F2xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP -;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* - Configure he external SRAM mounted on STM322xG-EVAL board ;* to be used as data memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -72,86 +72,86 @@ __vector_table DC32 SysTick_Handler ; SysTick ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -164,7 +164,7 @@ __vector_table Reset_Handler CPSID i ; Disable interrupts LDR R0, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R0 + MSR MSP, R0 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code BX R0 @@ -215,47 +215,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -264,358 +264,358 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler END diff --git a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s index 0491ca43..f3262e15 100644 --- a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -40,11 +40,11 @@ ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; SECTION `.text`:CODE:NOROOT(2) @@ -83,12 +83,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ @@ -101,7 +95,7 @@ _tx_initialize_low_level: ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address @@ -111,13 +105,13 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, #1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -148,8 +142,8 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; ; @@ -174,7 +168,7 @@ __tx_SysTickHandler: POP {r0, lr} BX LR ; } - + END - + diff --git a/ports_module/cortex_m3/iar/inc/tx_port.h b/ports_module/cortex_m3/iar/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/iar/inc/tx_port.h +++ b/ports_module/cortex_m3/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c index 31434744..d4fd04ec 100644 --- a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s index 35aeaf5b..96b7d2d7 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s index f8bf5036..9d575f8f 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s index a0f3a5d0..75952281 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s index 999af964..ce7ceb62 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s index 2e55ed27..3cc26d93 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s index 21edb519..f97239f6 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s index 116ba71c..eb2c3ffb 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s index a19bd35d..712a6e5c 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s index a2d8ca32..2801dd7d 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s index daaf5cf7..eea5683c 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt index 04e32d1f..b65ba4c8 100644 --- a/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt +++ b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt @@ -14,7 +14,7 @@ cpu0.INITNSVTOR=0x0 # (int , init-time) defa cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write diff --git a/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c index 36cb0c63..6edd89de 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -96,7 +96,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 65bfdcd7..ebbc79c0 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c index a65b6880..04d857ff 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c index 548b383a..6e48de6e 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include <arm_cmse.h> #include <stdlib.h> #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x100000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // <h>System Configuration // ======================= - + // <o>Global Dynamic Memory size [bytes] <0-1073741824:8> // <i> Defines the combined global dynamic memory size. // <i> Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // <o>Kernel Tick Frequency [Hz] <1-1000000> // <i> Defines base time unit for delays and timeouts. // <i> Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // <e>Round-Robin Thread switching // <i> Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // <o>Round-Robin Timeout <1-1000> // <i> Defines how many ticks a thread will execute before a thread switch. // <i> Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // </e> - -// <o>ISR FIFO Queue + +// <o>ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // <q>Object Memory usage counters // <i> Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // </h> - + // <h>Thread Configuration // ======================= - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // <o>Number of user Threads <1-1000> // <i> Defines maximum number of user threads that can be active at the same time. // <i> Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // <o>Number of user Threads with default Stack size <0-1000> // <i> Defines maximum number of user threads with default stack size. // <i> Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // <i> Defines the combined stack size for user threads with user-provided stack size. // <i> Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // </e> - + // <o>Default Thread Stack size [bytes] <96-1073741824:8> // <i> Defines stack size for threads with zero stack size specified. // <i> Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // <o>Idle Thread Stack size [bytes] <72-1073741824:8> // <i> Defines stack size for Idle thread. // <i> Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // <o>Idle Thread TrustZone Module Identifier // <i> Defines TrustZone Thread Context Management Identifier. // <i> Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // <q>Stack overrun checking // <i> Enables stack overrun check at thread switch. // <i> Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // <q>Stack usage watermark // <i> Initializes thread stack with watermark pattern for analyzing stack usage. // <i> Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// <o>Processor mode for Thread execution -// <0=> Unprivileged mode + +// <o>Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // <i> Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // </h> - + // <h>Timer Configuration // ====================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // <o>Number of Timer objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // </e> - + // <o>Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // <o>Timer Thread Stack size [bytes] <0-1073741824:8> // <i> Defines stack size for Timer thread. // <i> May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // <o>Timer Thread TrustZone Module Identifier // <i> Defines TrustZone Thread Context Management Identifier. // <i> Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // <o>Timer Callback Queue entries <0-256> // <i> Number of concurrent active timer callback functions. // <i> May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // </h> - + // <h>Event Flags Configuration // ============================ - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // <o>Number of Event Flags objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // </e> - + // </h> - + // <h>Mutex Configuration // ====================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // <o>Number of Mutex objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // </e> - + // </h> - + // <h>Semaphore Configuration // ========================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // <o>Number of Semaphore objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // </e> - + // </h> - + // <h>Memory Pool Configuration // ============================ - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // <o>Number of Memory Pool objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // <o>Data Storage Memory size [bytes] <0-1073741824:8> // <i> Defines the combined data storage memory size. // <i> Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // </e> - + // </h> - + // <h>Message Queue Configuration // ============================== - + // <e>Object specific Memory allocation // <i> Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // <o>Number of Message Queue objects <1-1000> // <i> Defines maximum number of objects that can be active at the same time. // <i> Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // <o>Data Storage Memory size [bytes] <0-1073741824:8> // <i> Defines the combined data storage memory size. // <i> Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // </e> - + // </h> - + // <h>Event Recorder Configuration // =============================== - + // <e>Global Initialization // <i> Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // <q>Start recording // <i> Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // <h>Global Event Filter Setup // <i> Initial recording level applied to all components. // <o.0>Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // <h>RTOS Event Filter Setup // <i> Recording levels for RTX components. // <i> Only applicable if events for the respective component are generated. - + // <h>Memory Management // <i> Recording level for Memory Management events. // <o.0>Error events @@ -374,10 +374,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // <h>Kernel // <i> Recording level for Kernel events. // <o.0>Error events @@ -385,10 +385,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // <h>Thread // <i> Recording level for Thread events. // <o.0>Error events @@ -396,10 +396,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // <h>Generic Wait // <i> Recording level for Generic Wait events. // <o.0>Error events @@ -407,10 +407,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // <h>Thread Flags // <i> Recording level for Thread Flags events. // <o.0>Error events @@ -418,10 +418,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // <h>Event Flags // <i> Recording level for Event Flags events. // <o.0>Error events @@ -429,10 +429,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // <h>Timer // <i> Recording level for Timer events. // <o.0>Error events @@ -440,10 +440,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // <h>Mutex // <i> Recording level for Mutex events. // <o.0>Error events @@ -451,10 +451,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // <h>Semaphore // <i> Recording level for Semaphore events. // <o.0>Error events @@ -462,10 +462,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // <h>Memory Pool // <i> Recording level for Memory Pool events. // <o.0>Error events @@ -473,10 +473,10 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // <h>Message Queue // <i> Recording level for Message Queue events. // <o.0>Error events @@ -484,87 +484,87 @@ // <o.2>Operation events // <o.3>Detailed operation events // </h> -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // </h> - + // </e> - + // <h>RTOS Event Generation // <i> Enables event generation for RTX components (requires RTX source variant). - + // <q>Memory Management // <i> Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // <q>Kernel // <i> Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // <q>Thread // <i> Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // <q>Generic Wait // <i> Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // <q>Thread Flags // <i> Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // <q>Event Flags // <i> Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // <q>Timer // <i> Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // <q>Mutex // <i> Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // <q>Semaphore // <i> Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // <q>Memory Pool // <i> Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // <q>Message Queue // <i> Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // </h> - + // </h> - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 78d1b429..62e042d2 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 93dd8379..756e7032 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -86,9 +86,9 @@ void module_manager_entry(ULONG thread_input) { (void)thread_input; - + tx_thread_secure_stack_allocate(&module_manager, 256); - + /* Initialize the module manager. */ txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE); @@ -96,22 +96,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -120,11 +120,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h index c930572b..114b543a 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'sample_threadx_module' - * Target: 'FVP Simulation Model' + * Project: 'sample_threadx_module' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c index e32c4ec6..9a6313ca 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -28,7 +28,7 @@ #define EXTERNAL_MEMORY (0x00200100) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -109,7 +109,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -125,7 +125,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -137,42 +137,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -180,23 +180,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -240,21 +240,21 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + tx_thread_secure_stack_allocate(thread_0, 256); thread_0_counter = func1(thread_0_counter); tx_thread_secure_stack_free(thread_0); - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -302,18 +302,18 @@ UINT status; { /* Test external memory sharing. */ // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -372,7 +372,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -425,7 +425,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f6530c9f..302efdf2 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section RESET - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 3d9b5a60..9e6fa804 100644 --- a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h index 014a2a2b..51ad5ce8 100644 --- a/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'txm' - * Target: 'ThreadX Module Library' + * Project: 'txm' + * Target: 'ThreadX Module Library' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/ac6/inc/txm_module_port.h b/ports_module/cortex_m33/ac6/inc/txm_module_port.h index 40877124..6d9d326f 100644 --- a/ports_module/cortex_m33/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m33/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,15 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -356,6 +348,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S index c596ac24..fd332fe2 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _txm_module_initialize .thumb_func diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c index db345a0f..bf6fcb5f 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -89,16 +90,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -113,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -128,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c index a8ce5c8c..51277114 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c index 15d58661..9752991f 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S index f1733eff..1938ecd0 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S index 63ccc8fc..6f32dfb0 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S index b354238d..e51c087d 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S index b5110d71..1a3e4116 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S index 41e6de04..c80e98a1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 1a3a94e6..707ad4de 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,28 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -542,7 +521,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -648,20 +627,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c index 3f585b78..50b85fa1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index 893135f0..a5fc5eb9 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S index 3b82681b..83f231a1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index 74ac2a29..6ca3be40 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S index a403bb30..17eae110 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S index a4f207a6..68865568 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S index c9c89ad0..06b149ce 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 83487f01..76c52f02 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index becd1da9..6e78d96d 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index d7dd22de..8048fa57 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 8c42b43f..12976ffe 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 0c57bc42..6f0f16e3 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 8c1fbc5f..95336ff5 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c index 19add3d8..de0910d5 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S index a9413251..5f663569 100644 --- a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble @@ -32,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/gnu/inc/txm_module_port.h b/ports_module/cortex_m33/gnu/inc/txm_module_port.h index 37a644d8..c48d5184 100644 --- a/ports_module/cortex_m33/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m33/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -350,6 +343,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c index 9d2e676b..0fa4f2de 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the GNU C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c index 91d90f1f..dc8297c4 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c index 56d9718b..17e7a4da 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S index 49415774..c89394c2 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s index 6adf027c..9ac66244 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s index 01a8f2b0..71d42cde 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s index 082f1af0..b9083160 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s index 779e5a76..c27e7362 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s index dc3d6ad7..506ddf52 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index e392380b..16913f57 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,28 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -541,7 +520,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -647,20 +626,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c index ac0e90a1..82acdfbb 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1509327e..3a59c6e3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S index 11b299f1..7e2e1ea5 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index a78b1eec..92f92809 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s index e7ef020c..370a18da 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s index 6bda9b54..95d8678f 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s index 2611dbf9..8acc0744 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 718fa052..76c52f02 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 4a860702..6e78d96d 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 7bd60c88..8048fa57 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 9be0809a..12976ffe 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c index 1c774a1c..6f0f16e3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index eebe10ad..6c3e0275 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c index 28299f6c..59aee1b9 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s index dbf96b9a..43467f18 100644 --- a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,13 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/iar/inc/txm_module_port.h b/ports_module/cortex_m33/iar/inc/txm_module_port.h index 84c62e1e..c84586b2 100644 --- a/ports_module/cortex_m33/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m33/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -351,6 +344,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c index ac1a3e29..1d2e1720 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c index 91d90f1f..dc8297c4 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c index 56d9718b..17e7a4da 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s index 1f0f001d..3cd737fb 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s index 6cbfd2f6..4456513f 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s index 27acc9bf..ada8e1be 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s index 405bfd1d..8531dde8 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s index 78d4624a..0e8bafdf 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 19fd6738..3b6a61ce 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,29 +69,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -533,7 +511,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -639,20 +617,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c index f2cf79f5..4e4a7803 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 524f6ec3..f70db3d5 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.5 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s index 960a54e1..7a8c0545 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,15 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.5 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 08200cd9..90b22834 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,17 +51,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s index ea318964..820bbc2e 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s index a286567a..d8482053 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s index d79f23c9..d96dbc15 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,13 +68,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 83487f01..76c52f02 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c index becd1da9..6e78d96d 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index d7dd22de..8048fa57 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 8c42b43f..12976ffe 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c index 0c57bc42..6f0f16e3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s index b543af9b..b8387650 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S index e2bdfe26..fb461536 100644 --- a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -130,14 +131,6 @@ Reset_Handler /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -145,14 +138,14 @@ Reset_Handler _tx_initialize_low_level /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ @@ -166,7 +159,7 @@ _tx_initialize_low_level // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -198,7 +191,7 @@ _tx_initialize_low_level /* Return to caller. */ - BX lr + BX lr // } @@ -216,12 +209,12 @@ __user_initial_stackheap /* Define shells for each of the unused vectors. */ EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler // EXPORT __tx_SVCallHandler //__tx_SVCallHandler -// B __tx_SVCallHandler +// B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler @@ -247,7 +240,7 @@ __tx_SysTickHandler BX LR // } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports_module/cortex_m4/ac5/inc/tx_port.h b/ports_module/cortex_m4/ac5/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/ac5/inc/tx_port.h +++ b/ports_module/cortex_m4/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s index c93160a7..2ce68011 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c index 17b178a3..b7bccaa8 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s index de72ba83..f401e147 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s index 572f40a8..16d7536e 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s index c64bac49..f3e273ed 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s index 58191f13..555691e4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s index 0564cfc5..7eb19d65 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s index 3494c7c1..1c82b416 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s index ce5e27db..5d090bbc 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s index b32ebf2e..06d5ccae 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s index 3e66442b..e2682bf3 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 3a7e076f..505706da 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 4fcddbc5..dceea55a 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject index 8e1efcb8..8af62edd 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat index eb8e0c23..1b489e7d 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index e615eedb..ccd76ffb 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject index 0a74f9ff..de727955 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject index f6ece7e0..212b7e51 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index eb8e0c23..1b489e7d 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index eb3e2f3a..4e457588 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,14 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -111,7 +104,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ diff --git a/ports_module/cortex_m4/ac6/example_build/tx/.cproject b/ports_module/cortex_m4/ac6/example_build/tx/.cproject index 945d3c88..8f251099 100644 --- a/ports_module/cortex_m4/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m4/ac6/example_build/txm/.cproject b/ports_module/cortex_m4/ac6/example_build/txm/.cproject index 2ba3d353..ff5b90d7 100644 --- a/ports_module/cortex_m4/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m4/ac6/inc/tx_port.h b/ports_module/cortex_m4/ac6/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/ac6/inc/tx_port.h +++ b/ports_module/cortex_m4/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac6/inc/txm_module_port.h b/ports_module/cortex_m4/ac6/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S index c36f6905..acfcf382 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c index ba187987..e75e693d 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S index d60cf6b8..330789f4 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S index abc0ac5d..a6c1a053 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S index 76b114b8..51b0e3fe 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S index b2fb050d..df262e8c 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S index 47c8f0f9..d3e167bd 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S index 4d52e60c..02431092 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S index 8cdaa034..5ae2c8f7 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S index f75b1e7a..b4348f9d 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S index f1f39c3f..1a52ecda 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4252a96a..aeec8b21 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S +++ b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S index d32562b4..e922a5b5 100644 --- a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -89,18 +82,18 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =__RAM_segment_used_end__ // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =_vectors // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -110,7 +103,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -142,7 +135,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } @@ -169,7 +162,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL <your C Function>.... */ @@ -205,7 +198,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S index 41ea3d71..5f663569 100644 --- a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/gnu/inc/tx_port.h +++ b/ports_module/cortex_m4/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/gnu/inc/txm_module_port.h b/ports_module/cortex_m4/gnu/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m4/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c index d751fc01..30632c1e 100644 --- a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S index af374956..85b1ee2a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S index 0728d86e..9c0f547a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 38790a85..55791677 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S index e0ae359a..56c4c4bc 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S index 32839c40..9d2ba7b0 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S index 734b64e7..a5a80868 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S index c62ccf30..0b26d993 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S index 234a2121..8c4a09fd 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S index 4d0c8003..6a14a673 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 3803b716..9c6b12e6 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/iar/example_build/cstartup_M.s b/ports_module/cortex_m4/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m4/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m4/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx.c b/ports_module/cortex_m4/iar/example_build/sample_threadx.c index 60f5a3d3..55b63731 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -101,41 +101,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -262,11 +262,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -325,7 +325,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -378,7 +378,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c index aea2c0b1..f925b527 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m4/iar/example_build/startup.s b/ports_module/cortex_m4/iar/example_build/startup.s index ba46e572..feddd8b4 100644 --- a/ports_module/cortex_m4/iar/example_build/startup.s +++ b/ports_module/cortex_m4/iar/example_build/startup.s @@ -7,7 +7,7 @@ ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -68,86 +68,86 @@ __vector_table DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU @@ -218,47 +218,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -267,363 +267,363 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT(2) -FPU_IRQHandler + SECTION .text:CODE:NOROOT(2) +FPU_IRQHandler B FPU_IRQHandler END diff --git a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s index 625fa222..07afc829 100644 --- a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -29,11 +30,11 @@ SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 SECTION `.text`:CODE:NOROOT(2) THUMB @@ -70,15 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,7 +78,7 @@ __tx_free_memory_start _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ @@ -96,7 +88,7 @@ _tx_initialize_low_level: STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =__vector_table // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -106,7 +98,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -138,7 +130,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } PUBLIC SysTick_Handler diff --git a/ports_module/cortex_m4/iar/inc/tx_port.h b/ports_module/cortex_m4/iar/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/iar/inc/tx_port.h +++ b/ports_module/cortex_m4/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/iar/inc/txm_module_port.h b/ports_module/cortex_m4/iar/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m4/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c index 70b4e83a..5d7767ae 100644 --- a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s index ff4f11e0..d0033b5b 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s index c26d32c5..f1291fec 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s index b72bbad3..e0e028c8 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s index 4002679f..00dab2e2 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s index b9093f8a..cf834228 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s index e618cb7f..b6a8c277 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s index 01213848..a80261c2 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s index 3260e917..4f8b9870 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s index 72cc4f61..fbf9c2ab 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 78dfa784..fab79337 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S index 2ab33a98..62d7eb93 100644 --- a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -130,14 +131,6 @@ Reset_Handler /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -145,14 +138,14 @@ Reset_Handler _tx_initialize_low_level /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ @@ -166,7 +159,7 @@ _tx_initialize_low_level // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -198,7 +191,7 @@ _tx_initialize_low_level /* Return to caller. */ - BX lr + BX lr // } @@ -216,12 +209,12 @@ __user_initial_stackheap /* Define shells for each of the unused vectors. */ EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler // EXPORT __tx_SVCallHandler //__tx_SVCallHandler -// B __tx_SVCallHandler +// B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler @@ -247,7 +240,7 @@ __tx_SysTickHandler BX LR // } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s index 1c0b602d..0dc2b736 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c index 8725edcf..48f5b3a8 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s index 5e826e21..0fb0e6c9 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s index 0445f04c..12b27e73 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s index 13ad3b6f..760396b3 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s index f3268762..02506666 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s index b51e9997..1b099aa2 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s index d65a873a..1810905a 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s index 6f0a830f..d54a8486 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s index 98ac59de..ed7165df 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s index ea6286b8..f2393840 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 66398049..aba38988 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 7d1d9ba1..9f9b6967 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject index fc1cb75e..a8cd64d6 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat index 8b4bb5bd..8be90bfd 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index fd9f4f76..2837a142 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject index 1e1ea739..0db37787 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - 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+ <resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + </cproject> diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject index f6ca2712..c8bb89b5 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,174 +1,174 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="" valueType="string"/> - + <option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/> - + <option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/> - + <option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.346291361" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" valueType="libs"> - + <listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/> - + </option> - + </tool> - + <tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/> - + </toolChain> - + </folderInfo> - + <sourceEntries> - + <entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> - + </sourceEntries> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - + </cconfiguration> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/> - + </cproject> diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index 8b4bb5bd..8be90bfd 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 44d7a30d..2df350e5 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,14 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -111,7 +104,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ diff --git a/ports_module/cortex_m7/ac6/example_build/tx/.cproject b/ports_module/cortex_m7/ac6/example_build/tx/.cproject index 5115080e..ec8102e7 100644 --- a/ports_module/cortex_m7/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m7/ac6/example_build/txm/.cproject b/ports_module/cortex_m7/ac6/example_build/txm/.cproject index 02c85d5a..78fcedcb 100644 --- a/ports_module/cortex_m7/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base"> - + <folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath=""> - + <toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6"> - 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+ <builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1164059605" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/> - + <tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6"> - + <option id="com.arm.tool.c.compiler.v6.base.option.target.775437314" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/> - + <option id="com.arm.tool.c.compiler.v6.base.option.cpu.957518664" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m7" valueType="string"/> - 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+ </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/> - + </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac6/inc/txm_module_port.h b/ports_module/cortex_m7/ac6/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S index 37f25b0e..7fb2e60f 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c index 98302d79..bd3c0c7c 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S index 003bf20d..9ecbaa0c 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S index a88957cc..1fab2a9b 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S index ddd46eb5..a10c760a 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S index f58e63d0..ea8bfd4d 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S index d195b3ff..7ea62177 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index a07d64f7..a3126bc7 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S index fd1aa689..0fd0dc46 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index 57262ceb..831c00e4 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S index 86f2a7f3..a2f1a438 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4c9a10dd..f18b5ef1 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s b/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s +++ b/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits -
\ No newline at end of file diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 1a1ca0de..e9273cbd 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -89,18 +82,18 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =__RAM_segment_used_end__ // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =_vectors // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -110,7 +103,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -142,7 +135,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } @@ -169,7 +162,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL <your C Function>.... */ @@ -205,7 +198,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S index 41ea3d71..5f663569 100644 --- a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c index 01f7c7c5..3eb08b2b 100644 --- a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S index 57b18cf6..63895928 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S index d118c5bd..96df9ac5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S index 62301c14..5778d8d4 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S index f74a3748..19f6f854 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S index f4be7eba..25f1aac3 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index 46013061..571af2ee 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S index 0c72a44f..d0e2eaf3 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index 4987b047..ce5a3f46 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S index d9477dea..6cc18b25 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index b6c11663..44b86df5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/iar/example_build/cstartup_M.s b/ports_module/cortex_m7/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m7/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m7/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx.c b/ports_module/cortex_m7/iar/example_build/sample_threadx.c index 9a626828..f1f4cb87 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -65,7 +65,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -93,41 +93,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -135,23 +135,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -254,11 +254,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -317,7 +317,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -370,7 +370,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c index 34b97d86..7e561048 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,18 +291,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)0x90000000 = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -361,7 +361,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -414,7 +414,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf index bffaf30d..9b98d2de 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c index de3999d9..9fc56315 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x90000000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x90000000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m7/iar/example_build/startup.s b/ports_module/cortex_m7/iar/example_build/startup.s index b1d725f7..a866a4cd 100644 --- a/ports_module/cortex_m7/iar/example_build/startup.s +++ b/ports_module/cortex_m7/iar/example_build/startup.s @@ -7,14 +7,14 @@ ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M7 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** -;* +;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, @@ -36,7 +36,7 @@ ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* +;* ;******************************************************************************* ; ; @@ -87,86 +87,86 @@ __vector_table DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -182,8 +182,8 @@ __vector_table DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; @@ -244,47 +244,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -293,438 +293,438 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s index 9789421b..2df2d19f 100644 --- a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -29,11 +30,11 @@ SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 SECTION `.text`:CODE:NOROOT(2) THUMB @@ -70,15 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,7 +78,7 @@ __tx_free_memory_start _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ @@ -96,7 +88,7 @@ _tx_initialize_low_level: STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =__vector_table // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -106,7 +98,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -138,7 +130,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } PUBLIC SysTick_Handler diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c index 8d024757..c858fb2b 100644 --- a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s index 52c33328..ccc96ede 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s index f3bca66a..dcf510a6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s index 8950acd5..f28d5bde 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s index 76e09a1c..36aaaf0a 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s index 57102c6d..55aa1d62 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index 1f9229ca..d38c8df7 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s index 04b1479c..2f7ac3ab 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s index 51c85491..0cef80c6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s index 1da9431e..775c0a45 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 2893050b..3ee7dd32 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject index 71818fd9..4ceb8982 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - + <cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1352491235"> - + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1352491235" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - + <externalSettings/> - + <extensions> - + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/> - + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> - + </extensions> - + </storageModule> - + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> - + <configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1352491235" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c index 4a677059..f8e0cecc 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -58,7 +58,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Setup the timer. */ timer_init(); @@ -85,42 +85,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 8732358f..44591770 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -103,12 +104,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject index ee2634f6..68b87b4b 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index feb9fb84..74eeb454 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -102,7 +102,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -118,7 +118,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -130,14 +130,14 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, @@ -157,14 +157,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -173,7 +173,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -181,14 +181,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -236,7 +236,7 @@ UINT status; /* Test external/shared memory. */ *(ULONG *) 0x08025000 = 0xdeadbeef; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -246,7 +246,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -298,11 +298,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -361,7 +361,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -414,7 +414,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c index 29268630..80e5f04f 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c @@ -9,17 +9,17 @@ void use_no_semihosting(void) __asm(".global __use_no_semihosting\n\t"); } #endif - + char *$Sub$$_sys_command_string(char *cmd, int len) { return 0; } - + __attribute__((noreturn)) void $Sub$$_sys_exit(int return_code) { while(1); } - + __attribute__((noreturn)) int $Sub$$__raise(int signal, int type) { while(1); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject index 71818fd9..4ceb8982 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,170 +1,170 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ </storageModule> - + <storageModule moduleId="scannerConfiguration"> - + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/sample_threadx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c index 6a92a2ac..78dc1538 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c @@ -1,4 +1,4 @@ -/* +/* Input ELF file: sample_threadx_module.axf Output C Array file: module_code.c */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index 926647b2..9eb35ca0 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -18,21 +18,21 @@ SDRAM 0x0 0x40000000 * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } - + IRQ_STACK +0 ALIGN 8 EMPTY 1024 {} - + FIQ_STACK +0 ALIGN 8 EMPTY 512 {} - + SVC_STACK +0 ALIGN 8 EMPTY 2048 {} - + SYS_STACK +0 ALIGN 8 EMPTY 2048 {} - + ABORT_STACK +0 ALIGN 8 EMPTY 2048 {} ; Application RW & ZI data (.data & .bss) DATA +0 0x100000 { - * (+RW,+ZI) + * (+RW,+ZI) } PERIPHERALS 0xA0000000 EMPTY 0x20000000 { }; Peripherals diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 99e8fa3e..2e683da2 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -47,7 +47,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Setup the timer. */ timer_init(); @@ -60,8 +60,8 @@ int main() void tx_application_define(void *first_unused_memory) { - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -72,7 +72,7 @@ void tx_application_define(void *first_unused_memory) void module_manager_entry(ULONG thread_input) { - + /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); @@ -80,40 +80,40 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000 /*module_code*/); - + /* Enable 128 byte read/write shared memory region at 0x08025000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(300); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Set maximum module priority to 5. */ txm_module_manager_maximum_module_priority_set(&my_module, 5); - /* In this demo, module threads 0 and 5 will not start because their priorities + /* In this demo, module threads 0 and 5 will not start because their priorities * are higher than 5. */ - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S index cd6479d3..bbd85a4c 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S @@ -3,7 +3,7 @@ // // Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. //---------------------------------------------------------------- @@ -130,7 +130,7 @@ Reset_Handler: CPS #SVC_MODE // Build SVC mode CPSR LDR sp, =Image$$SVC_STACK$$ZI$$Limit // Setup SVC stack pointer - + //---------------------------------------------------------------- // TCM Configuration @@ -196,7 +196,7 @@ Reset_Handler: // Enable Branch prediction //---------------------------------------------------------------- -// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. +// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. // Some control bits in the ACTLR control the program flow and prefetch features instead. // These are enabled by default, but are shown here for completeness. diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 8732358f..44591770 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -103,12 +104,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/example_build/tx/.cproject b/ports_module/cortex_r4/ac6/example_build/tx/.cproject index 9dfee32b..e97c3b82 100644 --- a/ports_module/cortex_r4/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/tx/.cproject @@ -1,164 +1,164 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - 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+ <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/tx"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + </cproject> diff --git a/ports_module/cortex_r4/ac6/example_build/txm/.cproject b/ports_module/cortex_r4/ac6/example_build/txm/.cproject index f9012e60..1e87101d 100644 --- a/ports_module/cortex_r4/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/txm/.cproject @@ -1,176 +1,176 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - + <storageModule moduleId="org.eclipse.cdt.core.settings"> - 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+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> - + <storageModule moduleId="refreshScope" versionNumber="2"> - + <configuration configurationName="Debug"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + <configuration configurationName="Release"> - + <resource resourceType="PROJECT" workspacePath="/txm"/> - + </configuration> - + </storageModule> - + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> - + <storageModule moduleId="com.arm.projectSettings" version="6.0.0"/> - + </cproject> diff --git a/ports_module/cortex_r4/ac6/inc/tx_port.h b/ports_module/cortex_r4/ac6/inc/tx_port.h index 33b7e737..2b334d2e 100644 --- a/ports_module/cortex_r4/ac6/inc/tx_port.h +++ b/ports_module/cortex_r4/ac6/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/AC6 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/AC6 */ /* 6.1 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +70,7 @@ #include <string.h> -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +106,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +121,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +169,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,11 +181,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -207,7 +199,7 @@ typedef unsigned short USHORT; VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -225,11 +217,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -237,8 +229,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -265,21 +257,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -299,7 +291,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -308,7 +300,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -344,8 +336,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_r4/ac6/inc/txm_module_port.h b/ports_module/cortex_r4/ac6/inc/txm_module_port.h index 3e6ec271..141a307b 100644 --- a/ports_module/cortex_r4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_r4/ac6/inc/txm_module_port.h @@ -1,52 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-R4/MPU/ARM */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -89,9 +84,9 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 1024 #endif -/* Defined, these options allows a memory-protected module to access kernel objects. - For example, when a module needs to send/receive a message from a kernel queue. - This does not allow modules to create or delete objects outside of their memory. +/* Defined, these options allows a memory-protected module to access kernel objects. + For example, when a module needs to send/receive a message from a kernel queue. + This does not allow modules to create or delete objects outside of their memory. Default setting for these values is undefined. */ /* #define TXM_MODULE_ENABLE_KERNEL_BLOCK_POOL_ACCESS */ /* #define TXM_MODULE_ENABLE_KERNEL_BYTE_POOL_ACCESS */ @@ -166,7 +161,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access to the kernel entry function, thus 11 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 12 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -234,7 +229,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the module properties. */ @@ -248,7 +243,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { \ _tx_mutex_put(&_txm_module_manager_mutex); \ return(TXM_MODULE_INVALID_PROPERTIES); \ - } + } /* Define the macro to check the code alignment. */ @@ -359,7 +354,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/ARM Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/ARM Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S index 051f6f66..f4a16554 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -43,43 +43,37 @@ .eabi_attribute Tag_ABI_PCS_R9_use, 1 .eabi_attribute Tag_ABI_PCS_RW_data, 2 .arm -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_initialize Cortex-R4/MPU/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function initializes the module c runtime. */ -/* */ -/* INPUT */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ /* heap_base Pointer to bottom of heap */ /* heap_top Pointer to top of heap */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ /* __scatterload Initialize C runtime */ /* __rt_lib_init Initialize heap */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ /* */ /**************************************************************************/ /* VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top) */ @@ -88,7 +82,7 @@ _txm_module_initialize: PUSH {r0-r12,lr} // Save dregs and LR - + B __scatterload // Call ARM func to initialize variables diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c index b2673994..ec0d81c6 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S index f87614c4..eaf3be37 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,12 @@ #endif .text .eabi_attribute Tag_ABI_align_preserved, 1 - + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-R4/MPU/ARM */ +/* _tx_thread_context_restore Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ @@ -89,12 +90,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ @@ -186,10 +181,10 @@ __tx_thread_preempt_restore: STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save registers MOV r4, r3 // Save SPSR in r4 - + CPS #IRQ_MODE // Switch back to IRQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SYS_MODE // Switch to SYS mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S index 696dc985..68951b08 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S index 94c20b72..7fbcc84a 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_restore(VOID) */ /* { */ @@ -186,15 +181,15 @@ __tx_thread_fiq_preempt_restore: LDMIA sp!, {r3, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - + CPS #SVC_MODE // Switch to SVC mode to save context on thread stack STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - + CPS #FIQ_MODE // Switch back to FIQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SVC_MODE // Switch to SVC mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S index 1d85abe5..3c1333b3 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_save(VOID) */ /* { */ @@ -90,7 +85,7 @@ .type _tx_thread_fiq_context_save, "function" _tx_thread_fiq_context_save: - /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked out, we are in IRQ mode, and all registers are intact. */ /* Check for a nested interrupt condition. */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S index df8a4633..5abbdddf 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_end(VOID) */ /* { */ @@ -90,13 +85,13 @@ .type _tx_thread_fiq_nesting_end, "function" _tx_thread_fiq_nesting_end: MOV r3, lr // Save ISR return address - + #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable IRQ and FIQ interrupts #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #FIQ_MODE // Switch back to FIQ mode diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S index f26d9a0c..73564d78 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_start(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S index 11ab4e4f..83aa06c4 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S index cd7476a6..d605e034 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S index 8e966de6..f9315d7f 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S index cf8e0ac1..664e02c5 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_end(VOID) */ /* { */ @@ -96,7 +91,7 @@ _tx_thread_irq_nesting_end: #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #IRQ_MODE // Switch back to IRQ mode diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S index b3ebe405..1d50b484 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_start(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S index 58b94d01..38792e97 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S index eb8e9a90..8f122083 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,12 +79,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S index 2c5f11d6..048b4525 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S index de49cc0d..dbb40aba 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,12 +76,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_vectored_context_save(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S index d48313ef..8c3abf90 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -84,12 +85,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 4572adab..94a6cfdd 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index a57590fa..2bd00d08 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 9962938d..1844c760 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index d9ff9c7a..28439101 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 8c9b8752..ea4ce4ff 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -519,7 +514,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4f9daad8..26bf9d51 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S index 7f23c553..f36ee23f 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -22,7 +23,7 @@ .global _txm_module_manager_kernel_dispatch .global _txm_system_mode_enter .global _txm_system_mode_exit - + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -54,12 +55,6 @@ /* */ /* Modules in user mode */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ .text .align 12 diff --git a/ports_module/cortex_r4/iar/example_build/cstartup.s b/ports_module/cortex_r4/iar/example_build/cstartup.s index 6953baa8..c01a67cb 100644 --- a/ports_module/cortex_r4/iar/example_build/cstartup.s +++ b/ports_module/cortex_r4/iar/example_build/cstartup.s @@ -136,19 +136,19 @@ __iar_program_start: MSR cpsr_c, r0 ; Change the mode LDR r1, =SFE(FIQ_STACK) ; End of FIQ_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the SVC stack pointer. CPS #SVC_MODE LDR r1, =SFE(SVC_STACK) ; End of SVC_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the abort stack pointer. CPS #ABT_MODE LDR r1, =SFE(ABT_STACK) ; End of ABT_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the normal stack pointer. BIC r0 ,r0, #MODE_MSK ; Clear the mode bits diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx.c b/ports_module/cortex_r4/iar/example_build/sample_threadx.c index 983109cc..ca92ff86 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -87,42 +87,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -249,11 +249,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -312,7 +312,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -365,7 +365,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c index 203cbba2..d4f98a30 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -263,7 +263,7 @@ UINT status; /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -289,18 +289,18 @@ UINT status; /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -354,12 +354,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf index bed79adf..69c8f600 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c index 8c319878..a0ec49ea 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c @@ -40,7 +40,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -50,8 +50,8 @@ int main() void tx_application_define(void *first_unused_memory) { - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -62,7 +62,7 @@ void tx_application_define(void *first_unused_memory) void module_manager_entry(ULONG thread_input) { - + /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) 0x08020000, 0x10000); @@ -70,35 +70,35 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Enable 128 byte read/write shared memory region at 0x08025000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(300); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s index b65b7a82..dd82541b 100644 --- a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -55,7 +55,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit (5) of CPSR/SPSR ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -68,45 +68,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -117,7 +111,7 @@ __tx_free_memory_start _tx_initialize_low_level ; ; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ -; +; ; /* For modules, stay in SYS mode and disable interrupts. */ CPSID i ; @@ -133,7 +127,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -166,17 +160,17 @@ IRQ_Handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -191,7 +185,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -210,22 +204,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -234,7 +228,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -250,41 +244,41 @@ __tx_irq_processing_return __tx_fiq_handler B __tx_fiq_handler ; FIQ interrupt handler ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MPU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MPU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -300,7 +294,7 @@ __tx_fiq_handler EXTERN _txm_module_manager_memory_fault_handler EXTERN _tx_execution_thread_exit EXTERN _tx_thread_schedule - + RSEG .text:CODE:NOROOT(2) PUBLIC Prefetch_Handler PUBLIC Abort_Handler @@ -323,15 +317,15 @@ Abort_Handler LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address LDR r1, [r0] ; Pickup the current thread pointer STR r1, [r3, #0] ; Save current thread pointer - + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR STR r0, [r3, #8] ; Save DFAR - + CMP r0, #0 ; Was it a data or instruction fault? SUBEQ lr, lr, #4 ; Adjust point of exception for instruction SUBNE lr, lr, #8 ; Adjust point of exception for data STR lr, [r3, #4] ; Save point of fault - + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR STR r0, [r3, #12] ; Save DFSR MRC p15, 0, r0, c6, c0, 2 ; Read IFAR @@ -343,7 +337,7 @@ Abort_Handler MCR p15, 0, r0, c5, c0, 0 ; Clear DFSR MCR p15, 0, r0, c6, c0, 2 ; Clear IFAR MCR p15, 0, r0, c5, c0, 1 ; Clear IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -360,7 +354,7 @@ Abort_Handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -372,7 +366,7 @@ Abort_Handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -387,11 +381,11 @@ Abort_Handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s index 31ccca5b..9b4f1122 100644 --- a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s @@ -26,7 +26,7 @@ __txm_module_preamble: DC32 0x6 ; Module Major Version DC32 0x1 ; Module Minor Version DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) + DC32 0x12345678 ; Module ID (application defined) DC32 0x00000001 ; Module Properties where: ; Bits 31-24: Compiler ID ; 0 -> IAR @@ -37,23 +37,23 @@ __txm_module_preamble: ; 1 -> User mode execution (MPU protection) DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point DC32 1 ; Module Start/Stop Thread Priority DC32 1022 ; Module Start/Stop Thread Stack Size DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size DC32 ROPI$$Length ; Module Code Size DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 + DC32 0 ; Reserved 0 DC32 0 ; Reserved 1 DC32 0 ; Reserved 2 DC32 0 ; Reserved 3 DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 DC32 0 ; Reserved 9 DC32 0 ; Reserved 10 DC32 0 ; Reserved 11 diff --git a/ports_module/cortex_r4/iar/inc/tx_port.h b/ports_module/cortex_r4/iar/inc/tx_port.h index 35f50af7..ae9421c8 100644 --- a/ports_module/cortex_r4/iar/inc/tx_port.h +++ b/ports_module/cortex_r4/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,19 +107,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -172,7 +164,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,11 +178,11 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ @@ -221,7 +213,7 @@ ULONG _tx_misra_time_stamp_get(VOID); ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -239,11 +231,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -253,23 +245,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -297,8 +289,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -309,22 +301,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -393,8 +385,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_r4/iar/inc/txm_module_port.h b/ports_module/cortex_r4/iar/inc/txm_module_port.h index a4014a7f..9cb72c16 100644 --- a/ports_module/cortex_r4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_r4/iar/inc/txm_module_port.h @@ -1,45 +1,40 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ @@ -51,13 +46,13 @@ #ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in txm_module_user.h. The defines in this file may +/* Yes, include the user defines in txm_module_user.h. The defines in this file may alternately be defined on the command line. */ #include "txm_module_user.h" #endif -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -162,7 +157,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access to the kernel entry function, thus 11 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 12 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -230,7 +225,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -340,7 +335,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c index 42ae543c..b27e06e3 100644 --- a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c b/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and <yvals.h> is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include <yvals.h> #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s index 5234d948..699cfd78 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; @@ -38,44 +38,38 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -103,13 +97,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -169,10 +163,10 @@ __tx_thread_preempt_restore LDMIA sp!, {r0-r3} ; Recover r0-r3 CPS #SYS_MODE ; Enter SYS mode STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack - + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -182,7 +176,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s index d8aa33a1..9589e706 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_system_state @@ -26,43 +26,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -79,7 +73,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -94,7 +88,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -110,7 +104,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -124,13 +118,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -150,7 +144,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -160,7 +154,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -175,7 +169,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s index a6fbb0f8..3eb61e11 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,65 +1,59 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; INT_MASK DEFINE 0x80 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -79,7 +73,7 @@ _tx_thread_interrupt_control ; MSR CPSR_cxsf, r1 ; Setup new CPSR AND r0, r3, #INT_MASK ; Return previous interrupt mask - + BX lr ; Return to caller ; ;} diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s index 7f9a2b2c..c05493d7 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,64 +1,58 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s index f862c87d..b1ab3f05 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,61 +1,55 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring interrupts to the state */ -;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s index 85c03c5f..b45a8768 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,73 +1,67 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; IRQ_MODE DEFINE 0x12 ; IRQ mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s index 97bc7029..0fd2c949 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,70 +1,64 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; SYS_MODE DEFINE 0x1F ; System mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s index 72270475..b6bcdfa2 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_execute_ptr @@ -36,45 +36,39 @@ SYS_MODE EQU 0x1F ; SYS mode MODE_MASK EQU 0x1F ; Mode mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -121,7 +115,7 @@ SWI_Handler ; ; The service call is handled here ; - + CMP r0, #0 ; Is it a schedule request? BEQ _tx_handler_svc_schedule ; Yes, go there @@ -130,7 +124,7 @@ SWI_Handler CMP r0, #2 ; Is it a system mode exit request? BEQ _tx_handler_svc_super_exit ; Yes, go there - + LDR r2, =0x123456 CMP r0, r2 ; Is it an ARM request? BEQ _tx_handler_svc_arm ; Yes, go there @@ -148,11 +142,11 @@ _tx_handler_svc_unrecognized_loop ; We should never get here ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 1, which means we are entering + ; At this point we have an SVC 1, which means we are entering ; supervisor mode to service a kernel call. _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) - LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -162,13 +156,13 @@ _tx_handler_svc_super_enter LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread - + ; Now we enter the system mode and return LDMFD sp!, {r0, r3} ; Get spsr from the stack BIC r0, r0, #MODE_MASK ; clear mode field ORR r0, r0, #SYS_MODE ; system mode code MSR SPSR_cxsf, r0 ; Restore the spsr - + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer CPS #SYS_MODE ; Switch to SYS mode MOV r3, sp ; Grab thread stack pointer @@ -182,15 +176,15 @@ _tx_handler_svc_super_enter STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 2, which means we are exiting + ; At this point we have an SVC 2, which means we are exiting ; supervisor mode after servicing a kernel call. _tx_handler_svc_super_exit ; Make sure that we have been called from the system mode exit location (security) - LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -218,19 +212,19 @@ _tx_handler_svc_super_exit STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; just return LDMFD sp!, {r0, r3} ; Get spsr from the stack MSR SPSR_cxsf, r0 ; Restore the spsr LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -239,10 +233,10 @@ _tx_handler_svc_schedule LDMFD sp!, {r0, r3} ; Get spsr from stack MSR SPSR_cxsf, r0 ; Restore spsr - LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -262,7 +256,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -319,7 +313,7 @@ __tx_thread_schedule_loop MRC p15, 0, r3, c6, c1, 0 ; Read DRBAR into r3 CMP r2, r3 ; Is module already loaded? BEQ _tx_end_mpu_update ; Yes - skip memory protection setup - + ; Disable MPU before applying new regions. MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR BIC r2, r2, #1 ; Disable MPU @@ -343,7 +337,7 @@ _tx_mpu_loop ADD r3, r3, #1 ; Increment loop index CMP r3, #0xB ; Check the limit BLE _tx_mpu_loop ; Loop if not finished - + ; Enable MPU with new regions. MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR ORR r2, r2, #1 ; Enable MPU @@ -351,18 +345,18 @@ _tx_mpu_loop DSB MCR p15, 0, r2, c1, c0, 0 ; Write to SCTLR ISB - ; + ; _tx_end_mpu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return - + MSR SPSR_cxsf, r5 ; Setup SPSR for return LDR r1, [r0, #8] ; Get thread SP LDR lr, [r1, #0x40] ; Get thread PC CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -375,7 +369,7 @@ _tx_end_mpu_update CPS #SYS_MODE ; Enter SYS mode _tx_skip_interrupt_vfp_restore #endif - + LDMIA sp!, {r0-r12, lr} ; Restore registers ADD sp, sp, #4 ; Fix stack pointer CPS #SVC_MODE ; Enter SVC mode @@ -384,7 +378,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -394,7 +388,7 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore #endif - + LDMIA sp!, {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode @@ -404,11 +398,11 @@ _tx_skip_solicited_vfp_restore ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; End SWI_Handler ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - + #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts @@ -424,7 +418,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s index 502c3529..1708ede4 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s @@ -1,81 +1,75 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; SYS_MODE DEFINE 0x1F ; SYS mode CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + ARM _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s index af808d42..f9d4c9e3 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_current_ptr @@ -27,44 +27,38 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -97,7 +91,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s index d5f077b2..2f075445 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_system_state @@ -25,43 +25,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -118,7 +112,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -150,7 +144,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s index 5d4efcd8..7213e213 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;Define Assembly language external references... @@ -34,46 +34,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -99,7 +93,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -217,13 +211,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 50e0c672..9876d72f 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,42 +26,36 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_power_of_two_block_size Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates a power of two size at or immediately above*/ -/* the input size and returns it to the caller. */ -/* */ -/* INPUT */ -/* */ -/* size Block size */ -/* */ -/* OUTPUT */ -/* */ -/* calculated size Rounded up to power of two */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -68,11 +63,11 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,58 +77,58 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* module_preamble Pointer to module preamble */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_power_of_two_block_size Calculate power of two size */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, - ULONG *code_size, - ULONG *code_alignment, - ULONG *data_size, +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, ULONG *data_alignment) { @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,9 +170,9 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ - *code_size = local_code_size; + *code_size = local_code_size; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 5b61abb8..4f9ced4c 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index ea6c2022..e468e239 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 5653ee37..21b4a4da 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 365f2e2d..e8e28bc7 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -514,7 +509,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index a2aa765a..9e0efc28 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; THUMB_MASK DEFINE 0x20 ; THUMB bit @@ -26,44 +26,38 @@ SYS_MODE DEFINE 0x1F ; SYS mode CPSR_MASK DEFINE 0xBF ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -76,7 +70,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s index 263a13cb..07d81f95 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,60 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; EXTERN _tx_thread_current_ptr EXTERN _txm_module_manager_kernel_dispatch - - + + RSEG .text:CODE:NOROOT(5) ARM -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ PUBLIC _txm_module_manager_user_mode_entry @@ -85,5 +79,5 @@ _txm_system_mode_exit NOP NOP _txm_module_manager_user_mode_end - + END diff --git a/ports_module/rxv2/iar/example_build/hwsetup.c b/ports_module/rxv2/iar/example_build/hwsetup.c index ab3e3bac..c03895a5 100644 --- a/ports_module/rxv2/iar/example_build/hwsetup.c +++ b/ports_module/rxv2/iar/example_build/hwsetup.c @@ -1,25 +1,25 @@ /* Adapted for use with IAR Embedded Workbench */ /*********************************************************************************************************************** * DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No -* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM -* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES -* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of -* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: -* http://www.renesas.com/disclaimer +* http://www.renesas.com/disclaimer * -* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : hwsetup.c -* Version : 1.0 +* Version : 1.0 * Device(s) : RX * H/W Platform : RX65N * Description : Defines the initialisation routines used each time the MCU is restarted. @@ -83,34 +83,34 @@ void operating_frequency_set(void) Peripheral Clock Frequency....... 48 MHz USB Clock Frequency.............. 48 MHz External Bus Clock Frequency..... 24 MHz */ - + volatile unsigned int i; - + /* Protect off. */ SYSTEM.PRCR.WORD = 0xA50B; - + /* Uncomment if not using sub-clock */ //SYSTEM.SOSCCR.BYTE = 0x01; /* stop sub-clock */ SYSTEM.SOSCCR.BYTE = 0x00; /* Enable sub-clock for RTC */ - + /* Wait 131,072 cycles * 12 MHz = 10.9 ms */ SYSTEM.MOSCWTCR.BYTE = 0x0D; - + /* x16 @PLL, 2 divisor */ SYSTEM.PLLCR.WORD = 0x0F01; - + /* EXTAL ON */ SYSTEM.MOSCCR.BYTE = 0x00; - + /* PLL ON */ SYSTEM.PLLCR2.BYTE = 0x00; - + for(i = 0;i< 0x168;i++) { /* Wait over 12ms */ __no_operation(); } - + /* Setup system clocks SCKCR - System Clock Control Register b31:b28 FCK[3:0] 0x02 = Flash clock: PLL/4 = (192 / 4) = 48 MHz @@ -120,17 +120,17 @@ void operating_frequency_set(void) b11:b8 PCKB[3:0] 0x02 = Peripheral clock B: PLL/4 = 48 MHz */ SYSTEM.SCKCR.LONG = 0x21031222; /* ICK=PLL/2,BCK,FCK,PCK=PLL/4 */ - + /* Setup IEBUS and USB clocks - SCKCR2 - System Clock Control Register 2 + SCKCR2 - System Clock Control Register 2 b7:b4 UCK[3:0] 0x03 = USB clock is PLL/4 = 48 MHz b3:b0 IEBCK[3:0] 0x01 = IE Bus clock is PLL/2 = 96 MHz */ SYSTEM.SCKCR2.WORD = 0x0031; - + /* ICLK, PCLKB, FCLK, BCLK, IECLK, and USBCLK all come from PLL circuit */ SYSTEM.SCKCR3.WORD = 0x0400; - + /* Protect on. */ SYSTEM.PRCR.WORD = 0xA500; } @@ -146,7 +146,7 @@ void interrupts_configure(void) { /* Protect off. */ SYSTEM.PRCR.WORD = 0xA50B; - + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory. */ @@ -154,9 +154,9 @@ void interrupts_configure(void) IR(BSC,BUSERR) = 0; /* Make this the highest priority interrupt (adjust as necessary for your application) */ - IPR(BSC,BUSERR) = 0x0F; + IPR(BSC,BUSERR) = 0x0F; /* Enable the interrupt in the ICU */ - IEN(BSC,BUSERR) = 1; + IEN(BSC,BUSERR) = 1; /* Enable illegal address interrupt in the BSC */ BSC.BEREN.BIT.IGAEN = 1; } @@ -167,11 +167,11 @@ void interrupts_configure(void) * Description : Sample ISR for bus error (must do hardware setup first!) * By default, this demo code enables the Bus Error Interrupt. * This interrupt will fire if the user tries to access code -* or data from one of the reserved areas in the memory map, +* or data from one of the reserved areas in the memory map, * including the areas covered by disabled chip selects. * A nop statement is included here as a convenient place * to set a breakpoint during debugging and development, and -* further handling should be added by the user for their +* further handling should be added by the user for their * application. * Arguments : none * Return value : none @@ -183,7 +183,7 @@ __interrupt void buserr_isr(void) the register BSC.BERSR2.WORD. The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units). */ - + /* Add your own code here to handle this interrupt */ __no_operation(); } diff --git a/ports_module/rxv2/iar/example_build/hwsetup.h b/ports_module/rxv2/iar/example_build/hwsetup.h index d2bae5f6..5ff001c0 100644 --- a/ports_module/rxv2/iar/example_build/hwsetup.h +++ b/ports_module/rxv2/iar/example_build/hwsetup.h @@ -1,25 +1,25 @@ /* Adapted for use with IAR Embedded Workbench */ /*********************************************************************************************************************** * DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No -* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM -* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES -* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of -* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: -* http://www.renesas.com/disclaimer +* http://www.renesas.com/disclaimer * -* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : hwsetup.h -* Version : 1.0 +* Version : 1.0 * Description : Hardware setup header file.. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ports_module/rxv2/iar/example_build/low_level_init.c b/ports_module/rxv2/iar/example_build/low_level_init.c index 5b89a40a..95069278 100644 --- a/ports_module/rxv2/iar/example_build/low_level_init.c +++ b/ports_module/rxv2/iar/example_build/low_level_init.c @@ -31,7 +31,7 @@ __intrinsic int __low_level_init ( void ) { hardware_setup(); - + /*==================================*/ /* Choose if segment initialization */ /* should be done or not. */ diff --git a/ports_module/rxv2/iar/example_build/sample_module_linker.icf b/ports_module/rxv2/iar/example_build/sample_module_linker.icf index b6187731..d37c93f1 100644 --- a/ports_module/rxv2/iar/example_build/sample_module_linker.icf +++ b/ports_module/rxv2/iar/example_build/sample_module_linker.icf @@ -60,10 +60,10 @@ define block HEAP with alignment = 4, size = _HEAP_SIZE { }; // { ro section .dataflash* }; define movable block ROPI with alignment = 4, fixed order, static base CB -{ +{ ro object txm_module_preamble_rx65n.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base SB diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module.c b/ports_module/rxv2/iar/example_build/sample_threadx_module.c index 51822c10..80d89b01 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -99,7 +99,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -115,7 +115,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -127,42 +127,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -170,23 +170,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -196,7 +196,7 @@ CHAR *pointer; tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); tx_queue_send_notify(queue_0, queue_0_notify); - + /* Create the semaphore used by threads 3 and 4. */ tx_semaphore_create(semaphore_0, "module semaphore 0", 1); @@ -241,7 +241,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -289,18 +289,18 @@ UINT status; { /* Write value to shared memory region. */ // *(ULONG *)0x00020000 = 0xCDCDCDCD; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -354,12 +354,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c index 4afbbe39..46e3be59 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,39 +75,39 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); - - + + /* Enable 128 byte read/write shared memory region at 0x00020000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x00020000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ | TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); - + /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); - + /* Set maximum module priority to 5. */ txm_module_manager_maximum_module_priority_set(&my_module, 5); - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s index 391e9c5c..b47b1684 100644 --- a/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -59,12 +59,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 01-31-2022 William E. Lamie Initial Version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_initialize_low_level @@ -74,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports_module/rxv2/iar/example_build/txm_module_preamble.s b/ports_module/rxv2/iar/example_build/txm_module_preamble.s index bf5bb9fb..13487bc7 100644 --- a/ports_module/rxv2/iar/example_build/txm_module_preamble.s +++ b/ports_module/rxv2/iar/example_build/txm_module_preamble.s @@ -1,7 +1,7 @@ /* Alignment of 4 (16-byte) */ SECTION .text:CODE (4) - - + + /* Define public symbols. */ PUBLIC __txm_module_preamble @@ -25,7 +25,7 @@ __txm_module_preamble: DC32 0x5 // Module Major Version DC32 0x6 // Module Minor Version DC32 32 // Module Preamble Size in 32-bit words - DC32 0x12345678 // Module ID (application defined) + DC32 0x12345678 // Module ID (application defined) DC32 0x00000007 // Module Properties where: // Bits 31-24: Compiler ID // 0 -> IAR @@ -39,23 +39,23 @@ __txm_module_preamble: // 1 -> Enable shared/external memory access DC32 __txm_module_thread_shell_entry - $ // Module Shell Entry Point DC32 _demo_module_start - $ // Module Start Thread Entry Point - DC32 0 // Module Stop Thread Entry Point + DC32 0 // Module Stop Thread Entry Point DC32 1 // Module Start/Stop Thread Priority DC32 1024 // Module Start/Stop Thread Stack Size DC32 __txm_module_callback_request_thread_entry - $ // Module Callback Thread Entry - DC32 1 // Module Callback Thread Priority - DC32 1024 // Module Callback Thread Stack Size + DC32 1 // Module Callback Thread Priority + DC32 1024 // Module Callback Thread Stack Size DC32 ROPI$$Length // Module Code Size DC32 RWPI$$Length // Module Data Size - DC32 0 // Reserved 0 + DC32 0 // Reserved 0 DC32 0 // Reserved 1 DC32 0 // Reserved 2 DC32 0 // Reserved 3 DC32 0 // Reserved 4 - DC32 0 // Reserved 5 - DC32 0 // Reserved 6 - DC32 0 // Reserved 7 - DC32 0 // Reserved 8 + DC32 0 // Reserved 5 + DC32 0 // Reserved 6 + DC32 0 // Reserved 7 + DC32 0 // Reserved 8 DC32 0 // Reserved 9 DC32 0 // Reserved 10 DC32 0 // Reserved 11 diff --git a/ports_module/rxv2/iar/inc/tx_port.h b/ports_module/rxv2/iar/inc/tx_port.h index 1790cd94..cc4bddee 100644 --- a/ports_module/rxv2/iar/inc/tx_port.h +++ b/ports_module/rxv2/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,21 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 06-02-2021 William E. Lamie Modified comments, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -70,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -118,8 +104,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -144,7 +130,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -156,11 +142,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -174,7 +160,7 @@ typedef unsigned short USHORT; ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; \ VOID *tx_thread_iar_tls_pointer; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -195,11 +181,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -207,8 +193,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -234,9 +220,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -286,8 +272,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv2/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/rxv2/iar/inc/txm_module_port.h b/ports_module/rxv2/iar/inc/txm_module_port.h index fc7520b9..5712f376 100644 --- a/ports_module/rxv2/iar/inc/txm_module_port.h +++ b/ports_module/rxv2/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -90,7 +85,7 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ -#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION /* Define constants specific to the tools the module can be built with for this particular modules port. */ @@ -255,7 +250,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { \ _tx_mutex_put(&_txm_module_manager_mutex); \ return(TXM_MODULE_INVALID_PROPERTIES); \ - } + } /* Define the macro to check the code alignment. */ @@ -395,6 +390,6 @@ VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instan #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module RXv2/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module RXv2/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c index 95d085fa..1242184c 100644 --- a/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init2(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init2(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s index f3d5293c..3faf9bc9 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 William E. Lamie Initial Version 6.1.10 */ -/* */ /**************************************************************************/ public __tx_initialize_low_level @@ -72,7 +66,7 @@ __tx_initialize_low_level: // _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; MOV.L #__tx_free_memory_start, R1 // Pick up unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] // Save first free memory address /* Set priority of SWINT to 1. */ @@ -89,7 +83,7 @@ __tx_initialize_low_level: /* Enable SWINT2. */ OR #(1 << 2), r2 MOV.B r2, [r1] - + RTS section FREEMEM:DATA diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s index b9dc97da..f4c5f492 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -72,16 +72,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ public __tx_thread_context_restore @@ -99,7 +89,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -121,17 +111,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -172,7 +162,7 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACGU #0, A1, R4 ; Save accumulators. MVFACHI #0, A1, R5 MVFACLO #0, A1, R6 @@ -181,7 +171,7 @@ __tx_thread_dont_save_ts: MVFACHI #0, A0, R5 MVFACLO #0, A0, R6 PUSHM R4-R6 - + ; ; /* Clear the current task pointer. */ ; _tx_thread_current_ptr = TX_NULL; diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s index 0d461baa..4e7b8fc3 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -65,14 +65,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ @@ -100,7 +92,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -126,7 +118,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -148,7 +140,7 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer @@ -167,5 +159,5 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s index 558b9153..b2cb65e4 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -59,14 +59,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -75,20 +67,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s index fb60efaa..572eff32 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,17 +63,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* removed unnecessary stack */ -/* type checking, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -134,40 +124,40 @@ __tx_thread_schedule_loop: MOV.L 156[R2],R1 // Pickup user_mode CMP #0,R1 // Is protection required for this thread? BEQ skip_mpu_setup // No, skip MPU setup - + MOV.L #0x00086408,R1 // Region 1 Start Page Register address MOV.L 144[R2],R2 // Address of module instance ptr at offset 144 in TCB ADD #100,R2,R2 // Get address of MPU table in module struct, starting at region 1 - + // Region 0 (Trampoline from User mode to ThreadX) set up in txm_module_manager_setup_mpu_registers.c - + // Build region 1 (User code) MOV.L [R2+],R4 // Pickup region 1 start page, increment to region 1 end page MOV.L R4,[R1+] // Setup region 1 start page reg, increment to region 1 end page reg. MOV.L [R2+],R4 // Pickup region 1 end page, increment to region 2 start page MOV.L R4,[R1+] // Setup region 1 end page reg, increment to region 2 start page reg. - + // Build region 2 (User data) MOV.L [R2+],R4 // Pickup region 2 start page, increment to region 2 end page MOV.L R4,[R1+] // Setup region 2 start page reg, increment to region 2 end page reg. MOV.L [R2+],R4 // Pickup region 2 end page, increment to region 3 start page MOV.L R4,[R1+] // Setup region 2 end page reg, increment to region 3 start page reg. - + // Build region 3 (Shared memory) MOV.L [R2+],R4 // Pickup region 3 start page, increment to region 3 end page MOV.L R4,[R1+] // Setup region 3 start page reg, increment to region 3 end page reg. MOV.L [R2+],R4 // Pickup region 3 end page, increment to region 4 start page MOV.L R4,[R1+] // Setup region 3 end page reg, increment to region 4 start page reg. - + // Region 4-7 unused - + // Setup background region MOV.L #0x00086504,R1 // Pickup MPBAC MOV #0,[R1] // Read/Write/Execute prohibited. // Enable MPU MOV.L #0x00086500,R1 // Pickup MPEN MOV #1,[R1] // Enable MPU - + skip_mpu_setup POPM R1-R3 // Restore accumulators. @@ -180,7 +170,7 @@ skip_mpu_setup MVTACGU R1, A1 POPM R6-R13 // Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 POPM R1-R2 @@ -195,7 +185,7 @@ skip_mpu_setup The priority of this interrupt is set to the lowest priority within tx_initialize_low_level() and triggered by ThreadX when calling _tx_thread_system_return(). */ - + public ___interrupt_27 ___interrupt_27: @@ -206,7 +196,7 @@ ___interrupt_27: BRA __tx_thread_context_restore -/* You may have to modify BSP to use this handler. +/* You may have to modify BSP to use this handler. // MPU Memory access violation PUBLIC ___excep_access_inst PUBLIC ___violation_handler @@ -260,15 +250,15 @@ ___violation_handler MOV.L R3, 32[R1] // Save R1 POP R3 // Recall R2 MOV.L R3, 36[R1] // Save R2 - + BSR __txm_module_manager_memory_fault_handler // Call memory manager fault handler - + // Decrement and save system state MOV.L #__tx_thread_system_state, R1 // Pickup address of system state MOV.L [R1], R2 // Pickup system state SUB #1, R2 // Decrement MOV.L R2, [R1] // Store new system state - + MOV.L #__tx_thread_current_ptr, R2 // Pickup address of current thread pointer MOV.L #0, [R2] // Clear current thread pointer BRA __tx_thread_schedule // Attempt to schedule the next thread @@ -284,15 +274,15 @@ __txm_module_manager_kernel CMP #__txm_module_manager_user_mode_entry+3, R5 // Did we come from user_mode_entry? BEQ __txm_module_manager_entry // If so, continue. RTE // If not, then return from where we came. - + __txm_module_manager_entry // We are entering the kernel from a module thread with user mode selected. - // At this point, we are out of user mode! + // At this point, we are out of user mode! // Clear current user mode. MOV.L #__tx_thread_current_ptr, R5 MOV [R5],R5 MOV #0,152[R5] - + // Switch to kernel stack PUSHM R1-R2 MVFC USP, R1 // Pickup module thread stack pointer @@ -312,7 +302,7 @@ __txm_module_manager_entry MOV.L 4[SP], R5 BCLR #20, R5 MOV.L R5, 4[SP] - + // Return to user_mode_entry where kernel_dispatch will be called. RTE @@ -324,12 +314,12 @@ __txm_module_manager_entry __txm_module_manager_user_mode_entry INT #26 // Enter ThreadX kernel (exit User mode). - + // At this point, we are out of user mode. // Simply call the kernel dispatch function. MOV.L #__txm_module_manager_kernel_dispatch,R5 JSR R5 - + // Restore user mode while inside of ThreadX. MOV.L #__tx_thread_current_ptr, R5 MOV [R5],R5 @@ -348,7 +338,7 @@ __txm_module_manager_user_mode_entry #endif MOV.L 172[R5], R5 // Pickup module thread stack pointer MVTC R5, USP // Set stack pointer - + // USP is set for an RTS, need to set for RTE to set User mode in PSW. // Push return address on SP @@ -359,21 +349,21 @@ __txm_module_manager_user_mode_entry BSET #20,R5 MOV.L R5,4[SP] RTE - + // Fill rest of page with NOPs. NOP NOP NOP NOP - + NOP NOP NOP NOP - + NOP NOP NOP NOP - + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s index be33d407..1d8f4593 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,26 +55,14 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -137,11 +125,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s index 714e1276..2c2021f6 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,14 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s index 1b736519..cb79535a 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,18 +73,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -147,14 +135,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -165,7 +153,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -184,9 +172,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -220,14 +208,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c index a12e5386..c14c1715 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 25d1ea2b..f407249a 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -106,7 +101,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -116,7 +111,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble ext/shared mem property bit set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if(!(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -127,24 +122,24 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address must be 16-byte aligned. */ address = (ULONG) start_address; if(address != (address & 0xFFFFFFF0)) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* Check length. */ - + /* At this point, we have a valid address and length. */ /* Build region start page register. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address & 0xFFFFFFF0; - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_EXECUTE) { @@ -158,17 +153,17 @@ TXM_MODULE_PREAMBLE *module_preamble; { attributes_check |= TXM_MODULE_MANAGER_ATTRIBUTE_READ_MPU_BIT; } - + /* Build region end page register with attributes, OR in the Valid bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = ((address + length - 1) & 0xFFFFFFF0) | attributes_check | 0x01; - + /* Save address and length in module. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 4cc5159e..0ff6baf2 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 405c049f..7fe88dfe 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c index 9175331b..183f38ae 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instance) { @@ -73,34 +68,34 @@ ULONG region_end_page_register; region_start_page_register = (ULONG) _txm_module_manager_user_mode_entry; region_start_page_register = region_start_page_register & 0xFFFFFFF0; module_instance -> txm_module_instance_mpu_registers[0] = region_start_page_register; - /* Region 0 End page is 2 pages away (for a total of 3 pages). + /* Region 0 End page is 2 pages away (for a total of 3 pages). * Set reading permitted, writing prohibited, execution permitted, enable region. */ module_instance -> txm_module_instance_mpu_registers[1] = (region_start_page_register + 0x20) | 0x0B; - + /* Place the trampoline protection in the MPU registers */ RSPAGE0 = module_instance -> txm_module_instance_mpu_registers[0]; REPAGE0 = module_instance -> txm_module_instance_mpu_registers[1]; - + /* Setup region 1 for code area. */ /* Set reading permitted, writing prohibited, execution permitted, enable region. */ - region_start_page_register = (ULONG) module_instance -> txm_module_instance_code_start; + region_start_page_register = (ULONG) module_instance -> txm_module_instance_code_start; region_size = (ULONG) module_instance -> txm_module_instance_code_size; - + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; region_start_page_register = region_start_page_register & 0xFFFFFFF0; - + module_instance -> txm_module_instance_mpu_registers[2] = region_start_page_register; module_instance -> txm_module_instance_mpu_registers[3] = region_end_page_register | 0x0B; - + /* Setup region 2 for data area. */ /* Set reading permitted, writing permitted, execution prohibited, enable region. */ - region_start_page_register = (ULONG) module_instance -> txm_module_instance_data_start; + region_start_page_register = (ULONG) module_instance -> txm_module_instance_data_start; region_size = (ULONG) module_instance -> txm_module_instance_data_size; - + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; region_start_page_register = region_start_page_register & 0xFFFFFFF0; - + module_instance -> txm_module_instance_mpu_registers[4] = region_start_page_register; module_instance -> txm_module_instance_mpu_registers[5] = region_end_page_register | 0x0D; - + } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 9cf9fa14..fa5bf71d 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -68,7 +62,7 @@ __txm_module_manager_thread_stack_build: /* Build an interrupt frame. The form of the fake interrupt stack on the Renesas RX should look like the following after it is built: - + Stack Top: 1 Interrupt stack frame type ACC0 ACC1 @@ -103,9 +97,9 @@ __txm_module_manager_thread_stack_build: BMC #20,R4 // if user mode, set mode bit of initial PSW MOV.L R4, [-R3] // initial PSW MOV.L R2, [-R3] // initial PC - + MOV.L 8[R1], R4 // Pickup thread entry info pointer, which is in the stack pointer position of the thread control block. - // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this // function with the actual, initial stack pointer. MOV.L R4,[-R3] // initial R2, which is the module entry information. MOV.L R1,[-R3] // initial R1, which is the thread control block. |