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port (#534)
* Reverted RISCV-64 port
* Fixed wrong load/store instructions used
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* Add BananaPi BPI-F3 BSP support
Add RISC-V supervisor support to the rv64/gnu port and
provide a complete board support package for the BananaPi BPI-F3
(SpacemiT K1 SoC, X60 cores).
Port changes (risc-v64/gnu):
- Guard all CSR accesses with TX_RISCV_SMODE to select S-mode registers
(sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in
context_save, context_restore, schedule, system_return,
interrupt_control, and stack_build.
- Add S-mode TX_INT_ENABLE/TX_DISABLE and inline TX_RESTORE macros
to tx_port.h.
- Add TX_RISCV_SMODE CMake option to CMakeLists.txt.
BananaPi BPI-F3 BSP (example_build/bananapi-f3):
- Boot flow: FSBL → OpenSBI (M-mode) → U-Boot (S-mode) → ThreadX
- S-mode trap handler with context save/restore integration
- SBI legacy ecall timer at 10 Hz (24 MHz timebase)
- PLIC driver with S-mode context, stale-IRQ drain, and callbacks
- PXA-compatible UART0 console (115200 8N1)
- Linker script at 0x200000 load address
Tested on risc-v board, BananaPi BPI-F3 hardware.
Signed-off-by: Akif Ejaz <[email protected]>
* Fixed S-mode context restore and PLIC spurious IRQ handling
- tx_thread_context_restore.S (non-nested path): set SPIE(0x20) alongside
SPP(0x100) so sret re-enables interrupts in the restored thread.
- tx_thread_context_restore.S (both S-mode paths): use FS=Dirty (0x6000)
instead of FS=Initial (0x2000) to match tx_thread_schedule.S and prevent
FP register corruption across context switches.
- plic.c (plic_irq_intr): return early when plic_claim() yields 0 (no
pending interrupt) to avoid completing a spurious IRQ ID 0, which is
undefined behavior per the PLIC spec.
Co-authored-by: Copilot <[email protected]>
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Signed-off-by: Akif Ejaz <[email protected]>
Co-authored-by: Frédéric Desbiens <[email protected]>
Co-authored-by: Copilot <[email protected]>
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Added rv64 rvv support
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* Updated version number constants
* Removed revision history from all files
* Added Eclipse ThreadX contributors' copyright header
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- removed the trailing whitespaces
Signed-off-by: Akif Ejaz <[email protected]>
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- removed tx_port.h dependency from .S files
- replaced tx_timer_interrupt.c with tx_timer_interrupt.S
- made some cleanups, formatting to better readability
- removed macros (LOAD/STORE/REGBYTES)
changed register nomenclature to use RISC-V ABI
names (ra, sp, t0, etc.)
- added readme_threadx.txt
Signed-off-by: Akif Ejaz <[email protected]>
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cee19603d Include tx_user.h conditionally.
e40e08007 Update owners
d69641273 Update release date and version
394aee52f Add tx_user.h to GNU port assembly files
5cca2ddd0 RISC-V 64 bit port for Microchip
e0f2c373c Link Winmm.lib that required by the high-resolution timer.
6af472a68 Update Win32 port with high resolution timer.
aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler
19091a262 Add .section .preamble to m3 m4 m7 module ports
ced60e1b7 Add missing parenthesis in ports assembly file
309dc77ca Modules Cortex-A7 IAR new port
c752a4063 Modules Cortex-A7 GNU new port
dc224b90f Fix race condition in tx_thread_wait_abort and update regression test
6e261f5b7 create threadx cmsis-pack
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