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* Updated version number constants
* Updated port version strings
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Co-authored-by: Copilot <[email protected]>
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Applied the standard MIT license header to all project-owned C, header,
assembly, shell, and Python files that were missing a copyright notice.
Third-party, toolchain startup, and auto-generated files were excluded.
Co-authored-by: Copilot <[email protected]>
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* Updated version number constants
* Updated port version strings
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Co-authored-by: Copilot <[email protected]>
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* Add LX8 support for > 32 interrupts
Also fix inconsistent SWPRI define in interrupt handler
* ThreadX: Fix context switch logic
- Disable interrupts prior to allocating a large exception frame;
only reenable them after deallocating the extra memory.
- Any user tasks with stacks based on TX_MINIMUM_STACK do not
have sufficient space for both a context switch frame and an ISR
frame; ill-timed interrupts were causing stack overruns.
* ThreadX: Interrupt fixes for TX_ENABLE_EXECUTION_CHANGE_NOTIFY
- Must reload register trashed by notify hook function call
- Must ensure PS.WOE is set before using call8
- Remove unused XT_USE_INT_WRAPPER define and associated changes,
which had a bug in XEA2 usage
- Fix another case where enabling the thread notify hooks for
call0 ABI corrupted a register
* ThreadX: Support for __DYNAMIC_REENT__
- ThreadX change to handle dynamic reent for both newlib and xclib
- Adapt ThreadX xclib interface code to handle dynamic reent pointers
* ThreadX: Xtensa execution profiling support
- Update upstream execution profiling for Xtensa port
* ThreadX: Update xtensa port readme
* ThreadX: Add Xtensa example to EPK
- tx_execution_profile.h now defines an Xtensa example
in addition to the existing Cortex example
* ThreadX: Add xtensa.cmake
* ThreadX: Update XSHAL_CLIB ifdefs in __getreent()
- Prevent a fall-through with no return value when neither
xclib nor newlib are used.
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* Updated version number constants
* Removed revision history from all files
* Added Eclipse ThreadX contributors' copyright header
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* Add error handling in lock initialization.
* Update release data and version.
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* Update version number in API header
* Update release date and version
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af5702cbf Include tx_user.h only when TX_INCLUDE_USER_DEFINE_FILE is defined for assembly files
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cee19603d Include tx_user.h conditionally.
e40e08007 Update owners
d69641273 Update release date and version
394aee52f Add tx_user.h to GNU port assembly files
5cca2ddd0 RISC-V 64 bit port for Microchip
e0f2c373c Link Winmm.lib that required by the high-resolution timer.
6af472a68 Update Win32 port with high resolution timer.
aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler
19091a262 Add .section .preamble to m3 m4 m7 module ports
ced60e1b7 Add missing parenthesis in ports assembly file
309dc77ca Modules Cortex-A7 IAR new port
c752a4063 Modules Cortex-A7 GNU new port
dc224b90f Fix race condition in tx_thread_wait_abort and update regression test
6e261f5b7 create threadx cmsis-pack
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b5d5df511 #include tx_user.h in assembly files for cortex-m ports
33e04e3d5 initial port of MIPS SMP for GHS and GNU
2eda2c17d capitalize extensions for M23 asm files
21c354ccb Fix armv7-m MPU settings for corner case, unify txm_module_port.h files
4a1ff93f9 remove uneeded include for ac6
c823e91ff update riscv iar example for latest iar tools
5559d185d check module stack for overlap (not kernel stack)
efa9ce7b7 apply patch from mobileye to fix time slice processing
75fdcb722 Updated copy_armv7_cm.yml
de04b9904 initialize unused MPU settings so that aliasing will work
79b317b60 add config directory to IAR RISC-V port in order to use simulator
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