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#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
; command above MUST be in first line (no comment above!)
;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*
ID From To Alias Security NSC
1 0x0000_0000 0x000F_FFFF 1MB Code ITCM 4 NS n/a
2 0x0010_0000 0x002F_FFFF 2MB Code SRAM (only 2MB) 5 NS n/a
4 0x1000_0000 0x100F_FFFF 1MB Code ITCM 1 S n/a
5 0x1100_0000 0x102F_FFFF 2MB Code SRAM (only 2MB) 2 S CODE NSC
7 0x2000_0000 0x203F_FFFF 4MB SRAM DTCM (4 x 1MB) 11 NS n/a
11 0x3000_0000 0x303F_FFFF 4MB SRAM DTCM (4 x 1MB) 7 S n/a
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00080000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20080000
#define __RAM_SIZE 0x00080000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000400
#define __HEAP_SIZE 0x00000C00
/*--------------------- CMSE Veneer Configuration ---------------------------
; <h> CMSE Veneer Configuration
; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
; </h>
*----------------------------------------------------------------------------*/
#define __CMSEVENEER_BASE 0x10100000
#define __CMSEVENEER_SIZE 0x00000400
/*
;------------- <<< end of configuration section >>> ---------------------------
*/
/*----------------------------------------------------------------------------
User Stack & Heap boundary definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/* ----------------------------------------------------------------------------
Stack seal size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define __STACKSEAL_SIZE ( 8 )
#else
#define __STACKSEAL_SIZE ( 0 )
#endif
/*----------------------------------------------------------------------------
Region base & size definition
*----------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
#else
#define __CV_BASE ( __CMSEVENEER_BASE )
#endif
#define __CV_SIZE ( __CMSEVENEER_SIZE )
#else
#define __CV_SIZE ( 0 )
#endif
#define __RO_BASE ( __ROM_BASE )
#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
#define __RW_BASE ( __RAM_BASE )
#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
/*----------------------------------------------------------------------------
Scatter Region definition
*----------------------------------------------------------------------------*/
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
}
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
ER_CMSE_VENEER __CV_BASE __CV_SIZE {
*(Veneer$$CMSE)
}
}
#endif
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