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/***************************************************************************
 * Copyright (c) 2024 Microsoft Corporation
 *
 * This program and the accompanying materials are made available under the
 * terms of the MIT License which is available at
 * https://opensource.org/licenses/MIT.
 *
 * SPDX-License-Identifier: MIT
 **************************************************************************/


/**************************************************************************/
/**************************************************************************/
/**                                                                       */
/** ThreadX Component                                                     */
/**                                                                       */
/**   Thread                                                              */
/**                                                                       */
/**************************************************************************/
/**************************************************************************/


/* #define TX_SOURCE_CODE  */


/* Include necessary system files.  */

/*  #include "tx_api.h"
    #include "tx_thread.h"
    #include "tx_timer.h"   */

#ifdef TX_ENABLE_FIQ_SUPPORT
    ENABLE_INTS     =   0xC0                    # IRQ & FIQ Interrupts enabled mask
#else
    ENABLE_INTS     =   0x80                    # IRQ Interrupts enabled mask
#endif

    .text
    .align  4
/**************************************************************************/
/*                                                                        */
/*  FUNCTION                                               RELEASE        */
/*                                                                        */
/*    _tx_thread_schedule                           Cortex-R4/Green Hills */
/*                                                           6.1          */
/*  AUTHOR                                                                */
/*                                                                        */
/*    William E. Lamie, Microsoft Corporation                             */
/*                                                                        */
/*  DESCRIPTION                                                           */
/*                                                                        */
/*    This function waits for a thread control block pointer to appear in */
/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
/*    in the variable, the corresponding thread is resumed.               */
/*                                                                        */
/*  INPUT                                                                 */
/*                                                                        */
/*    None                                                                */
/*                                                                        */
/*  OUTPUT                                                                */
/*                                                                        */
/*    None                                                                */
/*                                                                        */
/*  CALLS                                                                 */
/*                                                                        */
/*    None                                                                */
/*                                                                        */
/*  CALLED BY                                                             */
/*                                                                        */
/*    _tx_initialize_kernel_enter          ThreadX entry function         */
/*    _tx_thread_system_return             Return to system from thread   */
/*    _tx_thread_context_restore           Restore thread's context       */
/*                                                                        */
/*  RELEASE HISTORY                                                       */
/*                                                                        */
/*    DATE              NAME                      DESCRIPTION             */
/*                                                                        */
/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
/*                                                                        */
/**************************************************************************/
/* VOID   _tx_thread_schedule(VOID)
{  */
    .globl  _tx_thread_schedule
_tx_thread_schedule:

    /* Enable interrupts.  */

#ifdef TX_BEFORE_ARMV6
    MRS     r2, CPSR                            # Pickup CPSR
    BIC     r0, r2, ENABLE_INTS                 # Clear the disable bit(s)
    MSR     CPSR_c, r0                          # Enable interrupts
#else
#ifdef TX_ENABLE_FIQ_SUPPORT
    CPSIE   if                                  # Enable IRQ and FIQ interrupts
#else
    CPSIE   i                                   # Enable IRQ interrupts
#endif
#endif

    /* Wait for a thread to execute.  */
    /* do
    {  */
    LDR     r1, =_tx_thread_execute_ptr         # Address of thread execute ptr

__tx_thread_schedule_loop:

    LDR     r0, [r1]                            # Pickup next thread to execute
    CMP     r0, 0                               # Is it NULL?
    BEQ     __tx_thread_schedule_loop           # If so, keep looking for a thread

    /* }
    while(_tx_thread_execute_ptr == TX_NULL);  */

    /* Yes! We have a thread to execute.  Lockout interrupts and
       transfer control to it.  */

#ifdef TX_BEFORE_ARMV6
    MSR     CPSR_c, r2                          # Disable interrupts
#else
#ifdef TX_ENABLE_FIQ_SUPPORT
    CPSID   if                                  # Disable IRQ and FIQ interrupts
#else
    CPSID   i                                   # Disable IRQ interrupts
#endif
#endif

    /* Setup the current thread pointer.  */
    /* _tx_thread_current_ptr =  _tx_thread_execute_ptr;  */

#ifdef TX_ENABLE_EVENT_LOGGING
    MOV     v1, r0                              # Save temp register in non-volatile register
    BL      _tx_el_thread_running               # Call event logging routine
    MOV     r0, v1                              # Restore temp register
#endif

    LDR     r1, =_tx_thread_current_ptr         # Pickup address of current thread
    STR     r0, [r1]                            # Setup current thread pointer

    /* Increment the run count for this thread.  */
    /* _tx_thread_current_ptr -> tx_thread_run_count++;  */

    LDR     r2, [r0, 4]                         # Pickup run counter
    LDR     r3, [r0, 24]                        # Pickup time-slice for this thread
    ADD     r2, r2, 1                           # Increment thread run-counter
    STR     r2, [r0, 4]                         # Store the new run counter

    /* Setup time-slice, if present.  */
    /* _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;  */

    LDR     r2, =_tx_timer_time_slice           # Pickup address of time slice
                                        /*      #   variable  */
    LDR     sp, [r0, 8]                         # Switch stack pointers
    STR     r3, [r2]                            # Setup time-slice

    /* Switch to the thread's stack.  */
    /* sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;  */

#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY

    /* Call the thread entry function to indicate the thread is executing.  */

    BL      _tx_execution_thread_enter          # Call the thread execution enter function
#endif

    /* Determine if an interrupt frame or a synchronous task suspension frame
       is present.  */

    LDMIA   sp!, {r0, r1}                       # Pickup the stack type and saved CPSR
    MSR     SPSR_cxsf, r1                       # Setup SPSR for return
    CMP     r0, 0                               # Check for synchronous context switch
    LDMNEIA sp!, {r0-r12, lr, pc}^              # If non-zero, return to point of interrupt
                                        /*      #   in the thread  */
    LDMIA   sp!, {v1-r11, lr}                   # Otherwise, return to thread synchronously
    MSR     CPSR_cxsf,r1                        # Recover CPSR (r1 is still valid)
    RET                                         # Return to caller (Thumb safe)

    .type   _tx_thread_schedule,$function
    .size   _tx_thread_schedule,.-_tx_thread_schedule
/* }  */