1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
|
/***************************************************************************
* Copyright (c) 2025 10xEngineers
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Akif Ejaz, 10xEngineers */
/* Wei-Chen Lai, National Cheng Kung University */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_restore(VOID)
{ */
.global _tx_thread_context_restore
_tx_thread_context_restore:
/* Lockout interrupts. */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_exit // Call the ISR execution exit function
#endif
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state)
{ */
la t0, _tx_thread_system_state // Pickup addr of nested interrupt count
lw t1, 0(t0) // Pickup nested interrupt count
addi t1, t1, -1 // Decrement the nested interrupt counter
sw t1, 0(t0) // Store new nested count
beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore
/* Interrupts are nested. */
/* Just recover the saved registers and return to the point of
interrupt. */
/* Recover floating point registers only if saved mstatus.FS was not Off. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
lw t1, 29*4(sp) // Pickup saved mstatus
srli t1, t1, 13
andi t1, t1, 0x3
beqz t1, _tx_thread_skip_fp_restore // Skip if FS was Off
#endif
#if defined(__riscv_float_abi_single)
flw f0, 31*4(sp) // Recover ft0
flw f1, 32*4(sp) // Recover ft1
flw f2, 33*4(sp) // Recover ft2
flw f3, 34*4(sp) // Recover ft3
flw f4, 35*4(sp) // Recover ft4
flw f5, 36*4(sp) // Recover ft5
flw f6, 37*4(sp) // Recover ft6
flw f7, 38*4(sp) // Recover ft7
flw f10, 41*4(sp) // Recover fa0
flw f11, 42*4(sp) // Recover fa1
flw f12, 43*4(sp) // Recover fa2
flw f13, 44*4(sp) // Recover fa3
flw f14, 45*4(sp) // Recover fa4
flw f15, 46*4(sp) // Recover fa5
flw f16, 47*4(sp) // Recover fa6
flw f17, 48*4(sp) // Recover fa7
flw f28, 59*4(sp) // Recover ft8
flw f29, 60*4(sp) // Recover ft9
flw f30, 61*4(sp) // Recover ft10
flw f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*4(sp) // Recover ft0
fld f1, 32*4(sp) // Recover ft1
fld f2, 33*4(sp) // Recover ft2
fld f3, 34*4(sp) // Recover ft3
fld f4, 35*4(sp) // Recover ft4
fld f5, 36*4(sp) // Recover ft5
fld f6, 37*4(sp) // Recover ft6
fld f7, 38*4(sp) // Recover ft7
fld f10, 41*4(sp) // Recover fa0
fld f11, 42*4(sp) // Recover fa1
fld f12, 43*4(sp) // Recover fa2
fld f13, 44*4(sp) // Recover fa3
fld f14, 45*4(sp) // Recover fa4
fld f15, 46*4(sp) // Recover fa5
fld f16, 47*4(sp) // Recover fa6
fld f17, 48*4(sp) // Recover fa7
fld f28, 59*4(sp) // Recover ft8
fld f29, 60*4(sp) // Recover ft9
fld f30, 61*4(sp) // Recover ft10
fld f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
_tx_thread_skip_fp_restore:
/* Recover standard registers. */
/* Restore registers,
Skip global pointer because that does not change.
Also skip the saved registers since they have been restored by any function we called,
except s0 since we use it ourselves. */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits.
Set MPIE and restore MPP to Machine, preserve other fields. */
csrr t1, mstatus
/* Clear MPP/MPIE/MIE bits in t1 then set desired values. */
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1880 // Set MPP=Machine (0x1800) + MPIE=1 (0x80); mret sets MIE=MPIE
/* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit,
preserve everything except the bits we will modify. */
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely
lw ra, 28*4(sp) // Recover return address
lw t0, 19*4(sp) // Recover t0
lw t1, 18*4(sp) // Recover t1
lw t2, 17*4(sp) // Recover t2
lw s0, 12*4(sp) // Recover s0
lw a0, 27*4(sp) // Recover a0
lw a1, 26*4(sp) // Recover a1
lw a2, 25*4(sp) // Recover a2
lw a3, 24*4(sp) // Recover a3
lw a4, 23*4(sp) // Recover a4
lw a5, 22*4(sp) // Recover a5
lw a6, 21*4(sp) // Recover a6
lw a7, 20*4(sp) // Recover a7
lw t3, 16*4(sp) // Recover t3
lw t4, 15*4(sp) // Recover t4
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
#endif
mret // Return to point of interrupt
/* } */
_tx_thread_not_nested_restore:
/* Determine if a thread was interrupted and no preemption is required. */
/* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|| (_tx_thread_preempt_disable))
{ */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
lw t1, 0(t0) // Pickup current thread pointer
beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore
la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address
lw t2, 0(t0) // Pickup preempt disable flag (UINT)
bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread
la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address
lw t2, 0(t0) // Pickup thread execute pointer
bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt
_tx_thread_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Pickup the saved stack pointer. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
lw sp, 8(t1) // Switch back to thread's stack
/* Recover floating point registers only if saved mstatus.FS was not Off. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
lw t3, 29*4(sp) // Pickup saved mstatus
srli t3, t3, 13
andi t3, t3, 0x3
beqz t3, _tx_thread_no_preempt_skip_fp_restore // Skip if FS was Off
#endif
#if defined(__riscv_float_abi_single)
flw f0, 31*4(sp) // Recover ft0
flw f1, 32*4(sp) // Recover ft1
flw f2, 33*4(sp) // Recover ft2
flw f3, 34*4(sp) // Recover ft3
flw f4, 35*4(sp) // Recover ft4
flw f5, 36*4(sp) // Recover ft5
flw f6, 37*4(sp) // Recover ft6
flw f7, 38*4(sp) // Recover ft7
flw f10, 41*4(sp) // Recover fa0
flw f11, 42*4(sp) // Recover fa1
flw f12, 43*4(sp) // Recover fa2
flw f13, 44*4(sp) // Recover fa3
flw f14, 45*4(sp) // Recover fa4
flw f15, 46*4(sp) // Recover fa5
flw f16, 47*4(sp) // Recover fa6
flw f17, 48*4(sp) // Recover fa7
flw f28, 59*4(sp) // Recover ft8
flw f29, 60*4(sp) // Recover ft9
flw f30, 61*4(sp) // Recover ft10
flw f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*4(sp) // Recover ft0
fld f1, 32*4(sp) // Recover ft1
fld f2, 33*4(sp) // Recover ft2
fld f3, 34*4(sp) // Recover ft3
fld f4, 35*4(sp) // Recover ft4
fld f5, 36*4(sp) // Recover ft5
fld f6, 37*4(sp) // Recover ft6
fld f7, 38*4(sp) // Recover ft7
fld f10, 41*4(sp) // Recover fa0
fld f11, 42*4(sp) // Recover fa1
fld f12, 43*4(sp) // Recover fa2
fld f13, 44*4(sp) // Recover fa3
fld f14, 45*4(sp) // Recover fa4
fld f15, 46*4(sp) // Recover fa5
fld f16, 47*4(sp) // Recover fa6
fld f17, 48*4(sp) // Recover fa7
fld f28, 59*4(sp) // Recover ft8
fld f29, 60*4(sp) // Recover ft9
fld f30, 61*4(sp) // Recover ft10
fld f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
_tx_thread_no_preempt_skip_fp_restore:
/* Recover the saved context and return to the point of interrupt. */
/* Recover standard registers. */
/* Restore registers,
Skip global pointer because that does not change */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */
csrr t1, mstatus
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1880 // Set MPP=Machine (0x1800) + MPIE=1 (0x80); mret sets MIE=MPIE
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely
lw ra, 28*4(sp) // Recover return address
lw t0, 19*4(sp) // Recover t0
lw t1, 18*4(sp) // Recover t1
lw t2, 17*4(sp) // Recover t2
lw s0, 12*4(sp) // Recover s0
lw a0, 27*4(sp) // Recover a0
lw a1, 26*4(sp) // Recover a1
lw a2, 25*4(sp) // Recover a2
lw a3, 24*4(sp) // Recover a3
lw a4, 23*4(sp) // Recover a4
lw a5, 22*4(sp) // Recover a5
lw a6, 21*4(sp) // Recover a6
lw a7, 20*4(sp) // Recover a7
lw t3, 16*4(sp) // Recover t3
lw t4, 15*4(sp) // Recover t4
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
#endif
mret // Return to point of interrupt
/* }
else
{ */
_tx_thread_preempt_restore:
/* Instead of directly activating the thread again, ensure we save the
entire stack frame by saving the remaining registers. */
lw t0, 8(t1) // Pickup thread's stack pointer
ori t3, zero, 1 // Build interrupt stack type
sw t3, 0(t0) // Store stack type
/* Store floating point preserved registers only if saved mstatus.FS was not Off. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
lw t3, 29*4(t0) // Pickup saved mstatus
srli t3, t3, 13
andi t3, t3, 0x3
beqz t3, _tx_thread_preempt_skip_fp_restore // Skip if FS was Off
#endif
#ifdef __riscv_float_abi_single
fsw f8, 39*4(t0) // Store fs0
fsw f9, 40*4(t0) // Store fs1
fsw f18, 49*4(t0) // Store fs2
fsw f19, 50*4(t0) // Store fs3
fsw f20, 51*4(t0) // Store fs4
fsw f21, 52*4(t0) // Store fs5
fsw f22, 53*4(t0) // Store fs6
fsw f23, 54*4(t0) // Store fs7
fsw f24, 55*4(t0) // Store fs8
fsw f25, 56*4(t0) // Store fs9
fsw f26, 57*4(t0) // Store fs10
fsw f27, 58*4(t0) // Store fs11
#elif defined(__riscv_float_abi_double)
fsd f8, 39*4(t0) // Store fs0
fsd f9, 40*4(t0) // Store fs1
fsd f18, 49*4(t0) // Store fs2
fsd f19, 50*4(t0) // Store fs3
fsd f20, 51*4(t0) // Store fs4
fsd f21, 52*4(t0) // Store fs5
fsd f22, 53*4(t0) // Store fs6
fsd f23, 54*4(t0) // Store fs7
fsd f24, 55*4(t0) // Store fs8
fsd f25, 56*4(t0) // Store fs9
fsd f26, 57*4(t0) // Store fs10
fsd f27, 58*4(t0) // Store fs11
#endif
_tx_thread_preempt_skip_fp_restore:
/* Store standard preserved registers. */
sw x9, 11*4(t0) // Store s1
sw x18, 10*4(t0) // Store s2
sw x19, 9*4(t0) // Store s3
sw x20, 8*4(t0) // Store s4
sw x21, 7*4(t0) // Store s5
sw x22, 6*4(t0) // Store s6
sw x23, 5*4(t0) // Store s7
sw x24, 4*4(t0) // Store s8
sw x25, 3*4(t0) // Store s9
sw x26, 2*4(t0) // Store s10
sw x27, 1*4(t0) // Store s11
// Note: s0 is already stored!
/* Save the remaining time-slice and disable it. */
/* if (_tx_timer_time_slice)
{ */
la t0, _tx_timer_time_slice // Pickup time slice variable address
lw t2, 0(t0) // Pickup time slice
beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice
_tx_timer_time_slice = 0; */
sw t2, 24(t1) // Save current time slice
sw x0, 0(t0) // Clear global time slice
/* } */
_tx_thread_dont_save_ts:
/* Clear the current task pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
/* Return to the scheduler. */
/* _tx_thread_schedule(); */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
sw x0, 0(t0) // Clear current thread pointer
/* } */
_tx_thread_idle_system_restore:
/* Just return back to the scheduler! */
j _tx_thread_schedule // Return to scheduler
/* } */
|
