ports/risc-v64/gnu/example_build/bananapi-f3/tx_initialize_low_level.S


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139

/***************************************************************************
 * Copyright (c) 2025 10xEngineers
 *
 * This program and the accompanying materials are made available under the
 * terms of the MIT License which is available at
 * https://opensource.org/licenses/MIT.
 *
 * SPDX-License-Identifier: MIT
 **************************************************************************/

#include "csr.h"

    .section .text
    .align 4
/**************************************************************************/
/*                                                                        */
/*  FUNCTION                                               RELEASE        */
/*                                                                        */
/*    trap_entry                           		     RISC-V64/GNU         */
/*                                                           6.2.1        */
/*  AUTHOR                                                                */
/*                                                                        */
/*    Akif Ejaz, 10xEngineers                       			          */
/*                                                                        */
/*  DESCRIPTION                                                           */
/*                                                                        */
/*    This function is responsible for riscv processor trap handle        */
/*    It will do the contex save and call c trap_handler and do contex    */
/*    load 								                                  */
/*                                                                        */
/*  INPUT                                                                 */
/*                                                                        */
/*    None                                                                */
/*                                                                        */
/*  OUTPUT                                                                */
/*                                                                        */
/*    None                                                                */
/*                                                                        */
/*  CALLS                                                                 */
/*                                                                        */
/*    trap_handler                                                        */
/*                                                                        */
/*  CALLED BY                                                             */
/*                                                                        */
/*    hardware exception                                                  */
/*                                                                        */
/**************************************************************************/

    .global  trap_entry
    .extern  trap_handler
    .extern  _tx_thread_context_save
    .extern  _tx_thread_context_restore

trap_entry:
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
    addi    sp, sp, -520                       /* 65 * 8: integer + FP */
#else
    addi    sp, sp, -256                       /* 32 * 8: integer only */
#endif

    sd      x1, 224(sp)                        /* Save RA at offset 28*8 */

    call    _tx_thread_context_save

    csrr    a0, scause
    csrr    a1, sepc
    csrr    a2, stval
    addi    sp, sp, -8
    sd      ra, 0(sp)
    call    trap_handler
    ld      ra, 0(sp)
    addi    sp, sp, 8

    call    _tx_thread_context_restore
    /* never returns */
_trap_err:
    wfi
    j       _trap_err

    .section .text
/**************************************************************************/
/*                                                                        */
/*  FUNCTION                                               RELEASE        */
/*                                                                        */
/*    _tx_initialize_low_level                  RISC-V64/GNU              */
/*                                                                        */
/*  DESCRIPTION                                                           */
/*                                                                        */
/*    This function is responsible for any low-level processor            */
/*    initialization, including setting up interrupt vectors, setting     */
/*    up a periodic timer interrupt source, saving the system stack       */
/*    pointer for use in ISR processing later, and finding the first      */
/*    available RAM memory address for tx_application_define.             */
/*                                                                        */
/**************************************************************************/

    .global  _tx_initialize_low_level
    .weak    _tx_initialize_low_level
    .extern  _end
    .extern  board_init
    .extern  trap_entry
    .extern  _tx_thread_system_stack_ptr
    .extern  _tx_initialize_unused_memory

_tx_initialize_low_level:
    la      t0, _tx_thread_system_stack_ptr
    sd      sp, 0(t0)                                 /* Save system stack */

    la      t0, _end
    la      t1, _tx_initialize_unused_memory
    sd      t0, 0(t1)                                 /* First free address */

    /* Disable global S-mode interrupts during early init. */
    li      t0, SSTATUS_SIE
    csrrc   zero, sstatus, t0

    /* Set SPIE = 1 so SRET re-enables interrupts. */
    li      t0, SSTATUS_SPIE
    csrrs   zero, sstatus, t0

    /* Enable S-mode timer and external interrupts. */
    li      t0, (SIE_STIE | SIE_SEIE)
    csrrs   zero, sie, t0

#ifdef __riscv_flen
    li      t0, SSTATUS_FS
    csrrs   zero, sstatus, t0
    fscsr   x0
#endif

    addi    sp, sp, -8
    sd      ra, 0(sp)
    call    board_init
    ld      ra, 0(sp)
    addi    sp, sp, 8

    la      t0, trap_entry
    csrw    stvec, t0
    ret