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/***************************************************************************
* Copyright (c) 2026 Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* AI Disclosure: This file was largely AI-generated by Claude Code (Opus 5.5).
* The AI-generated portions may be considered public domain (CC0-1.0)
* and not subject to the project's licence. The human contributor has
* reviewed and verified that the code is correct.
*
* SPDX-License-Identifier: MIT and CC0-1.0
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
/* Erbium PLIC, RISC-V PLIC 1.0. Each hart has two contexts, machine mode
first, so hart h uses context 2h.
The silicon hardwires source priorities to 1 and context thresholds to
0, so an enabled, pending source always interrupts. The et-platform
simulator implements them as writable registers that reset to 0, which
masks every source, so plic_init() programs the silicon values. There is
no priority control beyond that.
Sources: 1 MRAM, 2 QSPI, 3 UART, 4 system register, 5 xSPI, 6 GPIO. */
#define PLIC 0xA0000000UL
#define PLIC_PRIORITY(irqno) (PLIC + (unsigned long)(irqno) * 4UL)
#define PLIC_MENABLE(hart) (PLIC + 0x2000UL + (hart) * 0x100UL)
#define PLIC_MTHRESHOLD(hart) (PLIC + 0x200000UL + (hart) * 0x2000UL)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004UL + (hart) * 0x2000UL)
#define PLIC_MCOMPLETE(hart) PLIC_MCLAIM(hart)
#define PLIC_NUM_SOURCES 6
#define MAX_CALLBACK_NUM (PLIC_NUM_SOURCES + 1)
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif /* RISCV_PLIC_H */
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