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authorzhiqiang <[email protected]>2025-09-05 09:57:38 +0800
committerzhiqiang <[email protected]>2025-09-05 09:57:38 +0800
commit3b983cb3e97e55c38959b7cf92c8fd65ca118095 (patch)
tree6abb9b846e8f480e90796a54acfc875f334a6523
parentf6ca80ab13997d8fdee084d218c22ae15d734e2a (diff)
the family name error of at32 has been corrected
-rw-r--r--docs/reference/boards.rst2
-rw-r--r--hw/bsp/at32f402_405/family.c6
2 files changed, 6 insertions, 2 deletions
diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index d984b3529..a8d73de5f 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -41,7 +41,7 @@ at_start_f413 AT-START-F413 at32f413 https://www.arterychip.com/en/pro
at_start_f415 AT-START-F415 at32f415 https://www.arterychip.com/en/product/AT32F415.jsp
at_start_f423 AT-START-F423 at32f423 https://www.arterychip.com/en/product/AT32F423.jsp
at_start_f425 AT-START-F425 at32f425 https://www.arterychip.com/en/product/AT32F425.jsp
-at_start_f435 AT-START-F435 at32f435_435 https://www.arterychip.com/en/product/AT32F435.jsp
+at_start_f435 AT-START-F435 at32f435_437 https://www.arterychip.com/en/product/AT32F435.jsp
at_start_f437 AT-START-F437 at32f435_437 https://www.arterychip.com/en/product/AT32F437.jsp
============== ============== ============= ================================================== ======
diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c
index 6b69c0157..cb5987cd4 100644
--- a/hw/bsp/at32f402_405/family.c
+++ b/hw/bsp/at32f402_405/family.c
@@ -163,7 +163,11 @@ void usb_clock48m_select(usb_clk48_s clk_s)
void usb_gpio_config(void)
{
- /*if needed*/
+ /* When the USB clock is enabled, the hardware will automatically
+ configure the pins; but other special pins that need to be used,
+ such as the pins used to detect VBUS or the pins that output the
+ SOF signal, still need to be configured separately, and these pins
+ are usually not required */
}
/**