diff options
| author | hathach <[email protected]> | 2023-07-07 16:24:22 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2023-07-07 16:24:22 +0700 |
| commit | 88478a9d052edc364561da39382faef72f937ecb (patch) | |
| tree | 05fa8d9e326140c26c10aa3e974bae10e615d8da | |
| parent | e0f1ba8b0e9cf46fabcddc72a61d5515df424edf (diff) | |
add PORT selection for makefile
| -rw-r--r-- | hw/bsp/ra/boards/ra6m5_ek/board.mk | 3 | ||||
| -rw-r--r-- | hw/bsp/ra/family.cmake | 2 | ||||
| -rw-r--r-- | hw/bsp/ra/family.mk | 12 | ||||
| -rw-r--r-- | src/portable/renesas/rusb2/dcd_rusb2.c | 4 |
4 files changed, 20 insertions, 1 deletions
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk index 567908b63..a5c933764 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.mk +++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk @@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5 # For flash-jlink target JLINK_DEVICE = R7FA6M5BH +# Port 1 is highspeed +PORT ?= 1 + flash: flash-jlink diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index eb2d4958f..f09e86a72 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS RA CACHE INTERNAL "") +set(FAMILY_MCUS RAXXX CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index b6e1bb0ae..f5097460a 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk +PORT ?= 0 + CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ + -DBOARD_TUD_RHPORT=$(PORT) \ -Wno-error=undef \ -Wno-error=strict-prototypes \ -Wno-error=cast-align \ @@ -15,6 +19,14 @@ CFLAGS += \ -nostartfiles \ -ffreestanding +ifeq ($(PORT), 1) + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + $(info "Using PORT 1 HighSpeed") +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + $(info "Using PORT 0 FullSpeed") +endif + SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3d3e52bfa..17d22f696 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo // Highspeed FIFO is 32-bit if ( is_highspeed_regbase(rusb) ) { + // TODO 32-bit access for better performance ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); }else { @@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) { (void) rusb; + + // TODO 16/32-bit access for better performance + uint8_t *p = (uint8_t*)buf; volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; |