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authorhathach <[email protected]>2023-10-27 17:40:53 +0700
committerhathach <[email protected]>2023-10-27 17:40:53 +0700
commit9cba9a753b2d8a8c06f1dacc5c16d656397f5d79 (patch)
treea8cfa51408b3e4fa8e45c8218a6230f0e7780d8c
parenta2390802f83e7c98cba7ca0bb816c89649661045 (diff)
update s3 devkitm with max3421 pin following metro s3, check max3421 version to make sure it is valid
-rw-r--r--.idea/cmake.xml2
-rw-r--r--hw/bsp/espressif/boards/espressif_s3_devkitm/board.h6
-rw-r--r--src/portable/analog/max3421/hcd_max3421.c5
3 files changed, 7 insertions, 6 deletions
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 88e0e27ad..9f17c805c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -16,7 +16,7 @@
</envs>
</ADDITIONAL_GENERATION_ENVIRONMENT>
</configuration>
- <configuration PROFILE_NAME="esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm">
+ <configuration PROFILE_NAME="espressif_s3_devkitm" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DMAX3421_HOST=1 -DLOG=2">
<ADDITIONAL_GENERATION_ENVIRONMENT>
<envs>
<env name="ESPBAUD" value="1500000" />
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index 4b4151e72..a319fbc61 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -38,9 +38,9 @@
// SPI for USB host shield
#define MAX3421_SPI_HOST SPI2_HOST
-#define MAX3421_SCK_PIN 36
-#define MAX3421_MOSI_PIN 35
-#define MAX3421_MISO_PIN 37
+#define MAX3421_SCK_PIN 39
+#define MAX3421_MOSI_PIN 42
+#define MAX3421_MISO_PIN 21
#define MAX3421_CS_PIN 15
#define MAX3421_INTR_PIN 14
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 787c1e511..4665c1b06 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -433,8 +433,9 @@ bool hcd_init(uint8_t rhport) {
reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
// V1 is 0x01, V2 is 0x12, V3 is 0x13
-// uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-// TU_LOG2_HEX(revision);
+ uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+ TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
+ TU_LOG2_HEX(revision);
// reset
reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);