diff options
| author | Cédric Berger <[email protected]> | 2025-12-26 17:25:25 +0100 |
|---|---|---|
| committer | Cédric Berger <[email protected]> | 2025-12-26 17:25:25 +0100 |
| commit | b3dd0a113adefd1493dbd1417ece346528951b1d (patch) | |
| tree | a13887d8ba778f5cc46c4f6221000d8f7f640375 | |
| parent | b209b177ecc41ca733a4420c60fb7c1170be2342 (diff) | |
Do not randomly include stm32h7xx.h
Enable D-Cache unless we're compiling for the M4 core of a dual-core H7 mcu by directly testing CORE_CM4
| -rw-r--r-- | src/common/tusb_mcu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 55f7e0b7c..ebe486e40 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -245,13 +245,12 @@ #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #elif TU_CHECK_MCU(OPT_MCU_STM32H7) - #include "stm32h7xx.h" #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 9 - #if __CORTEX_M == 7 + #ifndef CORE_CM4 // Enable dcache if DMA is enabled #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE |