diff options
| author | hathach <[email protected]> | 2023-07-18 15:13:58 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2023-07-18 15:13:58 +0700 |
| commit | b56c4fe945ec61d13c3480fe7e2e44bb3424181a (patch) | |
| tree | 09f7bd2116bce4533d21af09091abfa204fe5f6f | |
| parent | 0f53e746ffa21b6186809b2b896ddc74d38e9058 (diff) | |
| parent | 6798e7e059d81268f04a3e206e6c4354b295dbf1 (diff) | |
Merge branch 'master' into renesas_ra_hs_rebased
48 files changed, 13664 insertions, 27 deletions
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml index 038c87421..0e7e2befc 100644 --- a/.idea/runConfigurations/mcx947.xml +++ b/.idea/runConfigurations/mcx947.xml @@ -1,5 +1,5 @@ <component name="ProjectRunConfigurationManager"> - <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MCXN947_M33_0" -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc"> + <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MCXN947_M33_0" -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc"> <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD"> <debugger kind="GDB" isBundled="true" /> </custom-gdb-server> diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml index 6fabd8561..a39f1f684 100644 --- a/.idea/runConfigurations/rt1010.xml +++ b/.idea/runConfigurations/rt1010.xml @@ -1,6 +1,6 @@ <component name="ProjectRunConfigurationManager"> - <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MIMXRT1011xxx5A" -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc"> - <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD"> + <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MIMXRT1011xxx5A" -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc"> + <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD"> <debugger kind="GDB" isBundled="true" /> </custom-gdb-server> <method v="2"> diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake index 3ba95bf2c..99681ab12 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT MIMXRT1011) -set(JLINK_DEVICE MIMXRT1011DAE5A) +set(JLINK_DEVICE MIMXRT1011xxx5A) set(PYOCD_TARGET mimxrt1010) set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk index 89a459958..b845194c2 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk @@ -5,7 +5,7 @@ MCU_VARIANT = MIMXRT1011 LD_FILE = $(BOARD_PATH)/$(BOARD).ld # For flash-jlink target -JLINK_DEVICE = MIMXRT1011DAE5A +JLINK_DEVICE = MIMXRT1011xxx5A # For flash-pyocd target PYOCD_TARGET = mimxrt1010 diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c new file mode 100644 index 000000000..1b28b668a --- /dev/null +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c @@ -0,0 +1,340 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1010-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} +settings: +- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5'} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} +- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Xbar1); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); +#endif + /* Disable ADC_ACLK_EN clock gate. */ + CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; + /* Set ADC_ACLK_PODF. */ + CLOCK_SetDiv(kCLOCK_AdcDiv, 11); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h new file mode 100644 index 000000000..119fd94bd --- /dev/null +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex new file mode 100644 index 000000000..606ec2cfc --- /dev/null +++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex @@ -0,0 +1,692 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1011xxxxx</processor> + <package>MIMXRT1011DAE5A</package> + <board>MIMXRT1010-EVK</board> + <board_revision>A</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + <power_domains> + <power_domain name="NVCC_GPIO" value="3.3"/> + </power_domains> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPSPI1" description="Peripheral LPSPI1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPSPI1" signal="SDI" pin_num="57" pin_signal="GPIO_AD_03"/> + <pin peripheral="LPSPI1" signal="SDO" pin_num="56" pin_signal="GPIO_AD_04"/> + <pin peripheral="LPSPI1" signal="SCK" pin_num="52" pin_signal="GPIO_AD_06"/> + <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"/> + <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"/> + <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"/> + <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"/> + <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"/> + <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"/> + </pins> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/> + <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="65" pin_signal="GPIO_SD_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="66" pin_signal="GPIO_SD_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="68" pin_signal="GPIO_SD_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="67" pin_signal="GPIO_SD_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="64" pin_signal="GPIO_SD_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="69" pin_signal="GPIO_SD_06"/> + </pins> + </function> + <function name="BOARD_InitLEDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="gpio_interrupt" value="kGPIO_NoIntmode"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Enable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitCOMBO_SENSORPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="12" pin_signal="GPIO_01"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> + <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/> + <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.5.1</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="igpio not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Unsupported version of the igpio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.0.1</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="LPSPI Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="Unsupported version of the LPSPI Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="greaterOrEqual"> + <data type="Version">2.0.3</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sck" description="Signal serial clock is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sin" description="Signal serial data input is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sout" description="Signal serial data output is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="ClockOutput" resourceId="LPSPI_CLK_ROOT" description="LPSPI_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/> + </config_set> + <config_set name="interrupt_vector"/> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + <setting name="enable_irq_comb_16_31" value="false"/> + <struct name="gpio_interrupt_comb_16_31"> + <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="1f9167f9-b5d4-4014-bb88-164f5cb5df38" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + <instance name="LPSPI1" uuid="de6f91ec-e184-4998-995c-9c22586a5529" type="lpspi" type_id="lpspi_6e21a1e0a09f0a012d683c4f91752db8" mode="polling" peripheral="LPSPI1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="main"> + <setting name="mode" value="kLPSPI_Master"/> + <setting name="clockSource" value="LpspiClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="master"> + <setting name="baudRate" value="400000"/> + <setting name="bitsPerFrame" value="8"/> + <setting name="cpol" value="kLPSPI_ClockPolarityActiveHigh"/> + <setting name="cpha" value="kLPSPI_ClockPhaseFirstEdge"/> + <setting name="direction" value="kLPSPI_MsbFirst"/> + <setting name="pcsToSckDelayInNanoSec" value="1000"/> + <setting name="lastSckToPcsDelayInNanoSec" value="1000"/> + <setting name="betweenTransferDelayInNanoSec" value="1000"/> + <setting name="whichPcs" value="kLPSPI_Pcs0"/> + <setting name="pcsActiveHighOrLow" value="kLPSPI_PcsActiveLow"/> + <setting name="pinCfg" value="kLPSPI_SdiInSdoOut"/> + <setting name="dataOutConfig" value="kLpspiDataOutRetained"/> + </struct> + <setting name="set_FifoWaterMarks" value="false"/> + <struct name="fifoWaterMarks"> + <setting name="txWatermark" value="0"/> + <setting name="rxWatermark" value="0"/> + </struct> + <setting name="allPcsPolarityEnable" value="false"/> + <struct name="allPcsPolarity"> + <setting name="kLPSPI_Pcs1Active" value="kLPSPI_PcsActiveLow"/> + <setting name="kLPSPI_Pcs2Active" value="kLPSPI_PcsActiveLow"/> + <setting name="kLPSPI_Pcs3Active" value="kLPSPI_PcsActiveLow"/> + </struct> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="452cb7cf-ac6a-4f29-a940-5f049b272fb1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="be6880f0-7c2d-4331-bd40-2163fb383fd7" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="0f82c647-4c11-4163-87a4-aca908bb012c" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="18436376-474a-425e-81c0-9aa48fcbccd6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="5501650f-8266-4cab-aadb-7799f5079dfb" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake index 3ba95bf2c..99681ab12 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT MIMXRT1011) -set(JLINK_DEVICE MIMXRT1011DAE5A) +set(JLINK_DEVICE MIMXRT1011xxx5A) set(PYOCD_TARGET mimxrt1010) set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010) diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk index 17dc01cd9..488a56fdc 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk @@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY MCU_VARIANT = MIMXRT1011 # For flash-jlink target -JLINK_DEVICE = MIMXRT1011DAE5A +JLINK_DEVICE = MIMXRT1011xxx5A # For flash-pyocd target PYOCD_TARGET = mimxrt1010 diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c new file mode 100644 index 000000000..6cd18c8c2 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c @@ -0,0 +1,351 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1011xxxxx +package_id: MIMXRT1011DAE5A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1010-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#include "fsl_iomuxc.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ADC_ALT_CLK.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY_CLK.outFreq, value: 480 MHz} +settings: +- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true} +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5'} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK} +- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Xbar1); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); + CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0); +#endif + /* Disable ADC_ACLK_EN clock gate. */ + CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK; + /* Set ADC_ACLK_PODF. */ + CLOCK_SetDiv(kCLOCK_AdcDiv, 11); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */ + /* Set Pll3 SW clock source to use the USB1 PLL output. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Set safe value of the AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 1); + /* Set periph clock2 clock source to use the PLL3_SW_CLK. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h new file mode 100644 index 000000000..119fd94bd --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h @@ -0,0 +1,97 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex new file mode 100644 index 000000000..606ec2cfc --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex @@ -0,0 +1,692 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1011xxxxx</processor> + <package>MIMXRT1011DAE5A</package> + <board>MIMXRT1010-EVK</board> + <board_revision>A</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + <power_domains> + <power_domain name="NVCC_GPIO" value="3.3"/> + </power_domains> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPSPI1" description="Peripheral LPSPI1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPSPI1" signal="SDI" pin_num="57" pin_signal="GPIO_AD_03"/> + <pin peripheral="LPSPI1" signal="SDO" pin_num="56" pin_signal="GPIO_AD_04"/> + <pin peripheral="LPSPI1" signal="SCK" pin_num="52" pin_signal="GPIO_AD_06"/> + <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"/> + <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"/> + <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"/> + <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"/> + <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"/> + <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"/> + </pins> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/> + <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="65" pin_signal="GPIO_SD_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="66" pin_signal="GPIO_SD_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="68" pin_signal="GPIO_SD_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="67" pin_signal="GPIO_SD_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="64" pin_signal="GPIO_SD_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="69" pin_signal="GPIO_SD_06"/> + </pins> + </function> + <function name="BOARD_InitLEDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="gpio_interrupt" value="kGPIO_NoIntmode"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Enable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitCOMBO_SENSORPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="12" pin_signal="GPIO_01"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> + <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/> + <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.5.1</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="igpio not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Unsupported version of the igpio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="equivalent"> + <data type="Version">2.0.1</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="LPSPI Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals"> + <feature name="enabled" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="Unsupported version of the LPSPI Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals"> + <feature name="version" evaluation="greaterOrEqual"> + <data type="Version">2.0.3</data> + </feature> + </dependency> + </dependencies> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation="equal"> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sck" description="Signal serial clock is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sin" description="Signal serial data input is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sout" description="Signal serial data output is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals"> + <feature name="routed" evaluation=""> + <data type="Boolean">true</data> + </feature> + </dependency> + <dependency resourceType="ClockOutput" resourceId="LPSPI_CLK_ROOT" description="LPSPI_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals"> + <feature name="frequency" evaluation="greaterThan"> + <data type="Frequency" unit="Hz">0</data> + </feature> + </dependency> + </dependencies> + <instances> + <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/> + </config_set> + <config_set name="interrupt_vector"/> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + <setting name="enable_irq_comb_16_31" value="false"/> + <struct name="gpio_interrupt_comb_16_31"> + <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="1f9167f9-b5d4-4014-bb88-164f5cb5df38" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + <instance name="LPSPI1" uuid="de6f91ec-e184-4998-995c-9c22586a5529" type="lpspi" type_id="lpspi_6e21a1e0a09f0a012d683c4f91752db8" mode="polling" peripheral="LPSPI1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="main"> + <setting name="mode" value="kLPSPI_Master"/> + <setting name="clockSource" value="LpspiClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="master"> + <setting name="baudRate" value="400000"/> + <setting name="bitsPerFrame" value="8"/> + <setting name="cpol" value="kLPSPI_ClockPolarityActiveHigh"/> + <setting name="cpha" value="kLPSPI_ClockPhaseFirstEdge"/> + <setting name="direction" value="kLPSPI_MsbFirst"/> + <setting name="pcsToSckDelayInNanoSec" value="1000"/> + <setting name="lastSckToPcsDelayInNanoSec" value="1000"/> + <setting name="betweenTransferDelayInNanoSec" value="1000"/> + <setting name="whichPcs" value="kLPSPI_Pcs0"/> + <setting name="pcsActiveHighOrLow" value="kLPSPI_PcsActiveLow"/> + <setting name="pinCfg" value="kLPSPI_SdiInSdoOut"/> + <setting name="dataOutConfig" value="kLpspiDataOutRetained"/> + </struct> + <setting name="set_FifoWaterMarks" value="false"/> + <struct name="fifoWaterMarks"> + <setting name="txWatermark" value="0"/> + <setting name="rxWatermark" value="0"/> + </struct> + <setting name="allPcsPolarityEnable" value="false"/> + <struct name="allPcsPolarity"> + <setting name="kLPSPI_Pcs1Active" value="kLPSPI_PcsActiveLow"/> + <setting name="kLPSPI_Pcs2Active" value="kLPSPI_PcsActiveLow"/> + <setting name="kLPSPI_Pcs3Active" value="kLPSPI_PcsActiveLow"/> + </struct> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="452cb7cf-ac6a-4f29-a940-5f049b272fb1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="be6880f0-7c2d-4331-bd40-2163fb383fd7" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="0f82c647-4c11-4163-87a4-aca908bb012c" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="18436376-474a-425e-81c0-9aa48fcbccd6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="5501650f-8266-4cab-aadb-7799f5079dfb" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c new file mode 100644 index 000000000..ae1aa7fb1 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c @@ -0,0 +1,357 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1015xxxxx +package_id: MIMXRT1015DAF5A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1015-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '1', locked: true} +- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} +- {id: CCM.SEMC_PODF.scale, value: '2'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 0); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 1); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h new file mode 100644 index 000000000..2acdb16a7 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h @@ -0,0 +1,100 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex new file mode 100644 index 000000000..431a59af7 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex @@ -0,0 +1,576 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1015xxxxx</processor> + <package>MIMXRT1015DAF5A</package> + <board>MIMXRT1015-EVK</board> + <board_revision>B</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains> + <power_domain name="NVCC_GPIO" value="3.3"/> + </power_domains> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07"/> + <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="12" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="11" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="9" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="10" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="13" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/> + </pins> + </function> + <function name="BOARD_InitLEDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01"> + <pin_features> + <pin_feature name="direction" value="OUTPUT"/> + <pin_feature name="gpio_init_state" value="true"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitBUTTONPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="GPIO2" signal="gpio_io, 09" pin_num="1" pin_signal="GPIO_EMC_09"> + <pin_features> + <pin_feature name="direction" value="INPUT"/> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_4"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Enable"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitCOMBO_SENSORPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPI2C1" signal="SCL" pin_num="53" pin_signal="GPIO_AD_B1_14"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="52" pin_signal="GPIO_AD_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + <pin_feature name="software_input_on" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + </pin_features> + </pin> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/> + <setting id="CCM.CLKO2_SEL.sel" value="CCM.LPI2C_CLK_ROOT" locked="false"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/> + <setting id="CCM.SEMC_PODF.scale" value="2" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>N/A</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="57fc488c-a9f7-4a03-8ab3-5d2a3fd16a50" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="DEBUG_UART" uuid="600d7aee-5a2d-4373-9763-ce007b981c15" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="COMBO_SENSOR" uuid="96f9e552-25e5-434a-9454-5cf9e614733d" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="USER_LED" uuid="5592aac0-ced9-4284-88a8-bbeb5083a92f" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO3" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO3_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + <setting name="enable_irq_comb_16_31" value="false"/> + <struct name="gpio_interrupt_comb_16_31"> + <setting name="IRQn" value="GPIO3_Combined_16_31_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="USER_BUTTON" uuid="e7774953-3606-41b8-8b72-6e09025369e0" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_gpio"> + <setting name="enable_irq_comb_0_15" value="false"/> + <struct name="gpio_interrupt_comb_0_15"> + <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + <setting name="enable_irq_comb_16_31" value="false"/> + <struct name="gpio_interrupt_comb_16_31"> + <setting name="IRQn" value="GPIO2_Combined_16_31_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="0329fbca-00e5-4ec4-9f79-3cb65a7b267a" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="59cf1b09-8396-4bf9-bed6-03d5457c292f" type_id="system_54b53072540eeeb8f8e9343e71f28176"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="7d589e9f-7522-408c-b7c8-42770920766f" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="e9da5e16-1f55-49be-87ec-af8cfd4a4105" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="9dc7a034-9408-4852-9990-a713693635ee" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="28ec81a8-d7ea-4363-9330-20b877c481f6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="774dd0a0-63ed-4846-b9d7-dfd082d810e3" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="77cd333e-4adc-4c6e-8b18-bbe349d78182" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>N/A</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake index 1696dc987..39c94147c 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT MIMXRT1021) -set(JLINK_DEVICE MIMXRT1021DAG5A) +set(JLINK_DEVICE MIMXRT1021xxx5A) set(PYOCD_TARGET mimxrt1020) set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020) diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk index b15da1b67..e269c8ac5 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk @@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A MCU_VARIANT = MIMXRT1021 # For flash-jlink target -JLINK_DEVICE = MIMXRT1021DAG5A +JLINK_DEVICE = MIMXRT1021xxx5A # For flash-pyocd target PYOCD_TARGET = mimxrt1020 diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c new file mode 100644 index 000000000..764042928 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c @@ -0,0 +1,421 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1021xxxxx +package_id: MIMXRT1021DAG5A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1020-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true} +- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 0); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 2); +#endif + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h new file mode 100644 index 000000000..d678a4f66 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h @@ -0,0 +1,108 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex new file mode 100644 index 000000000..4ddaaed77 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex @@ -0,0 +1,597 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1020-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1021xxxxx</processor> + <package>MIMXRT1021DAG5A</package> + <board>MIMXRT1020-EVK</board> + <board_revision>A3</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <external_user_signals> + <properties/> + </external_user_signals> + <power_domains> + <power_domain name="NVCC_GPIO" value="3.3"/> + </power_domains> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/> + <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/> + <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/> + <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/> + <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/> + <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/> + <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> + <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/dcd.c" update_enabled="true"/> + <file path="board/dcd.h" update_enabled="true"/> + </generated_project_files> + <dcdx_profile> + <processor_version>13.0.2</processor_version> + <output_format>c_array</output_format> + </dcdx_profile> + <dcdx_configurations> + <dcdx_configuration name="Device_configuration"> + <description></description> + <options/> + <command_groups/> + </dcdx_configuration> + </dcdx_configurations> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="d0b30ebd-b05e-42b2-8e94-40b1625c2dba" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableTimerSync" value="true"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="27a94726-61ef-42ac-b517-d1eda3853dfe" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="e2a4cccd-cb23-4714-8c90-022fcf6146e8" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="bd191d83-2cb2-40ed-a718-47b39d772006" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="d097438f-179b-43e0-b37c-aee31212cebd" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="d84400f7-fd84-4466-908a-04abca190ef6" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="4f0123a9-0338-4076-b275-b49951642704" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="18150193-6d2b-469f-88e5-4908669bf3e5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="602159e8-d65b-45d3-b63b-cd33be549134" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="eb963b89-5367-4d86-8885-82b4b8cff735" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + <common name="common" version="1.0" enabled="true" update_project_code="true"> + <core name="core0" role="primary" project_name="Project"/> + </common> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake index 7011fec9b..45487d148 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT MIMXRT1024) -set(JLINK_DEVICE MIMXRT1024DAG5A) +set(JLINK_DEVICE MIMXRT1024xxx5A) set(PYOCD_TARGET mimxrt1024) set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK) diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk index 92209992d..3c325cc93 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk @@ -5,7 +5,7 @@ MCU_VARIANT = MIMXRT1024 CFLAGS += -Wno-error=array-bounds # For flash-jlink target -JLINK_DEVICE = MIMXRT1024DAG5A +JLINK_DEVICE = MIMXRT1024xxx5A # For flash-pyocd target PYOCD_TARGET = mimxrt1024 diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c new file mode 100644 index 000000000..ba0cadafa --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c @@ -0,0 +1,421 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1024xxxxx +package_id: MIMXRT1024DAG5A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1024-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK} +- {id: CCM.IPG_PODF.scale, value: '4'} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true} +- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6} +- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = + { + .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */ + .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */ + .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */ + .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 0); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 2); +#endif + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 18); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Enet PLL. */ + CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h new file mode 100644 index 000000000..d678a4f66 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h @@ -0,0 +1,108 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex new file mode 100644 index 000000000..2aa55a604 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex @@ -0,0 +1,503 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1024-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1024xxxxx</processor> + <package>MIMXRT1024DAG5A</package> + <board>MIMXRT1024-EVK</board> + <board_revision>B1</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains> + <power_domain name="NVCC_GPIO" value="3.3"/> + </power_domains> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/> + <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/> + <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/> + <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/> + <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/> + <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/> + <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/> + <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/dcd.c" update_enabled="true"/> + <file path="board/dcd.h" update_enabled="true"/> + </generated_project_files> + <dcdx_profile> + <processor_version>13.0.2</processor_version> + <output_format>c_array</output_format> + </dcdx_profile> + <dcdx_configurations> + <dcdx_configuration name="Device_configuration"> + <description></description> + <options/> + <command_groups/> + </dcdx_configuration> + </dcdx_configurations> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="NVIC" uuid="096e7e36-6917-481a-a4c5-06822cfc2da4" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="5dc935cc-5865-4d50-bac9-89ad440a12ee" type_id="system_54b53072540eeeb8f8e9343e71f28176"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="c2fe99b8-bf9b-437f-9446-a35000b06679" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7"> + <config_set_global name="global_messages"/> + </component> + <component name="generic_uart" uuid="eca93ea1-cadf-4247-bfdc-08769ef8ed12" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="fdf82c69-a73f-4f32-9699-457260453bc6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="gpio_adapter_common" uuid="af80d7a8-d163-4a6f-839d-0ce2b15abffd" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="uart_cmsis_common" uuid="dca6ee55-a78d-4884-99bd-4f821b552213" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="4c34638b-b184-4e9d-8a81-5f3a1287180a" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>N/A</processor_version> + </tee_profile> + </tee> + <common name="common" version="1.0" enabled="true" update_project_code="true"> + <core name="core0" role="primary" project_name="Project"/> + </common> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk index 9fd229105..60aa1e28f 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk @@ -1,6 +1,8 @@ CFLAGS += -DCPU_MIMXRT1052DVL6B MCU_VARIANT = MIMXRT1052 +JLINK_DEVICE = MIMXRT1052xxxxB + # For flash-pyocd target PYOCD_TARGET = mimxrt1050 diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c new file mode 100644 index 000000000..9738c6350 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c @@ -0,0 +1,495 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 40, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h new file mode 100644 index 000000000..6b4264bf2 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h @@ -0,0 +1,119 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex new file mode 100644 index 000000000..c0a5b5660 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex @@ -0,0 +1,1001 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="IMXRT1050-EVKB" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="789fd1d3-821c-40a6-b04d-44ccc5a5d158" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1052xxxxB</processor> + <package>MIMXRT1052DVL6B</package> + <board>IMXRT1050-EVKB</board> + <board_revision>A</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="CSX, 0" pin_num="C7" pin_signal="GPIO_EMC_41"/> + </pins> + </function> + <function name="BOARD_InitCSIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/> + <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/> + <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/> + <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/> + <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/> + <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/> + <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/> + <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/> + <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/> + <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/> + <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SCL"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SDA"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/> + </pins> + </function> + <function name="BOARD_InitLCDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/> + <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/> + </pins> + </function> + <function name="BOARD_InitHyperFlashPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitHyperFlashPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA3" pin_num="L5" pin_signal="GPIO_SD_B1_00"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA2" pin_num="M5" pin_signal="GPIO_SD_B1_01"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA1" pin_num="M3" pin_signal="GPIO_SD_B1_02"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA0" pin_num="M4" pin_signal="GPIO_SD_B1_03"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_B_SCLK" pin_num="P2" pin_signal="GPIO_SD_B1_04"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/> + <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="3" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM.PLL3_SW_CLK_SEL" locked="false"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/> + <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL5.div" value="40" locked="false"/> + <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/> + <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="false"/> + <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/> + <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="false"/> + <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="a7525270-2da6-4556-8d91-4ab9d0edc0e2" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="cb1fcaec-81fe-4d3e-a079-a7d2819d6075" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN2_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableTimerSync" value="true"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="CSI" uuid="da865a46-3511-4001-8bb0-5249c52b0e4d" type="csi" type_id="csi_b2cf1faba8074e676ac4be93ec552c5a" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_csi" quick_selection="QuickSelection1"> + <struct name="clockConfig"> + <setting name="clockSource" value="BusInterfaceClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="masterClockSource" value="CsiClock"/> + <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/> + </struct> + <struct name="config"> + <setting name="format" value="RGB565"/> + <setting name="i_width" value="320"/> + <setting name="i_height" value="240"/> + <setting name="dataBus" value="kCSI_DataBus8Bit"/> + <setting name="workMode" value="kCSI_GatedClockMode"/> + <setting name="useExtVsync" value="true"/> + <set name="polarityFlags"> + <selected/> + </set> + <struct name="buffers_config"> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufCount" value="4"/> + <setting name="bufferAlign" value="64"/> + </struct> + </struct> + <struct name="interruptsCfg"> + <setting name="isInterruptEnabled" value="false"/> + <set name="interruptSources"> + <selected/> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="CSI_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="CSI_LPI2C" uuid="47051ef3-2c25-4648-8f79-4ae87cd12674" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="64741c26-6183-46d0-8bfe-02a92aa90e05" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="LCD" uuid="8bf370a5-e797-45e8-b8c4-629c84c62843" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_elcdif"> + <struct name="config"> + <setting name="panelWidthInt" value="480"/> + <setting name="panelHeightInt" value="272"/> + <setting name="hsw" value="41"/> + <setting name="hfp" value="4"/> + <setting name="hbp" value="8"/> + <setting name="vsw" value="10"/> + <setting name="vfp" value="4"/> + <setting name="vbp" value="2"/> + <setting name="frameRate" value="60 Hz"/> + <setting name="clockSource" value="LcdIfClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="polarityFlags_st"> + <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/> + <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/> + <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/> + <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/> + </struct> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufferAlign" value="64"/> + <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/> + <setting name="dataBus" value="kELCDIF_DataBus16Bit"/> + <setting name="enablePxpHandShake" value="false"/> + <setting name="start" value="false"/> + </struct> + <setting name="isInterruptEnabled" value="true"/> + <set name="elcdifInterruptSources"> + <selected> + <id>kELCDIF_CurFrameDoneInterruptEnable</id> + </selected> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="LCDIF_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="687e3f12-1330-4ff9-8138-6aaf372d3e22" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="17c5d0d5-726a-40f6-a434-b121e9798a55" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="4a40b9b1-b64b-41b7-8ba7-728cda5039cd" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="c8d21d99-3f5e-47f2-aba7-0588ad4c2132" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="dfa0bda9-5863-49b3-9482-3ee85a2b93f0" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="3358d4d0-14d8-4ca7-9c13-378a0dc7f9a2" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="65c68c04-c4f4-4fbc-8c15-452d53d79fe6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="99f59d06-c3df-407a-856a-22072ef95a98" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + <common name="common" version="1.0" enabled="true" update_project_code="true"> + <core name="core0" role="primary" project_name="Project"/> + </common> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c new file mode 100644 index 000000000..c55e0135a --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c @@ -0,0 +1,509 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1060-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h new file mode 100644 index 000000000..7ce24b6f4 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex new file mode 100644 index 000000000..39b3ed606 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex @@ -0,0 +1,1001 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1062xxxxA</processor> + <package>MIMXRT1062DVL6A</package> + <board>MIMXRT1060-EVK</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/> + </pins> + </function> + <function name="BOARD_InitCSIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/> + <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/> + <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/> + <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/> + <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/> + <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/> + <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/> + <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/> + <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/> + <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/> + <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SCL"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SDA"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/> + </pins> + </function> + <function name="BOARD_InitLCDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/> + <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> + <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/> + <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/> + <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/> + <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/> + <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/> + <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/> + <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/> + <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN2_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_csi" quick_selection="QuickSelection1"> + <struct name="clockConfig"> + <setting name="clockSource" value="BusInterfaceClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="masterClockSource" value="CsiClock"/> + <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/> + </struct> + <struct name="config"> + <setting name="format" value="RGB565"/> + <setting name="i_width" value="320"/> + <setting name="i_height" value="240"/> + <setting name="dataBus" value="kCSI_DataBus8Bit"/> + <setting name="workMode" value="kCSI_GatedClockMode"/> + <setting name="useExtVsync" value="true"/> + <set name="polarityFlags"> + <selected/> + </set> + <struct name="buffers_config"> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufCount" value="4"/> + <setting name="bufferAlign" value="64"/> + </struct> + </struct> + <struct name="interruptsCfg"> + <setting name="isInterruptEnabled" value="false"/> + <set name="interruptSources"> + <selected/> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="CSI_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_elcdif"> + <struct name="config"> + <setting name="panelWidthInt" value="480"/> + <setting name="panelHeightInt" value="272"/> + <setting name="hsw" value="41"/> + <setting name="hfp" value="4"/> + <setting name="hbp" value="8"/> + <setting name="vsw" value="10"/> + <setting name="vfp" value="4"/> + <setting name="vbp" value="3"/> + <setting name="frameRate" value="60 Hz"/> + <setting name="clockSource" value="LcdIfClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="polarityFlags_st"> + <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/> + <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/> + <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/> + <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/> + </struct> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufferAlign" value="64"/> + <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/> + <setting name="dataBus" value="kELCDIF_DataBus16Bit"/> + <setting name="enablePxpHandShake" value="false"/> + <setting name="start" value="false"/> + </struct> + <setting name="isInterruptEnabled" value="true"/> + <set name="elcdifInterruptSources"> + <selected> + <id>kELCDIF_CurFrameDoneInterruptEnable</id> + </selected> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="LCDIF_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c new file mode 100644 index 000000000..778ab02f2 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c @@ -0,0 +1,511 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1064xxxxA +package_id: MIMXRT1064DVL6A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1064-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); + /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h new file mode 100644 index 000000000..7ce24b6f4 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex new file mode 100644 index 000000000..5e0fc72d3 --- /dev/null +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex @@ -0,0 +1,1006 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1064xxxxA</processor> + <package>MIMXRT1064DVL6A</package> + <board>MIMXRT1064-EVK</board> + <board_revision>1</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>true</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/> + </pins> + </function> + <function name="BOARD_InitCSIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/> + <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/> + <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/> + <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/> + <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/> + <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/> + <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/> + <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/> + <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/> + <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/> + <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SCL"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SDA"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/> + </pins> + </function> + <function name="BOARD_InitLCDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/> + <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> + <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/> + <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/> + <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/> + <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD1_DIV.scale" value="16" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/> + <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/> + <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/> + <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/> + <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="1c6563a6-c68b-40e5-8828-2853c99f95fa" called_from_default_init="true" id_prefix="BOARD_" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="e311ffe2-a68e-4ccc-bab1-c97e2207c5f0" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN2_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="CSI_LPI2C" uuid="7b69310c-fa35-4379-ac89-358df9280646" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="CSI_RGB565" uuid="ae342c96-df71-41a3-8419-3cccf201c91e" type="csi" type_id="csi_20660d007fd9c28a0b6ec615663d2939" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_csi"> + <struct name="clockConfig"> + <setting name="clockSource" value="BusInterfaceClock"/> + <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/> + <setting name="masterClockSource" value="CsiClock"/> + <setting name="masterClockSourceFreq" value="BOARD_BootClockRUN"/> + </struct> + <struct name="config"> + <setting name="format" value="RGB565"/> + <setting name="i_width" value="320"/> + <setting name="i_height" value="240"/> + <setting name="dataBus" value="kCSI_DataBus8Bit"/> + <setting name="workMode" value="kCSI_GatedClockMode"/> + <setting name="useExtVsync" value="true"/> + <set name="polarityFlags"> + <selected> + <id>kCSI_HsyncActiveHigh</id> + <id>kCSI_VsyncActiveLow</id> + </selected> + </set> + <struct name="buffers_config"> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufCount" value="4"/> + <setting name="bufferAlign" value="64"/> + </struct> + </struct> + <struct name="interruptsCfg"> + <set name="interruptSources"> + <selected/> + </set> + <setting name="isInterruptEnabled" value="false"/> + <struct name="interrupt"> + <setting name="IRQn" value="CSI_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="81411659-def5-4dbf-839a-d5e5f32dec0b" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t" quick_selection="QuickSelection1"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="LCD_RGB565" uuid="8c491814-4517-44d9-95de-844144e0c6b5" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_elcdif"> + <struct name="config"> + <setting name="panelWidthInt" value="480"/> + <setting name="panelHeightInt" value="272"/> + <setting name="hsw" value="41"/> + <setting name="hfp" value="4"/> + <setting name="hbp" value="8"/> + <setting name="vsw" value="10"/> + <setting name="vfp" value="4"/> + <setting name="vbp" value="2"/> + <setting name="frameRate" value="60 Hz"/> + <setting name="clockSource" value="LcdIfClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="polarityFlags_st"> + <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/> + <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/> + <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/> + <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/> + </struct> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufferAlign" value="64"/> + <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/> + <setting name="dataBus" value="kELCDIF_DataBus16Bit"/> + <setting name="enablePxpHandShake" value="false"/> + <setting name="start" value="false"/> + </struct> + <setting name="isInterruptEnabled" value="true"/> + <set name="elcdifInterruptSources"> + <selected> + <id>kELCDIF_CurFrameDoneInterruptEnable</id> + </selected> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="LCDIF_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="352dfcca-72ab-4214-bb68-9c1a927c4922" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="fe5e46a0-17b8-41e8-9cbc-ffb6f1cf78c1" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="f79f6878-69b5-4063-9007-0b8e509f7274" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="7ce8b24b-29e6-4b69-86e5-bdfd641cef44" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="ef6a8ae2-3961-4a05-a37f-d42a6a4d8a56" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="00a2a52b-0c40-4dbf-a6d0-5257cfc384e0" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="f30f7e21-6805-4236-9ab3-ff06a6013fa1" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="ea574324-8cc3-4da3-bdfc-2bdba0dfc3df" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c new file mode 100644 index 000000000..c55e0135a --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c @@ -0,0 +1,509 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1060-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h new file mode 100644 index 000000000..7ce24b6f4 --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40.mex b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex new file mode 100644 index 000000000..39b3ed606 --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex @@ -0,0 +1,1001 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1062xxxxA</processor> + <package>MIMXRT1062DVL6A</package> + <board>MIMXRT1060-EVK</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/> + </pins> + </function> + <function name="BOARD_InitCSIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/> + <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/> + <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/> + <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/> + <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/> + <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/> + <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/> + <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/> + <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/> + <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/> + <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SCL"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SDA"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/> + </pins> + </function> + <function name="BOARD_InitLCDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/> + <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> + <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/> + <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/> + <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/> + <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/> + <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/> + <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/> + <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/> + <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN2_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_csi" quick_selection="QuickSelection1"> + <struct name="clockConfig"> + <setting name="clockSource" value="BusInterfaceClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="masterClockSource" value="CsiClock"/> + <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/> + </struct> + <struct name="config"> + <setting name="format" value="RGB565"/> + <setting name="i_width" value="320"/> + <setting name="i_height" value="240"/> + <setting name="dataBus" value="kCSI_DataBus8Bit"/> + <setting name="workMode" value="kCSI_GatedClockMode"/> + <setting name="useExtVsync" value="true"/> + <set name="polarityFlags"> + <selected/> + </set> + <struct name="buffers_config"> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufCount" value="4"/> + <setting name="bufferAlign" value="64"/> + </struct> + </struct> + <struct name="interruptsCfg"> + <setting name="isInterruptEnabled" value="false"/> + <set name="interruptSources"> + <selected/> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="CSI_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_elcdif"> + <struct name="config"> + <setting name="panelWidthInt" value="480"/> + <setting name="panelHeightInt" value="272"/> + <setting name="hsw" value="41"/> + <setting name="hfp" value="4"/> + <setting name="hbp" value="8"/> + <setting name="vsw" value="10"/> + <setting name="vfp" value="4"/> + <setting name="vbp" value="3"/> + <setting name="frameRate" value="60 Hz"/> + <setting name="clockSource" value="LcdIfClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="polarityFlags_st"> + <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/> + <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/> + <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/> + <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/> + </struct> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufferAlign" value="64"/> + <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/> + <setting name="dataBus" value="kELCDIF_DataBus16Bit"/> + <setting name="enablePxpHandShake" value="false"/> + <setting name="start" value="false"/> + </struct> + <setting name="isInterruptEnabled" value="true"/> + <set name="elcdifInterruptSources"> + <selected> + <id>kELCDIF_CurFrameDoneInterruptEnable</id> + </selected> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="LCDIF_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c new file mode 100644 index 000000000..c55e0135a --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c @@ -0,0 +1,509 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 13.0.2 +board: MIMXRT1060-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USBPHY1_CLK.outFreq, value: 480 MHz} +- {id: USBPHY2_CLK.outFreq, value: 480 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} +- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} +- {id: CCM.TRACE_PODF.scale, value: '4', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} +- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} +- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7} +- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled} +- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .postDivider = 8, /* Divider after PLL */ + .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); + pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); + CCM_ANALOG->PLL_VIDEO = pllVideo; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* Init Usb2 PLL. */ + CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h new file mode 100644 index 000000000..7ce24b6f4 --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h @@ -0,0 +1,123 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41.mex b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex new file mode 100644 index 000000000..39b3ed606 --- /dev/null +++ b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex @@ -0,0 +1,1001 @@ +<?xml version="1.0" encoding= "UTF-8" ?> +<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <common> + <processor>MIMXRT1062xxxxA</processor> + <package>MIMXRT1062DVL6A</package> + <board>MIMXRT1060-EVK</board> + <board_revision>A2</board_revision> + <mcu_data>ksdk2_0</mcu_data> + <cores selected="core0"> + <core name="Cortex-M7F" id="core0" description="M7 core"/> + </cores> + <description></description> + </common> + <preferences> + <validate_boot_init_only>false</validate_boot_init_only> + <generate_extended_information>false</generate_extended_information> + <generate_code_modified_registers_only>false</generate_code_modified_registers_only> + <update_include_paths>true</update_include_paths> + <generate_registers_defines>false</generate_registers_defines> + </preferences> + <tools> + <pins name="Pins" version="13.1" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/pin_mux.c" update_enabled="true"/> + <file path="board/pin_mux.h" update_enabled="true"/> + </generated_project_files> + <pins_profile> + <processor_version>13.0.2</processor_version> + <power_domains/> + </pins_profile> + <functions_list> + <function name="BOARD_InitPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins/> + </function> + <function name="BOARD_InitDEBUG_UARTPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>true</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13"> + <pin_features> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Disable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + </pins> + </function> + <function name="BOARD_InitSDRAMPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/> + <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/> + <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/> + <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/> + <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/> + <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/> + <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/> + <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/> + <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/> + <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/> + <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/> + <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/> + <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/> + <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/> + <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/> + <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/> + <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/> + <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/> + <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/> + <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/> + <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/> + <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/> + <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/> + <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/> + <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/> + <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/> + <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/> + <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/> + <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/> + <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/> + <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/> + <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/> + <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/> + <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/> + <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/> + <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/> + <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/> + <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/> + <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/> + <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/> + </pins> + </function> + <function name="BOARD_InitCSIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/> + <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/> + <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/> + <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/> + <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/> + <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/> + <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/> + <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/> + <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/> + <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/> + <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/> + <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/> + <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SCL"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01"> + <pin_features> + <pin_feature name="identifier" value="CSI_I2C_SDA"/> + <pin_feature name="software_input_on" value="Disable"/> + <pin_feature name="hysteresis_enable" value="Disable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Keeper"/> + <pin_feature name="pull_keeper_enable" value="Enable"/> + <pin_feature name="open_drain" value="Enable"/> + <pin_feature name="speed" value="MHZ_100"/> + <pin_feature name="drive_strength" value="R0_6"/> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/> + </pins> + </function> + <function name="BOARD_InitLCDPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03"> + <pin_features> + <pin_feature name="hysteresis_enable" value="Enable"/> + <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/> + <pin_feature name="pull_keeper_select" value="Pull"/> + </pin_features> + </pin> + <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15"> + <pin_features> + <pin_feature name="slew_rate" value="Slow"/> + </pin_features> + </pin> + <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/> + </pins> + </function> + <function name="BOARD_InitCANPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/> + <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/> + </pins> + </function> + <function name="BOARD_InitENETPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/> + <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/> + <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/> + <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/> + <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/> + <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/> + <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/> + <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/> + <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/> + <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/> + </pins> + </function> + <function name="BOARD_InitUSDHCPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/> + <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/> + <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/> + <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/> + <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/> + <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/> + <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/> + </pins> + </function> + <function name="BOARD_InitQSPIPins"> + <description>Configures pin routing and optionally pin electrical features.</description> + <options> + <callFromInitBoot>false</callFromInitBoot> + <coreID>core0</coreID> + <enableClock>true</enableClock> + </options> + <dependencies> + <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins"> + <feature name="initialized" evaluation="equal"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <pins> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/> + <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/> + </pins> + </function> + </functions_list> + </pins> + <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/clock_config.c" update_enabled="true"/> + <file path="board/clock_config.h" update_enabled="true"/> + </generated_project_files> + <clocks_profile> + <processor_version>13.0.2</processor_version> + </clocks_profile> + <clock_configurations> + <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false"> + <description></description> + <options/> + <dependencies> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>INPUT</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="routed" evaluation=""> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN"> + <feature name="direction" evaluation=""> + <data>OUTPUT</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN"> + <feature name="enabled" evaluation="equal" configuration="core0"> + <data>true</data> + </feature> + </dependency> + </dependencies> + <clock_sources> + <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/> + </clock_sources> + <clock_outputs> + <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/> + <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/> + <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/> + <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/> + <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/> + <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/> + <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/> + <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/> + <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/> + <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/> + <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/> + <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/> + <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/> + <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/> + <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/> + <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/> + <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/> + <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/> + </clock_outputs> + <clock_settings> + <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/> + <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/> + <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/> + <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/> + <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/> + <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/> + <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/> + <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/> + <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/> + <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/> + <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/> + <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/> + <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/> + <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/> + <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/> + <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/> + <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/> + <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/> + <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/> + <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/> + <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/> + <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/> + <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/> + <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/> + <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/> + <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/> + <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/> + <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/> + </clock_settings> + <called_from_default_init>true</called_from_default_init> + </clock_configuration> + </clock_configurations> + </clocks> + <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <dcdx_profile> + <processor_version>0.0.0</processor_version> + </dcdx_profile> + <dcdx_configurations/> + </dcdx> + <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true"> + <generated_project_files> + <file path="board/peripherals.c" update_enabled="true"/> + <file path="board/peripherals.h" update_enabled="true"/> + </generated_project_files> + <peripherals_profile> + <processor_version>13.0.2</processor_version> + </peripherals_profile> + <functional_groups> + <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0"> + <description></description> + <options/> + <dependencies/> + <instances> + <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="interruptsCfg"> + <setting name="messageBufferIrqs" value="0"/> + <setting name="messageBufferIrqs2" value="0"/> + <set name="interruptsEnable"> + <selected/> + </set> + <setting name="enable_irq" value="false"/> + <struct name="interrupt_shared"> + <setting name="IRQn" value="CAN2_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="fsl_flexcan" quick_selection="default"> + <struct name="can_config"> + <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="baudRate" value="1000000"/> + <setting name="maxMbNum" value="16"/> + <setting name="enableLoopBack" value="false"/> + <setting name="enableSelfWakeup" value="false"/> + <setting name="enableIndividMask" value="false"/> + <struct name="timingConfig"> + <setting name="propSeg" value="2"/> + <setting name="phaseSeg1" value="4"/> + <setting name="phaseSeg2" value="3"/> + <setting name="rJumpwidth" value="2"/> + <struct name="bitTime"/> + </struct> + </struct> + <setting name="enableRxFIFO" value="false"/> + <struct name="rxFIFO"> + <setting name="idFilterTable" value=""/> + <setting name="idFilterNum" value="num0"/> + <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/> + <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/> + </struct> + <array name="channels"> + <struct name="0"> + <setting name="mbID" value="0"/> + <setting name="mbType" value="mbRx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + <struct name="1"> + <setting name="mbID" value="1"/> + <setting name="mbType" value="mbTx"/> + <struct name="rxMb"> + <setting name="id" value="0"/> + <setting name="format" value="kFLEXCAN_FrameFormatStandard"/> + <setting name="type" value="kFLEXCAN_FrameTypeData"/> + </struct> + </struct> + </array> + </config_set> + </instance> + <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_csi" quick_selection="QuickSelection1"> + <struct name="clockConfig"> + <setting name="clockSource" value="BusInterfaceClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <setting name="masterClockSource" value="CsiClock"/> + <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/> + </struct> + <struct name="config"> + <setting name="format" value="RGB565"/> + <setting name="i_width" value="320"/> + <setting name="i_height" value="240"/> + <setting name="dataBus" value="kCSI_DataBus8Bit"/> + <setting name="workMode" value="kCSI_GatedClockMode"/> + <setting name="useExtVsync" value="true"/> + <set name="polarityFlags"> + <selected/> + </set> + <struct name="buffers_config"> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufCount" value="4"/> + <setting name="bufferAlign" value="64"/> + </struct> + </struct> + <struct name="interruptsCfg"> + <setting name="isInterruptEnabled" value="false"/> + <set name="interruptSources"> + <selected/> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="CSI_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </struct> + </config_set> + </instance> + <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="main" quick_selection="qs_interrupt"> + <setting name="clockSource" value="Lpi2cClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="interrupt"> + <setting name="IRQn" value="LPI2C1_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + <config_set name="master" quick_selection="qs_master_transfer"> + <setting name="mode" value="transfer"/> + <struct name="config"> + <setting name="enableMaster" value="true"/> + <setting name="enableDoze" value="true"/> + <setting name="debugEnable" value="false"/> + <setting name="ignoreAck" value="false"/> + <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/> + <setting name="baudRate_Hz" value="100000"/> + <setting name="busIdleTimeout_ns" value="0"/> + <setting name="pinLowTimeout_ns" value="0"/> + <setting name="sdaGlitchFilterWidth_ns" value="0"/> + <setting name="sclGlitchFilterWidth_ns" value="0"/> + <struct name="hostRequest"> + <setting name="enable" value="false"/> + <setting name="source" value="kLPI2C_HostRequestExternalPin"/> + <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/> + </struct> + <set name="edmaRequestSources"> + <selected/> + </set> + </struct> + <struct name="transfer"> + <setting name="blocking" value="false"/> + <setting name="enable_custom_handle" value="false"/> + <struct name="callback"> + <setting name="name" value=""/> + <setting name="userData" value=""/> + </struct> + <set name="flags"> + <selected/> + </set> + <setting name="slaveAddress" value="0"/> + <setting name="direction" value="kLPI2C_Write"/> + <setting name="subaddress" value="0"/> + <setting name="subaddressSize" value="1"/> + <setting name="blocking_buffer" value="false"/> + <setting name="enable_custom_buffer" value="false"/> + <setting name="dataSize" value="1"/> + </struct> + </config_set> + </instance> + <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="lpuartConfig_t"> + <struct name="lpuartConfig"> + <setting name="clockSource" value="LpuartClock"/> + <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/> + <setting name="baudRate_Bps" value="115200"/> + <setting name="parityMode" value="kLPUART_ParityDisabled"/> + <setting name="dataBitsCount" value="kLPUART_EightDataBits"/> + <setting name="isMsb" value="false"/> + <setting name="stopBitCount" value="kLPUART_OneStopBit"/> + <setting name="enableMatchAddress1" value="false"/> + <setting name="matchAddress1" value="0"/> + <setting name="enableMatchAddress2" value="false"/> + <setting name="matchAddress2" value="0"/> + <setting name="txFifoWatermark" value="0"/> + <setting name="rxFifoWatermark" value="1"/> + <setting name="enableRxRTS" value="false"/> + <setting name="enableTxCTS" value="false"/> + <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/> + <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/> + <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/> + <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/> + <setting name="enableTx" value="true"/> + <setting name="enableRx" value="true"/> + </struct> + </config_set> + </instance> + <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false"> + <config_set name="fsl_elcdif"> + <struct name="config"> + <setting name="panelWidthInt" value="480"/> + <setting name="panelHeightInt" value="272"/> + <setting name="hsw" value="41"/> + <setting name="hfp" value="4"/> + <setting name="hbp" value="8"/> + <setting name="vsw" value="10"/> + <setting name="vfp" value="4"/> + <setting name="vbp" value="3"/> + <setting name="frameRate" value="60 Hz"/> + <setting name="clockSource" value="LcdIfClock"/> + <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/> + <struct name="polarityFlags_st"> + <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/> + <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/> + <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/> + <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/> + </struct> + <setting name="bufferName" value="defaultBuffer"/> + <setting name="bufferAlign" value="64"/> + <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/> + <setting name="dataBus" value="kELCDIF_DataBus16Bit"/> + <setting name="enablePxpHandShake" value="false"/> + <setting name="start" value="false"/> + </struct> + <setting name="isInterruptEnabled" value="true"/> + <set name="elcdifInterruptSources"> + <selected> + <id>kELCDIF_CurFrameDoneInterruptEnable</id> + </selected> + </set> + <struct name="interrupt"> + <setting name="IRQn" value="LCDIF_IRQn"/> + <setting name="enable_interrrupt" value="enabled"/> + <setting name="enable_priority" value="false"/> + <setting name="priority" value="0"/> + <setting name="enable_custom_name" value="false"/> + </struct> + </config_set> + </instance> + <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false"> + <config_set name="nvic"> + <array name="interrupt_table"/> + <array name="interrupts"/> + </config_set> + </instance> + </instances> + </functional_group> + </functional_groups> + <components> + <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system"> + <config_set_global name="global_system_definitions"> + <setting name="user_definitions" value=""/> + <setting name="user_includes" value=""/> + </config_set_global> + </component> + <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg"> + <config_set_global name="global_messages"/> + </component> + <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6"> + <config_set_global name="global_gpio_adapter_common" quick_selection="default"/> + </component> + <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6"> + <config_set_global name="global_uart"/> + </component> + <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80"> + <config_set_global name="global_can"/> + </component> + <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8"> + <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/> + </component> + <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619"> + <config_set_global name="global_enet"/> + </component> + </components> + </periphs> + <tee name="TEE" version="4.0" enabled="false" update_project_code="true"> + <generated_project_files/> + <tee_profile> + <processor_version>0.0.0</processor_version> + </tee_profile> + </tee> + </tools> +</configuration> diff --git a/hw/bsp/mcx/mcx.jlinkscript b/hw/bsp/imxrt/debug.jlinkscript index fd8bcffef..fd8bcffef 100644 --- a/hw/bsp/mcx/mcx.jlinkscript +++ b/hw/bsp/imxrt/debug.jlinkscript diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 735fbdb9b..bfab1d496 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -91,6 +91,16 @@ void board_init(void) BOARD_BootClockRUN(); SystemCoreClockUpdate(); +#ifdef TRACE_ETM + // RT1011 ETM pins +// IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U); +// IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U); +// IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U); +// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U); +// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U); +// CLOCK_EnableClock(kCLOCK_Trace); +#endif + // Enable IOCON clock CLOCK_EnableClock(kCLOCK_Iomuxc); @@ -234,21 +244,18 @@ int board_uart_read(uint8_t* buf, int len) return count; } -int board_uart_write(void const * buf, int len) -{ +int board_uart_write(void const * buf, int len) { LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len); return len; } #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ +void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis(void) -{ +uint32_t board_millis(void) { return system_ticks; } #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index a8841f8ce..f1c5b0ab1 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -24,12 +24,14 @@ set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") function(add_board_target BOARD_TARGET) if (NOT TARGET ${BOARD_TARGET}) add_library(${BOARD_TARGET} STATIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c + #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c ${SDK_DIR}/drivers/common/fsl_common.c ${SDK_DIR}/drivers/igpio/fsl_gpio.c + ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c - ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c ) target_compile_definitions(${BOARD_TARGET} PUBLIC @@ -39,12 +41,15 @@ function(add_board_target BOARD_TARGET) XIP_BOOT_HEADER_ENABLE=1 ) target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board ${CMSIS_DIR}/CMSIS/Core/Include ${SDK_DIR}/devices/${MCU_VARIANT} - ${SDK_DIR}/devices/${MCU_VARIANT}/project_template ${SDK_DIR}/devices/${MCU_VARIANT}/drivers + #${SDK_DIR}/drivers/adc_12b1msps_sar ${SDK_DIR}/drivers/common ${SDK_DIR}/drivers/igpio + ${SDK_DIR}/drivers/lpspi ${SDK_DIR}/drivers/lpuart ) diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript new file mode 100644 index 000000000..fd8bcffef --- /dev/null +++ b/hw/bsp/mcx/debug.jlinkscript @@ -0,0 +1,5 @@ +int SetupTarget(void) { + JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000"); + + return 0; +} diff --git a/src/host/usbh.c b/src/host/usbh.c index f3e9d3858..184bda23b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -791,7 +791,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b uint8_t const dir = tu_edpt_dir(ep_addr); tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir]; - TU_LOG_USBH(" Queue EP %02X with %u bytes ... ", ep_addr, total_bytes); + TU_LOG_USBH(" Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes); // Attempt to transfer on a busy endpoint, sound like an race condition ! TU_ASSERT(ep_state->busy == 0); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 3a38bef58..4e5ff0359 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -47,6 +47,8 @@ #error "Unsupported MCU" #endif +#define TU_RUSB2_HCD_DBG 0 + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -126,7 +128,7 @@ static unsigned find_pipe(unsigned xfer) for (int i = 3; i <= 5; ++i) { if (0 == _hcd.pipe[i].ep) return i; } - for (int i = 1; i <= 1; ++i) { + for (int i = 1; i <= 2; ++i) { if (0 == _hcd.pipe[i].ep) return i; } break; @@ -419,10 +421,11 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num) (void)rhport; xfer_result_t result; uint16_t volatile *ctr = get_pipectr(num); - // TU_LOG1("NRDY %d %x\n", num, *ctr); + TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr); switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) { default: return; case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break; + case RUSB2_PIPE_CTR_PID_STALL2: result = XFER_RESULT_STALLED; break; case RUSB2_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break; } pipe_state_t *pipe = &_hcd.pipe[num]; @@ -451,7 +454,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num) hcd_event_xfer_complete(pipe->dev, pipe->ep, pipe->length - pipe->remaining, XFER_RESULT_SUCCESS, true); - // TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining); + TU_LOG(TU_RUSB2_HCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining); } } @@ -614,7 +617,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0]; for (int i = 0; i < 2 * 15; ++i, ++ep) { unsigned num = *ep; - if (!num || dev_addr != _hcd.pipe[num].dev) continue; + if (!num || (dev_addr != _hcd.pipe[num].dev)) continue; ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1]; *ctr = 0; @@ -636,7 +639,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; - // TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR); + TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR); TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */ TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ); @@ -729,7 +732,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b { bool r; hcd_int_disable(rhport); - // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen); + TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen); r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen); hcd_int_enable(rhport); return r; @@ -774,7 +777,7 @@ void hcd_int_handler(uint8_t rhport) /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */ RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1); RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0); - // TU_LOG1("IS %04x %04x\n", is0, is1); + TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1); is1 &= RUSB2->INTENB1; is0 &= RUSB2->INTENB0; diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h index aceeb3c3e..005d7f2be 100644 --- a/src/portable/renesas/rusb2/rusb2_type.h +++ b/src/portable/renesas/rusb2/rusb2_type.h @@ -1671,6 +1671,7 @@ TU_ATTR_BIT_FIELD_ORDER_END #define RUSB2_PIPE_CTR_PID_NAK (0U << RUSB2_PIPE_CTR_PID_Pos) /* NAK response */ #define RUSB2_PIPE_CTR_PID_BUF (1U << RUSB2_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ #define RUSB2_PIPE_CTR_PID_STALL (2U << RUSB2_PIPE_CTR_PID_Pos) /* STALL response */ +#define RUSB2_PIPE_CTR_PID_STALL2 (3U << RUSB2_PIPE_CTR_PID_Pos) /* Also STALL response */ #define RUSB2_DVSTCTR0_RHST_LS (1U << RUSB2_DVSTCTR0_RHST_Pos) /* Low-speed connection */ #define RUSB2_DVSTCTR0_RHST_FS (2U << RUSB2_DVSTCTR0_RHST_Pos) /* Full-speed connection */ |