code style and clean up CDC serial header files

4 files changed, 224 insertions, 224 deletions

diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index c18066f57..7d91f01fe 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _CH34X_H_
-#define _CH34X_H_
+#ifndef TUSB_CH34X_H
+#define TUSB_CH34X_H
 
 // There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
@@ -40,45 +40,45 @@
 #endif
 
 // USB requests
-#define CH34X_REQ_READ_VERSION 0x5F // dec  95
-#define CH34X_REQ_WRITE_REG    0x9A // dec 154
-#define CH34X_REQ_READ_REG     0x95 // dec 149
-#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
-#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
+#define CH34X_REQ_READ_VERSION        0x5F // dec  95
+#define CH34X_REQ_WRITE_REG           0x9A // dec 154
+#define CH34X_REQ_READ_REG            0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT         0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL          0xA4 // dev 164
 
 // registers
-#define CH34X_REG_BREAK        0x05
-#define CH34X_REG_PRESCALER    0x12
-#define CH34X_REG_DIVISOR      0x13
-#define CH34X_REG_LCR          0x18
-#define CH34X_REG_LCR2         0x25
-#define CH34X_REG_MCR_MSR      0x06
-#define CH34X_REG_MCR_MSR2     0x07
-#define CH34X_NBREAK_BITS      0x01
+#define CH34X_REG_BREAK               0x05
+#define CH34X_REG_PRESCALER           0x12
+#define CH34X_REG_DIVISOR             0x13
+#define CH34X_REG_LCR                 0x18
+#define CH34X_REG_LCR2                0x25
+#define CH34X_REG_MCR_MSR             0x06
+#define CH34X_REG_MCR_MSR2            0x07
+#define CH34X_NBREAK_BITS             0x01
 
-#define CH341_REG_0x0F         0x0F // undocumented register
-#define CH341_REG_0x2C         0x2C // undocumented register
-#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+#define CH341_REG_0x0F                0x0F // undocumented register
+#define CH341_REG_0x2C                0x2C // undocumented register
+#define CH341_REG_0x27                0x27 // hardware flow control (cts/rts)
 
-#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
-#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
+#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR          TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
 
 // modem control bits
-#define CH34X_BIT_RTS ( 1 << 6 )
-#define CH34X_BIT_DTR ( 1 << 5 )
+#define CH34X_BIT_RTS                 (1 << 6)
+#define CH34X_BIT_DTR                 (1 << 5)
 
 // line control bits
-#define CH34X_LCR_ENABLE_RX    0x80
-#define CH34X_LCR_ENABLE_TX    0x40
-#define CH34X_LCR_MARK_SPACE   0x20
-#define CH34X_LCR_PAR_EVEN     0x10
-#define CH34X_LCR_ENABLE_PAR   0x08
-#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
-#define CH34X_LCR_STOP_BITS_2  0x04
-#define CH34X_LCR_CS8          0x03
-#define CH34X_LCR_CS7          0x02
-#define CH34X_LCR_CS6          0x01
-#define CH34X_LCR_CS5          0x00
-#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
+#define CH34X_LCR_ENABLE_RX           0x80
+#define CH34X_LCR_ENABLE_TX           0x40
+#define CH34X_LCR_MARK_SPACE          0x20
+#define CH34X_LCR_PAR_EVEN            0x10
+#define CH34X_LCR_ENABLE_PAR          0x08
+#define CH34X_LCR_PAR_MASK            0x38 // all parity bits
+#define CH34X_LCR_STOP_BITS_2         0x04
+#define CH34X_LCR_CS8                 0x03
+#define CH34X_LCR_CS7                 0x02
+#define CH34X_LCR_CS6                 0x01
+#define CH34X_LCR_CS5                 0x00
+#define CH34X_LCR_CS_MASK             0x03 // all CSx bits
 
-#endif /* _CH34X_H_ */
+#endif // TUSB_CH34X_H
diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h
index e18da7d51..a553a54da 100644
--- a/src/class/cdc/serial/cp210x.h
+++ b/src/class/cdc/serial/cp210x.h
@@ -31,7 +31,7 @@
 // parts are overtaken from vendors driver
 // https://www.silabs.com/documents/public/software/cp210x-3.1.0.tar.gz
 
-/* Config request codes */
+// Config request codes
 #define CP210X_IFC_ENABLE      0x00
 #define CP210X_SET_BAUDDIV     0x01
 #define CP210X_GET_BAUDDIV     0x02
@@ -60,56 +60,56 @@
 #define CP210X_SET_BAUDRATE    0x1E
 #define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device
 
-/* SILABSER_IFC_ENABLE_REQUEST_CODE */
-#define CP210X_UART_ENABLE       0x0001
-#define CP210X_UART_DISABLE        0x0000
+// SILABSER_IFC_ENABLE_REQUEST_CODE
+#define CP210X_UART_ENABLE              0x0001
+#define CP210X_UART_DISABLE             0x0000
 
-/* SILABSER_SET_BAUDDIV_REQUEST_CODE */
-#define CP210X_BAUD_RATE_GEN_FREQ      0x384000
+// SILABSER_SET_BAUDDIV_REQUEST_CODE
+#define CP210X_BAUD_RATE_GEN_FREQ     0x384000
 
-/*SILABSER_SET_LINE_CTL_REQUEST_CODE */
-#define CP210X_BITS_DATA_MASK        0x0f00
-#define CP210X_BITS_DATA_5       0x0500
-#define CP210X_BITS_DATA_6       0x0600
-#define CP210X_BITS_DATA_7       0x0700
-#define CP210X_BITS_DATA_8       0x0800
-#define CP210X_BITS_DATA_9       0x0900
+// SILABSER_SET_LINE_CTL_REQUEST_CODE
+#define CP210X_BITS_DATA_MASK           0x0f00
+#define CP210X_BITS_DATA_5              0x0500
+#define CP210X_BITS_DATA_6              0x0600
+#define CP210X_BITS_DATA_7              0x0700
+#define CP210X_BITS_DATA_8              0x0800
+#define CP210X_BITS_DATA_9              0x0900
 
-#define CP210X_BITS_PARITY_MASK      0x00f0
-#define CP210X_BITS_PARITY_NONE      0x0000
-#define CP210X_BITS_PARITY_ODD       0x0010
-#define CP210X_BITS_PARITY_EVEN      0x0020
-#define CP210X_BITS_PARITY_MARK      0x0030
-#define CP210X_BITS_PARITY_SPACE     0x0040
+#define CP210X_BITS_PARITY_MASK         0x00f0
+#define CP210X_BITS_PARITY_NONE         0x0000
+#define CP210X_BITS_PARITY_ODD          0x0010
+#define CP210X_BITS_PARITY_EVEN         0x0020
+#define CP210X_BITS_PARITY_MARK         0x0030
+#define CP210X_BITS_PARITY_SPACE        0x0040
 
-#define CP210X_BITS_STOP_MASK        0x000f
-#define CP210X_BITS_STOP_1       0x0000
-#define CP210X_BITS_STOP_1_5       0x0001
-#define CP210X_BITS_STOP_2       0x0002
+#define CP210X_BITS_STOP_MASK           0x000f
+#define CP210X_BITS_STOP_1              0x0000
+#define CP210X_BITS_STOP_1_5            0x0001
+#define CP210X_BITS_STOP_2              0x0002
 
-/* SILABSER_SET_BREAK_REQUEST_CODE */
-#define CP210X_BREAK_ON        0x0001
-#define CP210X_BREAK_OFF       0x0000
+// SILABSER_SET_BREAK_REQUEST_CODE
+#define CP210X_BREAK_ON                 0x0001
+#define CP210X_BREAK_OFF                0x0000
 
-/* SILABSER_SET_MHS_REQUEST_CODE */
-#define CP210X_MCR_DTR         0x0001
-#define CP210X_MCR_RTS         0x0002
-#define CP210X_MCR_ALL         0x0003
-#define CP210X_MSR_CTS         0x0010
-#define CP210X_MSR_DSR         0x0020
-#define CP210X_MSR_RING        0x0040
-#define CP210X_MSR_DCD         0x0080
-#define CP210X_MSR_ALL         0x00F0
+// SILABSER_SET_MHS_REQUEST_CODE
+#define CP210X_MCR_DTR                  0x0001
+#define CP210X_MCR_RTS                  0x0002
+#define CP210X_MCR_ALL                  0x0003
+#define CP210X_MSR_CTS                  0x0010
+#define CP210X_MSR_DSR                  0x0020
+#define CP210X_MSR_RING                 0x0040
+#define CP210X_MSR_DCD                  0x0080
+#define CP210X_MSR_ALL                  0x00F0
 
-#define CP210X_CONTROL_WRITE_DTR     0x0100
-#define CP210X_CONTROL_WRITE_RTS     0x0200
+#define CP210X_CONTROL_WRITE_DTR        0x0100
+#define CP210X_CONTROL_WRITE_RTS        0x0200
 
-#define CP210X_LSR_BREAK       0x0001
-#define CP210X_LSR_FRAMING_ERROR     0x0002
-#define CP210X_LSR_HW_OVERRUN        0x0004
-#define CP210X_LSR_QUEUE_OVERRUN     0x0008
-#define CP210X_LSR_PARITY_ERROR      0x0010
-#define CP210X_LSR_ALL         0x001F
+#define CP210X_LSR_BREAK                0x0001
+#define CP210X_LSR_FRAMING_ERROR        0x0002
+#define CP210X_LSR_HW_OVERRUN           0x0004
+#define CP210X_LSR_QUEUE_OVERRUN        0x0008
+#define CP210X_LSR_PARITY_ERROR         0x0010
+#define CP210X_LSR_ALL                  0x001F
 
 // supported baudrates
 // reference: datasheets and AN205 "CP210x Baud Rate Support"
diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h
index 42716f73e..4afedec9b 100644
--- a/src/class/cdc/serial/ftdi_sio.h
+++ b/src/class/cdc/serial/ftdi_sio.h
@@ -28,43 +28,43 @@
 #include <stdint.h>
 
 // Commands
-#define FTDI_SIO_RESET              0 // Reset the port
-#define FTDI_SIO_MODEM_CTRL         1 // Set the modem control register
-#define FTDI_SIO_SET_FLOW_CTRL      2 // Set flow control register
-#define FTDI_SIO_SET_BAUD_RATE      3 // Set baud rate
-#define FTDI_SIO_SET_DATA           4 // Set the data characteristics of the port
-#define FTDI_SIO_GET_MODEM_STATUS   5 // Retrieve current value of modem status register
-#define FTDI_SIO_SET_EVENT_CHAR     6 // Set the event character
-#define FTDI_SIO_SET_ERROR_CHAR     7 // Set the error character
-#define FTDI_SIO_SET_LATENCY_TIMER  9 // Set the latency timer
-#define FTDI_SIO_GET_LATENCY_TIMER 10 // Get the latency timer
-#define FTDI_SIO_SET_BITMODE       11 // Set bitbang mode
-#define FTDI_SIO_READ_PINS         12 // Read immediate value of pins
-#define FTDI_SIO_READ_EEPROM     0x90 // Read EEPROM
+#define FTDI_SIO_RESET                0 // Reset the port
+#define FTDI_SIO_MODEM_CTRL           1 // Set the modem control register
+#define FTDI_SIO_SET_FLOW_CTRL        2 // Set flow control register
+#define FTDI_SIO_SET_BAUD_RATE        3 // Set baud rate
+#define FTDI_SIO_SET_DATA             4 // Set the data characteristics of the port
+#define FTDI_SIO_GET_MODEM_STATUS     5 // Retrieve current value of modem status register
+#define FTDI_SIO_SET_EVENT_CHAR       6 // Set the event character
+#define FTDI_SIO_SET_ERROR_CHAR       7 // Set the error character
+#define FTDI_SIO_SET_LATENCY_TIMER    9 // Set the latency timer
+#define FTDI_SIO_GET_LATENCY_TIMER   10 // Get the latency timer
+#define FTDI_SIO_SET_BITMODE         11 // Set bitbang mode
+#define FTDI_SIO_READ_PINS           12 // Read immediate value of pins
+#define FTDI_SIO_READ_EEPROM       0x90 // Read EEPROM
 
 // Channel indices for FT2232, FT2232H and FT4232H devices
-#define CHANNEL_A   1
-#define CHANNEL_B   2
-#define CHANNEL_C   3
-#define CHANNEL_D   4
+#define CHANNEL_A 1
+#define CHANNEL_B 2
+#define CHANNEL_C 3
+#define CHANNEL_D 4
 
 // Port Identifier Table
-#define PIT_DEFAULT   0 // SIOA
-#define PIT_SIOA      1 // SIOA
+#define PIT_DEFAULT  0 // SIOA
+#define PIT_SIOA     1 // SIOA
 // The device this driver is tested with one has only one port
-#define PIT_SIOB      2 // SIOB
-#define PIT_PARALLEL  3 // Parallel
+#define PIT_SIOB     2 // SIOB
+#define PIT_PARALLEL 3 // Parallel
 
 // FTDI_SIO_RESET
-#define FTDI_SIO_RESET_REQUEST FTDI_SIO_RESET
-#define FTDI_SIO_RESET_REQUEST_TYPE 0x40
-#define FTDI_SIO_RESET_SIO 0
-#define FTDI_SIO_RESET_PURGE_RX 1
-#define FTDI_SIO_RESET_PURGE_TX 2
+#define FTDI_SIO_RESET_REQUEST                    FTDI_SIO_RESET
+#define FTDI_SIO_RESET_REQUEST_TYPE               0x40
+#define FTDI_SIO_RESET_SIO                        0
+#define FTDI_SIO_RESET_PURGE_RX                   1
+#define FTDI_SIO_RESET_PURGE_TX                   2
 
 // FTDI_SIO_SET_BAUDRATE
-#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE 0x40
-#define FTDI_SIO_SET_BAUDRATE_REQUEST 3
+#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE        0x40
+#define FTDI_SIO_SET_BAUDRATE_REQUEST             3
 
 enum ftdi_sio_baudrate {
   ftdi_sio_b300 = 0,
@@ -80,89 +80,89 @@ enum ftdi_sio_baudrate {
 };
 
 // FTDI_SIO_SET_DATA
-#define FTDI_SIO_SET_DATA_REQUEST FTDI_SIO_SET_DATA
-#define FTDI_SIO_SET_DATA_REQUEST_TYPE  0x40
-#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_ODD  (0x1 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8)
-#define FTDI_SIO_SET_DATA_PARITY_SPACE  (0x4 << 8)
-#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_15  (0x1 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11)
-#define FTDI_SIO_SET_BREAK    (0x1 << 14)
+#define FTDI_SIO_SET_DATA_REQUEST                 FTDI_SIO_SET_DATA
+#define FTDI_SIO_SET_DATA_REQUEST_TYPE            0x40
+#define FTDI_SIO_SET_DATA_PARITY_NONE             (0x0 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_ODD              (0x1 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_EVEN             (0x2 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_MARK             (0x3 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_SPACE            (0x4 << 8)
+#define FTDI_SIO_SET_DATA_STOP_BITS_1             (0x0 << 11) // same coding as ACM
+#define FTDI_SIO_SET_DATA_STOP_BITS_15            (0x1 << 11) // 1.5 not supported, for future use?
+#define FTDI_SIO_SET_DATA_STOP_BITS_2             (0x2 << 11)
+#define FTDI_SIO_SET_BREAK                        (0x1 << 14)
 
 // FTDI_SIO_MODEM_CTRL
-#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40
-#define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL
+#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE      0x40
+#define FTDI_SIO_SET_MODEM_CTRL_REQUEST           FTDI_SIO_MODEM_CTRL
 
-#define FTDI_SIO_SET_DTR_MASK 0x1
-#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK  << 8) | 1)
-#define FTDI_SIO_SET_DTR_LOW  ((FTDI_SIO_SET_DTR_MASK  << 8) | 0)
-#define FTDI_SIO_SET_RTS_MASK 0x2
-#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2)
-#define FTDI_SIO_SET_RTS_LOW  ((FTDI_SIO_SET_RTS_MASK << 8) | 0)
+#define FTDI_SIO_SET_DTR_MASK                     0x1
+#define FTDI_SIO_SET_DTR_HIGH                     ((FTDI_SIO_SET_DTR_MASK << 8) | 1)
+#define FTDI_SIO_SET_DTR_LOW                      ((FTDI_SIO_SET_DTR_MASK << 8) | 0)
+#define FTDI_SIO_SET_RTS_MASK                     0x2
+#define FTDI_SIO_SET_RTS_HIGH                     ((FTDI_SIO_SET_RTS_MASK << 8) | 2)
+#define FTDI_SIO_SET_RTS_LOW                      ((FTDI_SIO_SET_RTS_MASK << 8) | 0)
 
 // FTDI_SIO_SET_FLOW_CTRL
-#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40
-#define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL
+#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE       0x40
+#define FTDI_SIO_SET_FLOW_CTRL_REQUEST            FTDI_SIO_SET_FLOW_CTRL
 #define FTDI_SIO_DISABLE_FLOW_CTRL 0x0
-#define FTDI_SIO_RTS_CTS_HS (0x1 << 8)
-#define FTDI_SIO_DTR_DSR_HS (0x2 << 8)
-#define FTDI_SIO_XON_XOFF_HS (0x4 << 8)
+#define FTDI_SIO_RTS_CTS_HS                       (0x1 << 8)
+#define FTDI_SIO_DTR_DSR_HS                       (0x2 << 8)
+#define FTDI_SIO_XON_XOFF_HS                      (0x4 << 8)
 
 // FTDI_SIO_GET_LATENCY_TIMER
-#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST FTDI_SIO_GET_LATENCY_TIMER
-#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE 0xC0
+#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST       FTDI_SIO_GET_LATENCY_TIMER
+#define  FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE  0xC0
 
 // FTDI_SIO_SET_LATENCY_TIMER
-#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST FTDI_SIO_SET_LATENCY_TIMER
-#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE 0x40
+#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST       FTDI_SIO_SET_LATENCY_TIMER
+#define  FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE  0x40
 
 // FTDI_SIO_SET_EVENT_CHAR
-#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST FTDI_SIO_SET_EVENT_CHAR
-#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE 0x40
+#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST          FTDI_SIO_SET_EVENT_CHAR
+#define  FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE     0x40
 
 // FTDI_SIO_GET_MODEM_STATUS
-#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE 0xc0
-#define FTDI_SIO_GET_MODEM_STATUS_REQUEST FTDI_SIO_GET_MODEM_STATUS
-#define FTDI_SIO_CTS_MASK 0x10
-#define FTDI_SIO_DSR_MASK 0x20
-#define FTDI_SIO_RI_MASK  0x40
-#define FTDI_SIO_RLSD_MASK 0x80
+#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE    0xc0
+#define FTDI_SIO_GET_MODEM_STATUS_REQUEST         FTDI_SIO_GET_MODEM_STATUS
+#define FTDI_SIO_CTS_MASK                         0x10
+#define FTDI_SIO_DSR_MASK                         0x20
+#define FTDI_SIO_RI_MASK                          0x40
+#define FTDI_SIO_RLSD_MASK                        0x80
 
 // FTDI_SIO_SET_BITMODE
-#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE 0x40
-#define FTDI_SIO_SET_BITMODE_REQUEST FTDI_SIO_SET_BITMODE
+#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE         0x40
+#define FTDI_SIO_SET_BITMODE_REQUEST              FTDI_SIO_SET_BITMODE
 
 // Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST
-#define FTDI_SIO_BITMODE_RESET    0x00
-#define FTDI_SIO_BITMODE_CBUS   0x20
+#define FTDI_SIO_BITMODE_RESET                    0x00
+#define FTDI_SIO_BITMODE_CBUS                     0x20
 
 // FTDI_SIO_READ_PINS
-#define FTDI_SIO_READ_PINS_REQUEST_TYPE 0xc0
-#define FTDI_SIO_READ_PINS_REQUEST FTDI_SIO_READ_PINS
+#define FTDI_SIO_READ_PINS_REQUEST_TYPE           0xc0
+#define FTDI_SIO_READ_PINS_REQUEST                FTDI_SIO_READ_PINS
 
 // FTDI_SIO_READ_EEPROM
-#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE 0xc0
-#define FTDI_SIO_READ_EEPROM_REQUEST FTDI_SIO_READ_EEPROM
+#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE         0xc0
+#define FTDI_SIO_READ_EEPROM_REQUEST              FTDI_SIO_READ_EEPROM
 
 #define FTDI_FTX_CBUS_MUX_GPIO    0x8
 #define FTDI_FT232R_CBUS_MUX_GPIO 0xa
 
 #define FTDI_RS0_CTS  (1 << 4)
 #define FTDI_RS0_DSR  (1 << 5)
-#define FTDI_RS0_RI (1 << 6)
+#define FTDI_RS0_RI   (1 << 6)
 #define FTDI_RS0_RLSD (1 << 7)
 
-#define FTDI_RS_DR  1
-#define FTDI_RS_OE  (1<<1)
-#define FTDI_RS_PE  (1<<2)
-#define FTDI_RS_FE  (1<<3)
-#define FTDI_RS_BI  (1<<4)
-#define FTDI_RS_THRE  (1<<5)
-#define FTDI_RS_TEMT  (1<<6)
-#define FTDI_RS_FIFO  (1<<7)
+#define FTDI_RS_DR    1
+#define FTDI_RS_OE    (1 << 1)
+#define FTDI_RS_PE    (1 << 2)
+#define FTDI_RS_FE    (1 << 3)
+#define FTDI_RS_BI    (1 << 4)
+#define FTDI_RS_THRE  (1 << 5)
+#define FTDI_RS_TEMT  (1 << 6)
+#define FTDI_RS_FIFO  (1 << 7)
 
 // chip types and names
 enum ftdi_chip_type {
@@ -206,14 +206,14 @@ enum ftdi_chip_type {
 
 // private interface data
 typedef struct ftdi_private {
-  enum ftdi_chip_type chip_type;
-  uint8_t channel; // channel index, or 0 for legacy types
+  enum    ftdi_chip_type chip_type;
+  uint8_t channel;                  // channel index, or 0 for legacy types
 } ftdi_private_t;
 
-#define FTDI_OK true
-#define FTDI_FAIL false
+#define FTDI_OK           true
+#define FTDI_FAIL         false
 #define FTDI_NOT_POSSIBLE -1
-#define FTDI_REQUESTED -2
+#define FTDI_REQUESTED    -2
 
 // division and round function overtaken from math.h
 #define DIV_ROUND_CLOSEST(x, divisor)(      \
diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h
index bf264191b..d69bdbfae 100644
--- a/src/class/cdc/serial/pl2303.h
+++ b/src/class/cdc/serial/pl2303.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _PL2303_H_
-#define _PL2303_H_
+#ifndef TUSB_PL2303_H
+#define TUSB_PL2303_H
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -36,66 +36,66 @@
 //   https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.c
 // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uplcom.c
 
-/* quirks */
-#define PL2303_QUIRK_UART_STATE_IDX0 1
-#define PL2303_QUIRK_LEGACY 2
-#define PL2303_QUIRK_ENDPOINT_HACK 4
+// quirks
+#define PL2303_QUIRK_UART_STATE_IDX0      1
+#define PL2303_QUIRK_LEGACY               2
+#define PL2303_QUIRK_ENDPOINT_HACK        4
 
-/* requests and bits */
-#define PL2303_SET_LINE_REQUEST_TYPE 0x21     // class request host to device interface
-#define PL2303_SET_LINE_REQUEST 0x20          // dec 32
+// requests and bits
+#define PL2303_SET_LINE_REQUEST_TYPE      0x21    // class request host to device interface
+#define PL2303_SET_LINE_REQUEST           0x20    // dec 32
 
-#define PL2303_SET_CONTROL_REQUEST_TYPE 0x21  // class request host to device interface
-#define PL2303_SET_CONTROL_REQUEST 0x22       // dec 34
-#define PL2303_CONTROL_DTR 0x01               // dec 1
-#define PL2303_CONTROL_RTS 0x02               // dec 2
+#define PL2303_SET_CONTROL_REQUEST_TYPE   0x21    // class request host to device interface
+#define PL2303_SET_CONTROL_REQUEST        0x22    // dec 34
+#define PL2303_CONTROL_DTR                0x01    // dec 1
+#define PL2303_CONTROL_RTS                0x02    // dec 2
 
-#define PL2303_BREAK_REQUEST_TYPE 0x21        // class request host to device interface
-#define PL2303_BREAK_REQUEST 0x23             // dec 35
-#define PL2303_BREAK_ON 0xffff
-#define PL2303_BREAK_OFF 0x0000
+#define PL2303_BREAK_REQUEST_TYPE         0x21    // class request host to device interface
+#define PL2303_BREAK_REQUEST              0x23    // dec 35
+#define PL2303_BREAK_ON                   0xffff
+#define PL2303_BREAK_OFF                  0x0000
 
-#define PL2303_GET_LINE_REQUEST_TYPE 0xa1     // class request device to host interface
-#define PL2303_GET_LINE_REQUEST 0x21          // dec 33
+#define PL2303_GET_LINE_REQUEST_TYPE      0xa1    // class request device to host interface
+#define PL2303_GET_LINE_REQUEST           0x21    // dec 33
 
-#define PL2303_VENDOR_WRITE_REQUEST_TYPE 0x40 // vendor request host to device interface
-#define PL2303_VENDOR_WRITE_REQUEST 0x01      // dec 1
-#define PL2303_VENDOR_WRITE_NREQUEST 0x80     // dec 128
+#define PL2303_VENDOR_WRITE_REQUEST_TYPE  0x40    // vendor request host to device interface
+#define PL2303_VENDOR_WRITE_REQUEST       0x01    // dec 1
+#define PL2303_VENDOR_WRITE_NREQUEST      0x80    // dec 128
 
-#define PL2303_VENDOR_READ_REQUEST_TYPE 0xc0  // vendor request device to host interface
-#define PL2303_VENDOR_READ_REQUEST 0x01       // dec 1
-#define PL2303_VENDOR_READ_NREQUEST 0x81      // dec 129
+#define PL2303_VENDOR_READ_REQUEST_TYPE   0xc0    // vendor request device to host interface
+#define PL2303_VENDOR_READ_REQUEST        0x01    // dec 1
+#define PL2303_VENDOR_READ_NREQUEST       0x81    // dec 129
 
-#define PL2303_UART_STATE_INDEX 8
-#define PL2303_UART_STATE_MSR_MASK 0x8b
-#define PL2303_UART_STATE_TRANSIENT_MASK 0x74
-#define PL2303_UART_DCD 0x01
-#define PL2303_UART_DSR 0x02
-#define PL2303_UART_BREAK_ERROR 0x04
-#define PL2303_UART_RING 0x08
-#define PL2303_UART_FRAME_ERROR 0x10
-#define PL2303_UART_PARITY_ERROR 0x20
-#define PL2303_UART_OVERRUN_ERROR 0x40
-#define PL2303_UART_CTS 0x80
+#define PL2303_UART_STATE_INDEX           8
+#define PL2303_UART_STATE_MSR_MASK        0x8b
+#define PL2303_UART_STATE_TRANSIENT_MASK  0x74
+#define PL2303_UART_DCD                   0x01
+#define PL2303_UART_DSR                   0x02
+#define PL2303_UART_BREAK_ERROR           0x04
+#define PL2303_UART_RING                  0x08
+#define PL2303_UART_FRAME_ERROR           0x10
+#define PL2303_UART_PARITY_ERROR          0x20
+#define PL2303_UART_OVERRUN_ERROR         0x40
+#define PL2303_UART_CTS                   0x80
 
-#define PL2303_FLOWCTRL_MASK 0xf0
+#define PL2303_FLOWCTRL_MASK              0xf0
 
-#define PL2303_CLEAR_HALT_REQUEST_TYPE 0x02   // standard request host to device endpoint
+#define PL2303_CLEAR_HALT_REQUEST_TYPE    0x02    // standard request host to device endpoint
 
-/* registers via vendor read/write requests */
-#define PL2303_READ_TYPE_HX_STATUS 0x8080
+// registers via vendor read/write requests
+#define PL2303_READ_TYPE_HX_STATUS        0x8080
 
-#define PL2303_HXN_RESET_REG 0x07
-#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02
-#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01
+#define PL2303_HXN_RESET_REG              0x07
+#define PL2303_HXN_RESET_UPSTREAM_PIPE    0x02
+#define PL2303_HXN_RESET_DOWNSTREAM_PIPE  0x01
 
-#define PL2303_HXN_FLOWCTRL_REG 0x0a
-#define PL2303_HXN_FLOWCTRL_MASK 0x1c
-#define PL2303_HXN_FLOWCTRL_NONE 0x1c
-#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18
-#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c
+#define PL2303_HXN_FLOWCTRL_REG           0x0a
+#define PL2303_HXN_FLOWCTRL_MASK          0x1c
+#define PL2303_HXN_FLOWCTRL_NONE          0x1c
+#define PL2303_HXN_FLOWCTRL_RTS_CTS       0x18
+#define PL2303_HXN_FLOWCTRL_XON_XOFF      0x0c
 
-/* type data */
+// type data
 enum pl2303_type {
   TYPE_H,
   TYPE_HX,
@@ -107,9 +107,9 @@ enum pl2303_type {
 };
 
 struct pl2303_type_data {
-  uint8_t const *name;
+  uint8_t  const *name;
   uint32_t const max_baud_rate;
-  uint8_t const quirks;
+  uint8_t  const quirks;
   uint16_t const no_autoxonxoff:1;
   uint16_t const no_divisors:1;
   uint16_t const alt_divisors:1;
@@ -146,7 +146,7 @@ struct pl2303_type_data {
     .no_divisors = true, \
   }
 
-/* private data types */
+// private data types
 struct pl2303_serial_private {
   const struct pl2303_type_data* type;
   uint8_t quirks;
@@ -157,16 +157,16 @@ typedef struct TU_ATTR_PACKED {
   bool supports_hx_status;
 } pl2303_private_t;
 
-/* buffer sizes for line coding data */
-#define PL2303_LINE_CODING_BUFSIZE 7
+// buffer sizes for line coding data
+#define PL2303_LINE_CODING_BUFSIZE          7
 #define PL2303_LINE_CODING_BAUDRATE_BUFSIZE 4
 
-/* bulk endpoints */
-#define PL2303_OUT_EP 0x02
-#define PL2303_IN_EP 0x83
+// bulk endpoints
+#define PL2303_OUT_EP                       0x02
+#define PL2303_IN_EP                        0x83
 
-/* return values of pl2303_detect_type() */
+// return values of pl2303_detect_type()
 #define PL2303_SUPPORTS_HX_STATUS_TRIGGERED -1
-#define PL2303_DETECT_TYPE_FAILED -2
+#define PL2303_DETECT_TYPE_FAILED           -2
 
-#endif /* _PL2303_H_ */
+#endif // TUSB_PL2303_H