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| author | Ha Thach <[email protected]> | 2023-03-14 09:08:32 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-03-14 09:08:32 +0700 |
| commit | ea8ecea59aa60a1028cce16b0f15bb33918b11af (patch) | |
| tree | 4af7e758e6ae6d7812e8851a33ba7e654973629c | |
| parent | 7cf67b28456f6cb8738956bd6af1fd2b8300de4f (diff) | |
| parent | d31aac453eaa0b56a998c3cca5d2efd4c55209af (diff) | |
Merge pull request #1953 from tannewt/fix_cached_imx_reset
Flush the dcd data on reset
| -rw-r--r-- | src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index c7cc3e0e8..5bccf81a7 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -48,6 +48,8 @@ #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) +// Clean means to push any cached changes to RAM and invalidate "removes" the +// entry from the cache. #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr #else @@ -199,6 +201,8 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); } void dcd_init(uint8_t rhport) |