hw/bsp/lpc43: configure safe flash timing

1 files changed, 12 insertions, 1 deletions

diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index 0f3c62fef..7f0722a33 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -60,10 +60,21 @@ void SystemInit(void);
 void SystemInit(void)
 {
 #if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
+  __disable_irq();
+#endif
+
+  if (Chip_CREG_OnChipFlashIsPresent()) {
+    // The boot ROM configures flash for its 96 MHz clock, and debugger core
+    // resets can preserve it. Use safe timing before switching the M4 to 204 MHz.
+    Chip_CREG_SetFLASHAccess(FLASHTIM_SAFE_SETTING);
+    __DSB();
+    __ISB();
+  }
+
+#if defined(__ICCARM__) && !defined(DONT_RESET_ON_RESTART)
   // A debugger restart resets the M4 core, but can leave LPC43 peripherals and
   // pending interrupts active. Match the GCC startup sequence, which the IAR
   // startup lacks, before the C runtime can reuse peripheral DMA memory.
-  __disable_irq();
   LPC_RGU->RESET_CTRL[0] = 0x10DF1000u;
   LPC_RGU->RESET_CTRL[1] = 0x01DFF7FFu;
   for (uint32_t i = 0; i < 8; i++) {