optimize interrupt handling time

Signed-off-by: HiFiPhile <[email protected]>

2 files changed, 24 insertions, 11 deletions

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 4dfd04fb4..6f7f490a8 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -343,7 +343,7 @@ void dcd_int_handler(uint8_t rhport) {
   uint32_t int_status = FSDEV_REG->ISTR;
 
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
-  if (int_status & U_ISTR_SOF) {
+  if ((int_status & U_ISTR_SOF) && (FSDEV_REG->CNTR & U_CNTR_SOFM)) {
     FSDEV_REG->ISTR = (fsdev_bus_t)~U_ISTR_SOF;
     dcd_event_sof(0, FSDEV_REG->FNR & U_FNR_FN, true);
   }
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
index 74cc9d0a4..b15c95302 100644
--- a/src/portable/st/stm32_fsdev/fsdev_stm32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -266,32 +266,45 @@ TU_ATTR_ALWAYS_INLINE static inline void fsdev_int_disable(uint8_t rhport) {
  *
  * CTR may trigger before final PMA SRAM accesses complete on OUT transfers.
  * Insert delay before reading PMA count/data.
- * Max CPU frequency in MHz, used to derive conservative FSDEV PMA delay defaults.
+ * Max CPU frequency in Hz, used to derive conservative FSDEV PMA delay defaults.
  */
 #if CFG_TUSB_MCU == OPT_MCU_STM32H5
-  #define FSDEV_STM32_CPU_MHZ 250U
+  #define FSDEV_STM32_CPU_HZ 250000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
-  #define FSDEV_STM32_CPU_MHZ 160U
+  #define FSDEV_STM32_CPU_HZ 160000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U3
-  #define FSDEV_STM32_CPU_MHZ 96U
+  #define FSDEV_STM32_CPU_HZ 96000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
-  #define FSDEV_STM32_CPU_MHZ 56U
+  #define FSDEV_STM32_CPU_HZ 56000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  #define FSDEV_STM32_CPU_MHZ 64U
+  #define FSDEV_STM32_CPU_HZ 64000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32C0
-  #define FSDEV_STM32_CPU_MHZ 48U
+  #define FSDEV_STM32_CPU_HZ 48000000U
 #elif CFG_TUSB_MCU == OPT_MCU_STM32C5
-  #define FSDEV_STM32_CPU_MHZ 144U
+  #define FSDEV_STM32_CPU_HZ 144000000U
 #endif
 
+// 11 cycles / 800ns = ~13750000 cycles per second, used to derive conservative FSDEV PMA delay defaults
 #ifndef CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT
-  #define CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ / 4U)
+  #define CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT (FSDEV_STM32_CPU_HZ / 13750000U)
 #endif
 
+// 11 cycles / 6.4us = ~1718750 cycles per second, used to derive conservative FSDEV PMA delay defaults
 #ifndef CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT
-  #define CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ * 2U)
+  #define CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT (FSDEV_STM32_CPU_HZ / 1718750U)
 #endif
 
+/**
+ * LDR from SP-relative: 2 cycles
+ * SUBS: 1 cycle
+ * STR to SP-relative: 2 cycles
+ * LDR from SP-relative: 2 cycles
+ * CMP: 1 cycle
+ * BNE:
+ * taken: 3 cycles total (often shown as 1 + pipeline refill)
+ * not taken: 1 cycle
+ * Total cycles if delay is needed: 11 cycles
+ */
 TU_ATTR_ALWAYS_INLINE static inline void fsdev_btable_workaround_delay(bool low_speed) {
   volatile uint32_t cycle_count = low_speed ? CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT : CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT;
   while (cycle_count > 0U) {