diff options
| author | William D. Jones <[email protected]> | 2019-10-29 11:43:26 -0400 |
|---|---|---|
| committer | William D. Jones <[email protected]> | 2019-10-29 11:43:26 -0400 |
| commit | ffeb61a71070b262e5ffb975abad74c2d57b8fb9 (patch) | |
| tree | 0032b8a4083e9f1bb19c31de13d3050011c184c5 | |
| parent | 66faa96f1609a1a6e95004ec7adbcd1568df01e2 (diff) | |
msp_exp430f5529lp: Use ti submodule for includes and linker files.
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/board.mk | 6 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/in430.h | 345 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/iomacros.h | 87 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/msp430.h | 1920 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/msp430f5529.h | 4789 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/msp430f5529.ld | 457 | ||||
| -rw-r--r-- | hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld | 867 |
7 files changed, 3 insertions, 8468 deletions
diff --git a/hw/bsp/msp_exp430f5529lp/board.mk b/hw/bsp/msp_exp430f5529lp/board.mk index a0893a08e..95192a990 100644 --- a/hw/bsp/msp_exp430f5529lp/board.mk +++ b/hw/bsp/msp_exp430f5529lp/board.mk @@ -7,10 +7,10 @@ CFLAGS += \ #-mmcu=msp430f5529 # All source paths should be relative to the top level. -LD_FILE = hw/bsp/msp_exp430f5529lp/msp430f5529.ld -LDINC += $(TOP)/hw/bsp/$(BOARD) +LD_FILE = hw/mcu/ti/msp430/msp430-gcc-support-files/include/msp430f5529.ld +LDINC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include -INC += $(TOP)/hw/bsp/$(BOARD) +INC += $(TOP)/hw/mcu/ti/msp430/msp430-gcc-support-files/include # For TinyUSB port source VENDOR = ti diff --git a/hw/bsp/msp_exp430f5529lp/in430.h b/hw/bsp/msp_exp430f5529lp/in430.h deleted file mode 100644 index 9df9194c6..000000000 --- a/hw/bsp/msp_exp430f5529lp/in430.h +++ /dev/null @@ -1,345 +0,0 @@ -/******************************************************************************* - * in430.h - - * - * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -/* 1.207 */ - -#ifndef __IN430_H__ -#define __IN430_H__ - -/* Definitions for projects using the GNU C/C++ compiler */ -#if !defined(__ASSEMBLER__) - -/* Definitions of things which are intrinsics with IAR and CCS, but which don't - appear to be intrinsics with the GCC compiler */ - -/* The data type used to hold interrupt state */ -typedef unsigned int __istate_t; - -#define _no_operation() __asm__ __volatile__ ("nop") - -#define _get_interrupt_state() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SR, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__) -#define _set_interrupt_state(x) \ -({ \ - __asm__ __volatile__ ("nop { mov %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop") - -#define _bis_SR_register(x) \ - __asm__ __volatile__ ("nop { bis.w %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - ) -#else - -#define _set_interrupt_state(x) \ -({ \ - __asm__ __volatile__ ("mov %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define _enable_interrupts() __asm__ __volatile__ ("eint") - -#define _bis_SR_register(x) \ - __asm__ __volatile__ ("bis.w %0, SR" \ - : : "ri"((unsigned int) x) \ - ) - -#endif - -#define _disable_interrupts() __asm__ __volatile__ ("dint { nop") - -#define _bic_SR_register(x) \ - __asm__ __volatile__ ("bic.w %0, SR { nop" \ - : : "ri"((unsigned int) x) \ - ) - -#define _get_SR_register() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SR, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#define _swap_bytes(x) \ -({ \ - unsigned int __dst = x; \ - __asm__ __volatile__( \ - "swpb %0" \ - : "+r" ((unsigned int) __dst) \ - :); \ - __dst; \ -}) - -/* Alternative names for GCC built-ins */ -#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x) -#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x) - -/* Additional intrinsics provided for IAR/CCS compatibility */ -#define _bcd_add_short(x,y) \ -({ \ - unsigned short __z = ((unsigned short) y); \ - __asm__ __volatile__( \ - "clrc \n\t" \ - "dadd.w %1, %0" \ - : "+r" ((unsigned short) __z) \ - : "ri" ((unsigned short) x) \ - ); \ - __z; \ -}) - -#define __bcd_add_short(x,y) _bcd_add_short(x,y) - -#define _bcd_add_long(x,y) \ -({ \ - unsigned long __z = ((unsigned long) y); \ - __asm__ __volatile__( \ - "clrc \n\t" \ - "dadd.w %L1, %L0 \n\t" \ - "dadd.w %H1, %H0" \ - : "+r" ((unsigned long) __z) \ - : "ri" ((unsigned long) x) \ - ); \ - __z; \ - }) - -#define __bcd_add_long(x,y) _bcd_add_long(x,y) - -#define _get_SP_register() \ -({ \ - unsigned int __x; \ - __asm__ __volatile__( \ - "mov SP, %0" \ - : "=r" ((unsigned int) __x) \ - :); \ - __x; \ -}) - -#define __get_SP_register() _get_SP_register() - -#define _set_SP_register(x) \ -({ \ - __asm__ __volatile__ ("mov %0, SP" \ - : : "ri"((unsigned int) x) \ - );\ -}) - -#define __set_SP_register(x) _set_SP_register(x) - -#define _data16_write_addr(addr,src) \ -({ \ - unsigned long __src = src; \ - __asm__ __volatile__ ( \ - "movx.a %1, 0(%0)" \ - : : "r"((unsigned int) addr), "m"((unsigned long) __src) \ - ); \ -}) - -#define __data16_write_addr(addr,src) _data16_write_addr(addr,src) - -#define _data16_read_addr(addr) \ -({ \ - unsigned long __dst; \ - __asm__ __volatile__ ( \ - "movx.a @%1, %0" \ - : "=m"((unsigned long) __dst) \ - : "r"((unsigned int) addr) \ - ); \ - __dst; \ -}) - -#define __data16_read_addr(addr) _data16_read_addr(addr) - -#define _data20_write_char(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.b %2, 0(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((char) src) \ - ); \ -}) - -#define __data20_write_char(addr,src) _data20_write_char(addr,src) - -#define _data20_read_char(addr) \ -({ \ - char __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.b 0(%1), %0" \ - : "=r"((char) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_char(addr) _data20_read_char(addr) - -#define _data20_write_short(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.w %2, 0(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((short) src) \ - ); \ -}) - -#define __data20_write_short(addr,src) _data20_write_short(addr,src) - -#define _data20_read_short(addr) \ -({ \ - short __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.w 0(%1), %0" \ - : "=r"((short) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_short(addr) _data20_read_short(addr) - -#define _data20_write_long(addr,src) \ -({ \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %1, %0 \n\t" \ - "mov.w %L2, 0(%0) \n\t" \ - "mov.w %H2, 2(%0)" \ - : "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr), "ri"((long) src) \ - ); \ -}) - -#define __data20_write_long(addr,src) _data20_write_long(addr,src) - -#define _data20_read_long(addr) \ -({ \ - long __dst; \ - unsigned int __tmp; \ - unsigned long __addr = addr; \ - __asm__ __volatile__ ( \ - "movx.a %2, %1 \n\t" \ - "mov.w 0(%1), %L0 \n\t" \ - "mov.w 2(%1), %H0" \ - : "=r"((long) __dst), "=&r"((unsigned int) __tmp) \ - : "m"((unsigned long) __addr) \ - ); \ - __dst ; \ -}) - -#define __data20_read_long(addr) _data20_read_long(addr) - -#define _low_power_mode_0() _bis_SR_register(0x18) -#define _low_power_mode_1() _bis_SR_register(0x58) -#define _low_power_mode_2() _bis_SR_register(0x98) -#define _low_power_mode_3() _bis_SR_register(0xD8) -#define _low_power_mode_4() _bis_SR_register(0xF8) -#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0) - -#define __low_power_mode_0() _low_power_mode_0() -#define __low_power_mode_1() _low_power_mode_1() -#define __low_power_mode_2() _low_power_mode_2() -#define __low_power_mode_3() _low_power_mode_3() -#define __low_power_mode_4() _low_power_mode_4() -#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit() - -#define _even_in_range(x,y) (x) -#define __even_in_range(x,y) _even_in_range(x,y) - -/* Define some alternative names for the intrinsics, which have been used - in the various versions of IAR and GCC */ -#define __no_operation() _no_operation() - -#define __get_interrupt_state() _get_interrupt_state() -#define __set_interrupt_state(x) _set_interrupt_state(x) -#define __enable_interrupt() _enable_interrupts() -#define __disable_interrupt() _disable_interrupts() - -#define __bic_SR_register(x) _bic_SR_register(x) -#define __bis_SR_register(x) _bis_SR_register(x) -#define __get_SR_register() _get_SR_register() - -#define __swap_bytes(x) _swap_bytes(x) - -#define __nop() _no_operation() - -#define __eint() _enable_interrupts() -#define __dint() _disable_interrupts() - -#define _NOP() _no_operation() -#define _EINT() _enable_interrupts() -#define _DINT() _disable_interrupts() - -#define _BIC_SR(x) _bic_SR_register(x) -#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x) -#define _BIS_SR(x) _bis_SR_register(x) -#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x) -#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x) - -#define _SWAP_BYTES(x) _swap_bytes(x) - -#define __no_init __attribute__((noinit)) - -#endif /* !defined _GNU_ASSEMBLER_ */ - -#endif /* __IN430_H__ */ diff --git a/hw/bsp/msp_exp430f5529lp/iomacros.h b/hw/bsp/msp_exp430f5529lp/iomacros.h deleted file mode 100644 index 5ddda4873..000000000 --- a/hw/bsp/msp_exp430f5529lp/iomacros.h +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* - * iomacros.h - - * - * Copyright (C) 2003-2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -/* 1.207 */ - -#if !defined(_IOMACROS_H_) -#define _IOMACROS_H_ - - -#if defined(__ASSEMBLER__) - -/* Definitions for assembly compilation using the GNU assembler */ -#define sfrb(x,x_) x=x_ -#define sfrw(x,x_) x=x_ -#define sfra(x,x_) x=x_ -#define sfrl(x,x_) x=x_ - -#define const_sfrb(x,x_) x=x_ -#define const_sfrw(x,x_) x=x_ -#define const_sfra(x,x_) x=x_ -#define const_sfrl(x,x_) x=x_ - -#define sfr_b(x) -#define sfr_w(x) -#define sfr_a(x) -#define sfr_l(x) - -#else - -#define sfr_b(x) extern volatile unsigned char x -#define sfr_w(x) extern volatile unsigned int x -#define sfr_a(x) extern volatile unsigned long int x -#define sfr_l(x) extern volatile unsigned long int x - -#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_) -#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_) -#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_) -#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_) - -#define sfrb(x,x_) sfrb_(x,x_) -#define sfrw(x,x_) sfrw_(x,x_) -#define sfra(x,x_) sfra_(x,x_) -#define sfrl(x,x_) sfrl_(x,x_) - -#define const_sfrb(x,x_) const sfrb_(x,x_) -#define const_sfrw(x,x_) const sfrw_(x,x_) -#define const_sfra(x,x_) const sfra_(x,x_) -#define const_sfrl(x,x_) const sfrl_(x,x_) - -#define __interrupt __attribute__((__interrupt__)) -#define __interrupt_vec(vec) __attribute__((interrupt(vec))) - -#endif /* defined(__ASSEMBLER__) */ - -#endif /* _IOMACROS_H_ */ diff --git a/hw/bsp/msp_exp430f5529lp/msp430.h b/hw/bsp/msp_exp430f5529lp/msp430.h deleted file mode 100644 index a162addc0..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430.h +++ /dev/null @@ -1,1920 +0,0 @@ -/******************************************************************* -* * -* This file is a generic include file controlled by * -* compiler/assembler IDE generated defines * -* * -*******************************************************************/ - -#ifndef __msp430 -#define __msp430 - - -#if defined (__MSP430C111__) -#include "msp430c111.h" - -#elif defined (__MSP430C1111__) -#include "msp430c1111.h" - -#elif defined (__MSP430C112__) -#include "msp430c112.h" - -#elif defined (__MSP430C1121__) -#include "msp430c1121.h" - -#elif defined (__MSP430C1331__) -#include "msp430c1331.h" - -#elif defined (__MSP430C1351__) -#include "msp430c1351.h" - -#elif defined (__MSP430C311S__) -#include "msp430c311s.h" - -#elif defined (__MSP430C312__) -#include "msp430c312.h" - -#elif defined (__MSP430C313__) -#include "msp430c313.h" - -#elif defined (__MSP430C314__) -#include "msp430c314.h" - -#elif defined (__MSP430C315__) -#include "msp430c315.h" - -#elif defined (__MSP430C323__) -#include "msp430c323.h" - -#elif defined (__MSP430C325__) -#include "msp430c325.h" - -#elif defined (__MSP430C336__) -#include "msp430c336.h" - -#elif defined (__MSP430C337__) -#include "msp430c337.h" - -#elif defined (__MSP430C412__) -#include "msp430c412.h" - -#elif defined (__MSP430C413__) -#include "msp430c413.h" - -#elif defined (__MSP430CG4616__) -#include "msp430cg4616.h" - -#elif defined (__MSP430CG4617__) -#include "msp430cg4617.h" - -#elif defined (__MSP430CG4618__) -#include "msp430cg4618.h" - -#elif defined (__MSP430CG4619__) -#include "msp430cg4619.h" - -#elif defined (__MSP430E112__) -#include "msp430e112.h" - -#elif defined (__MSP430E313__) -#include "msp430e313.h" - -#elif defined (__MSP430E315__) -#include "msp430e315.h" - -#elif defined (__MSP430E325__) -#include "msp430e325.h" - -#elif defined (__MSP430E337__) -#include "msp430e337.h" - -#elif defined (__MSP430F110__) -#include "msp430f110.h" - -#elif defined (__MSP430F1101__) -#include "msp430f1101.h" - -#elif defined (__MSP430F1101A__) -#include "msp430f1101a.h" - -#elif defined (__MSP430F1111__) -#include "msp430f1111.h" - -#elif defined (__MSP430F1111A__) -#include "msp430f1111a.h" - -#elif defined (__MSP430F112__) -#include "msp430f112.h" - -#elif defined (__MSP430F1121__) -#include "msp430f1121.h" - -#elif defined (__MSP430F1121A__) -#include "msp430f1121a.h" - -#elif defined (__MSP430F1122__) -#include "msp430f1122.h" - -#elif defined (__MSP430F1132__) -#include "msp430f1132.h" - -#elif defined (__MSP430F122__) -#include "msp430f122.h" - -#elif defined (__MSP430F1222__) -#include "msp430f1222.h" - -#elif defined (__MSP430F123__) -#include "msp430f123.h" - -#elif defined (__MSP430F1232__) -#include "msp430f1232.h" - -#elif defined (__MSP430F133__) -#include "msp430f133.h" - -#elif defined (__MSP430F135__) -#include "msp430f135.h" - -#elif defined (__MSP430F147__) -#include "msp430f147.h" - -#elif defined (__MSP430F148__) -#include "msp430f148.h" - -#elif defined (__MSP430F149__) -#include "msp430f149.h" - -#elif defined (__MSP430F1471__) -#include "msp430f1471.h" - -#elif defined (__MSP430F1481__) -#include "msp430f1481.h" - -#elif defined (__MSP430F1491__) -#include "msp430f1491.h" - -#elif defined (__MSP430F155__) -#include "msp430f155.h" - -#elif defined (__MSP430F156__) -#include "msp430f156.h" - -#elif defined (__MSP430F157__) -#include "msp430f157.h" - -#elif defined (__MSP430F167__) -#include "msp430f167.h" - -#elif defined (__MSP430F168__) -#include "msp430f168.h" - -#elif defined (__MSP430F169__) -#include "msp430f169.h" - -#elif defined (__MSP430F1610__) -#include "msp430f1610.h" - -#elif defined (__MSP430F1611__) -#include "msp430f1611.h" - -#elif defined (__MSP430F1612__) -#include "msp430f1612.h" - -#elif defined (__MSP430F2001__) -#include "msp430f2001.h" - -#elif defined (__MSP430F2011__) -#include "msp430f2011.h" - -#elif defined (__MSP430F2002__) -#include "msp430f2002.h" - -#elif defined (__MSP430F2012__) -#include "msp430f2012.h" - -#elif defined (__MSP430F2003__) -#include "msp430f2003.h" - -#elif defined (__MSP430F2013__) -#include "msp430f2013.h" - -#elif defined (__MSP430F2101__) -#include "msp430f2101.h" - -#elif defined (__MSP430F2111__) -#include "msp430f2111.h" - -#elif defined (__MSP430F2121__) -#include "msp430f2121.h" - -#elif defined (__MSP430F2131__) -#include "msp430f2131.h" - -#elif defined (__MSP430F2112__) -#include "msp430f2112.h" - -#elif defined (__MSP430F2122__) -#include "msp430f2122.h" - -#elif defined (__MSP430F2132__) -#include "msp430f2132.h" - -#elif defined (__MSP430F2232__) -#include "msp430f2232.h" - -#elif defined (__MSP430F2252__) -#include "msp430f2252.h" - -#elif defined (__MSP430F2272__) -#include "msp430f2272.h" - -#elif defined (__MSP430F2234__) -#include "msp430f2234.h" - -#elif defined (__MSP430F2254__) -#include "msp430f2254.h" - -#elif defined (__MSP430F2274__) -#include "msp430f2274.h" - -#elif defined (__MSP430F2330__) -#include "msp430f2330.h" - -#elif defined (__MSP430F2350__) -#include "msp430f2350.h" - -#elif defined (__MSP430F2370__) -#include "msp430f2370.h" - -#elif defined (__MSP430F233__) -#include "msp430f233.h" - -#elif defined (__MSP430F235__) -#include "msp430f235.h" - -#elif defined (__MSP430F247__) -#include "msp430f247.h" - -#elif defined (__MSP430F248__) -#include "msp430f248.h" - -#elif defined (__MSP430F249__) -#include "msp430f249.h" - -#elif defined (__MSP430F2410__) -#include "msp430f2410.h" - -#elif defined (__MSP430F2471__) -#include "msp430f2471.h" - -#elif defined (__MSP430F2481__) -#include "msp430f2481.h" - -#elif defined (__MSP430F2491__) -#include "msp430f2491.h" - -#elif defined (__MSP430F2416__) -#include "msp430f2416.h" - -#elif defined (__MSP430F2417__) -#include "msp430f2417.h" - -#elif defined (__MSP430F2418__) -#include "msp430f2418.h" - -#elif defined (__MSP430F2419__) -#include "msp430f2419.h" - -#elif defined (__MSP430F2616__) -#include "msp430f2616.h" - -#elif defined (__MSP430F2617__) -#include "msp430f2617.h" - -#elif defined (__MSP430F2618__) -#include "msp430f2618.h" - -#elif defined (__MSP430F2619__) -#include "msp430f2619.h" - -#elif defined (__MSP430F412__) -#include "msp430f412.h" - -#elif defined (__MSP430F413__) -#include "msp430f413.h" - -#elif defined (__MSP430F415__) -#include "msp430f415.h" - -#elif defined (__MSP430F417__) -#include "msp430f417.h" - -#elif defined (__MSP430F4132__) -#include "msp430f4132.h" - -#elif defined (__MSP430F4152__) -#include "msp430f4152.h" - -#elif defined (__MSP430F423__) -#include "msp430f423.h" - -#elif defined (__MSP430F425__) -#include "msp430f425.h" - -#elif defined (__MSP430F427__) -#include "msp430f427.h" - -#elif defined (__MSP430F423A__) -#include "msp430f423a.h" - -#elif defined (__MSP430F425A__) -#include "msp430f425a.h" - -#elif defined (__MSP430F427A__) -#include "msp430f427a.h" - -#elif defined (__MSP430F435__) -#include "msp430f435.h" - -#elif defined (__MSP430F436__) -#include "msp430f436.h" - -#elif defined (__MSP430F437__) -#include "msp430f437.h" - -#elif defined (__MSP430F4351__) -#include "msp430f4351.h" - -#elif defined (__MSP430F4361__) -#include "msp430f4361.h" - -#elif defined (__MSP430F4371__) -#include "msp430f4371.h" - -#elif defined (__MSP430F4481__) -#include "msp430f4481.h" - -#elif defined (__MSP430F4491__) -#include "msp430f4491.h" - -#elif defined (__MSP430F447__) -#include "msp430f447.h" - -#elif defined (__MSP430F448__) -#include "msp430f448.h" - -#elif defined (__MSP430F449__) -#include "msp430f449.h" - -#elif defined (__MSP430FE423__) -#include "msp430fe423.h" - -#elif defined (__MSP430FE425__) -#include "msp430fe425.h" - -#elif defined (__MSP430FE427__) -#include "msp430fe427.h" - -#elif defined (__MSP430FE423A__) -#include "msp430fe423a.h" - -#elif defined (__MSP430FE425A__) -#include "msp430fe425a.h" - -#elif defined (__MSP430FE427A__) -#include "msp430fe427a.h" - -#elif defined (__MSP430FE4232__) -#include "msp430fe4232.h" - -#elif defined (__MSP430FE4242__) -#include "msp430fe4242.h" - -#elif defined (__MSP430FE4252__) -#include "msp430fe4252.h" - -#elif defined (__MSP430FE4272__) -#include "msp430fe4272.h" - -#elif defined (__MSP430F4783__) -#include "msp430f4783.h" - -#elif defined (__MSP430F4793__) -#include "msp430f4793.h" - -#elif defined (__MSP430F4784__) -#include "msp430f4784.h" - -#elif defined (__MSP430F4794__) -#include "msp430f4794.h" - -#elif defined (__MSP430F47126__) -#include "msp430f47126.h" - -#elif defined (__MSP430F47127__) -#include "msp430f47127.h" - -#elif defined (__MSP430F47163__) -#include "msp430f47163.h" - -#elif defined (__MSP430F47173__) -#include "msp430f47173.h" - -#elif defined (__MSP430F47183__) -#include "msp430f47183.h" - -#elif defined (__MSP430F47193__) -#include "msp430f47193.h" - -#elif defined (__MSP430F47166__) -#include "msp430f47166.h" - -#elif defined (__MSP430F47176__) -#include "msp430f47176.h" - -#elif defined (__MSP430F47186__) -#include "msp430f47186.h" - -#elif defined (__MSP430F47196__) -#include "msp430f47196.h" - -#elif defined (__MSP430F47167__) -#include "msp430f47167.h" - -#elif defined (__MSP430F47177__) -#include "msp430f47177.h" - -#elif defined (__MSP430F47187__) -#include "msp430f47187.h" - -#elif defined (__MSP430F47197__) -#include "msp430f47197.h" - -#elif defined (__MSP430F4250__) -#include "msp430f4250.h" - -#elif defined (__MSP430F4260__) -#include "msp430f4260.h" - -#elif defined (__MSP430F4270__) -#include "msp430f4270.h" - -#elif defined (__MSP430FG4250__) -#include "msp430fg4250.h" - -#elif defined (__MSP430FG4260__) -#include "msp430fg4260.h" - -#elif defined (__MSP430FG4270__) -#include "msp430fg4270.h" - -#elif defined (__MSP430FW423__) -#include "msp430fw423.h" - -#elif defined (__MSP430FW425__) -#include "msp430fw425.h" - -#elif defined (__MSP430FW427__) -#include "msp430fw427.h" - -#elif defined (__MSP430FW428__) -#include "msp430fw428.h" - -#elif defined (__MSP430FW429__) -#include "msp430fw429.h" - -#elif defined (__MSP430FG437__) -#include "msp430fg437.h" - -#elif defined (__MSP430FG438__) -#include "msp430fg438.h" - -#elif defined (__MSP430FG439__) -#include "msp430fg439.h" - -#elif defined (__MSP430F438__) -#include "msp430f438.h" - -#elif defined (__MSP430F439__) -#include "msp430f439.h" - -#elif defined (__MSP430F477__) -#include "msp430f477.h" - -#elif defined (__MSP430F478__) -#include "msp430f478.h" - -#elif defined (__MSP430F479__) -#include "msp430f479.h" - -#elif defined (__MSP430FG477__) -#include "msp430fg477.h" - -#elif defined (__MSP430FG478__) -#include "msp430fg478.h" - -#elif defined (__MSP430FG479__) -#include "msp430fg479.h" - -#elif defined (__MSP430F46161__) -#include "msp430f46161.h" - -#elif defined (__MSP430F46171__) -#include "msp430f46171.h" - -#elif defined (__MSP430F46181__) -#include "msp430f46181.h" - -#elif defined (__MSP430F46191__) -#include "msp430f46191.h" - -#elif defined (__MSP430F4616__) -#include "msp430f4616.h" - -#elif defined (__MSP430F4617__) -#include "msp430f4617.h" - -#elif defined (__MSP430F4618__) -#include "msp430f4618.h" - -#elif defined (__MSP430F4619__) -#include "msp430f4619.h" - -#elif defined (__MSP430FG4616__) -#include "msp430fg4616.h" - -#elif defined (__MSP430FG4617__) -#include "msp430fg4617.h" - -#elif defined (__MSP430FG4618__) -#include "msp430fg4618.h" - -#elif defined (__MSP430FG4619__) -#include "msp430fg4619.h" - -#elif defined (__MSP430F5418__) -#include "msp430f5418.h" - -#elif defined (__MSP430F5419__) -#include "msp430f5419.h" - -#elif defined (__MSP430F5435__) -#include "msp430f5435.h" - -#elif defined (__MSP430F5436__) -#include "msp430f5436.h" - -#elif defined (__MSP430F5437__) -#include "msp430f5437.h" - -#elif defined (__MSP430F5438__) -#include "msp430f5438.h" - -#elif defined (__MSP430F5418A__) -#include "msp430f5418a.h" - -#elif defined (__MSP430F5419A__) -#include "msp430f5419a.h" - -#elif defined (__MSP430F5435A__) -#include "msp430f5435a.h" - -#elif defined (__MSP430F5436A__) -#include "msp430f5436a.h" - -#elif defined (__MSP430F5437A__) -#include "msp430f5437a.h" - -#elif defined (__MSP430F5438A__) -#include "msp430f5438a.h" - -#elif defined (__MSP430F5212__) -#include "msp430f5212.h" - -#elif defined (__MSP430F5213__) -#include "msp430f5213.h" - -#elif defined (__MSP430F5214__) -#include "msp430f5214.h" - -#elif defined (__MSP430F5217__) -#include "msp430f5217.h" - -#elif defined (__MSP430F5218__) -#include "msp430f5218.h" - -#elif defined (__MSP430F5219__) -#include "msp430f5219.h" - -#elif defined (__MSP430F5222__) -#include "msp430f5222.h" - -#elif defined (__MSP430F5223__) -#include "msp430f5223.h" - -#elif defined (__MSP430F5224__) -#include "msp430f5224.h" - -#elif defined (__MSP430F5227__) -#include "msp430f5227.h" - -#elif defined (__MSP430F5228__) -#include "msp430f5228.h" - -#elif defined (__MSP430F5229__) -#include "msp430f5229.h" - -#elif defined (__MSP430F5232__) -#include "msp430f5232.h" - -#elif defined (__MSP430F5234__) -#include "msp430f5234.h" - -#elif defined (__MSP430F5237__) -#include "msp430f5237.h" - -#elif defined (__MSP430F5239__) -#include "msp430f5239.h" - -#elif defined (__MSP430F5242__) -#include "msp430f5242.h" - -#elif defined (__MSP430F5244__) -#include "msp430f5244.h" - -#elif defined (__MSP430F5247__) -#include "msp430f5247.h" - -#elif defined (__MSP430F5249__) -#include "msp430f5249.h" - -#elif defined (__MSP430F5304__) -#include "msp430f5304.h" - -#elif defined (__MSP430F5308__) -#include "msp430f5308.h" - -#elif defined (__MSP430F5309__) -#include "msp430f5309.h" - -#elif defined (__MSP430F5310__) -#include "msp430f5310.h" - -#elif defined (__MSP430F5340__) -#include "msp430f5340.h" - -#elif defined (__MSP430F5341__) -#include "msp430f5341.h" - -#elif defined (__MSP430F5342__) -#include "msp430f5342.h" - -#elif defined (__MSP430F5324__) -#include "msp430f5324.h" - -#elif defined (__MSP430F5325__) -#include "msp430f5325.h" - -#elif defined (__MSP430F5326__) -#include "msp430f5326.h" - -#elif defined (__MSP430F5327__) -#include "msp430f5327.h" - -#elif defined (__MSP430F5328__) -#include "msp430f5328.h" - -#elif defined (__MSP430F5329__) -#include "msp430f5329.h" - -#elif defined (__MSP430F5500__) -#include "msp430f5500.h" - -#elif defined (__MSP430F5501__) -#include "msp430f5501.h" - -#elif defined (__MSP430F5502__) -#include "msp430f5502.h" - -#elif defined (__MSP430F5503__) -#include "msp430f5503.h" - -#elif defined (__MSP430F5504__) -#include "msp430f5504.h" - -#elif defined (__MSP430F5505__) -#include "msp430f5505.h" - -#elif defined (__MSP430F5506__) -#include "msp430f5506.h" - -#elif defined (__MSP430F5507__) -#include "msp430f5507.h" - -#elif defined (__MSP430F5508__) -#include "msp430f5508.h" - -#elif defined (__MSP430F5509__) -#include "msp430f5509.h" - -#elif defined (__MSP430F5510__) -#include "msp430f5510.h" - -#elif defined (__MSP430F5513__) -#include "msp430f5513.h" - -#elif defined (__MSP430F5514__) -#include "msp430f5514.h" - -#elif defined (__MSP430F5515__) -#include "msp430f5515.h" - -#elif defined (__MSP430F5517__) -#include "msp430f5517.h" - -#elif defined (__MSP430F5519__) -#include "msp430f5519.h" - -#elif defined (__MSP430F5521__) -#include "msp430f5521.h" - -#elif defined (__MSP430F5522__) -#include "msp430f5522.h" - -#elif defined (__MSP430F5524__) -#include "msp430f5524.h" - -#elif defined (__MSP430F5525__) -#include "msp430f5525.h" - -#elif defined (__MSP430F5526__) -#include "msp430f5526.h" - -#elif defined (__MSP430F5527__) -#include "msp430f5527.h" - -#elif defined (__MSP430F5528__) -#include "msp430f5528.h" - -#elif defined (__MSP430F5529__) -#include "msp430f5529.h" - -#elif defined (__MSP430P112__) -#include "msp430p112.h" - -#elif defined (__MSP430P313__) -#include "msp430p313.h" - -#elif defined (__MSP430P315__) -#include "msp430p315.h" - -#elif defined (__MSP430P315S__) -#include "msp430p315s.h" - -#elif defined (__MSP430P325__) -#include "msp430p325.h" - -#elif defined (__MSP430P337__) -#include "msp430p337.h" - -#elif defined (__CC430F5133__) -#include "cc430f5133.h" - -#elif defined (__CC430F5135__) -#include "cc430f5135.h" - -#elif defined (__CC430F5137__) -#include "cc430f5137.h" - -#elif defined (__CC430F6125__) -#include "cc430f6125.h" - -#elif defined (__CC430F6126__) -#include "cc430f6126.h" - -#elif defined (__CC430F6127__) -#include "cc430f6127.h" - -#elif defined (__CC430F6135__) -#include "cc430f6135.h" - -#elif defined (__CC430F6137__) -#include "cc430f6137.h" - -#elif defined (__CC430F5123__) -#include "cc430f5123.h" - -#elif defined (__CC430F5125__) -#include "cc430f5125.h" - -#elif defined (__CC430F5143__) -#include "cc430f5143.h" - -#elif defined (__CC430F5145__) -#include "cc430f5145.h" - -#elif defined (__CC430F5147__) -#include "cc430f5147.h" - -#elif defined (__CC430F6143__) -#include "cc430f6143.h" - -#elif defined (__CC430F6145__) -#include "cc430f6145.h" - -#elif defined (__CC430F6147__) -#include "cc430f6147.h" - -#elif defined (__MSP430F5333__) -#include "msp430f5333.h" - -#elif defined (__MSP430F5335__) -#include "msp430f5335.h" - -#elif defined (__MSP430F5336__) -#include "msp430f5336.h" - -#elif defined (__MSP430F5338__) -#include "msp430f5338.h" - -#elif defined (__MSP430F5630__) -#include "msp430f5630.h" - -#elif defined (__MSP430F5631__) -#include "msp430f5631.h" - -#elif defined (__MSP430F5632__) -#include "msp430f5632.h" - -#elif defined (__MSP430F5633__) -#include "msp430f5633.h" - -#elif defined (__MSP430F5634__) -#include "msp430f5634.h" - -#elif defined (__MSP430F5635__) -#include "msp430f5635.h" - -#elif defined (__MSP430F5636__) -#include "msp430f5636.h" - -#elif defined (__MSP430F5637__) -#include "msp430f5637.h" - -#elif defined (__MSP430F5638__) -#include "msp430f5638.h" - -#elif defined (__MSP430F6433__) -#include "msp430f6433.h" - -#elif defined (__MSP430F6435__) -#include "msp430f6435.h" - -#elif defined (__MSP430F6436__) -#include "msp430f6436.h" - -#elif defined (__MSP430F6438__) -#include "msp430f6438.h" - -#elif defined (__MSP430F6630__) -#include "msp430f6630.h" - -#elif defined (__MSP430F6631__) -#include "msp430f6631.h" - -#elif defined (__MSP430F6632__) -#include "msp430f6632.h" - -#elif defined (__MSP430F6633__) -#include "msp430f6633.h" - -#elif defined (__MSP430F6634__) -#include "msp430f6634.h" - -#elif defined (__MSP430F6635__) -#include "msp430f6635.h" - -#elif defined (__MSP430F6636__) -#include "msp430f6636.h" - -#elif defined (__MSP430F6637__) -#include "msp430f6637.h" - -#elif defined (__MSP430F6638__) -#include "msp430f6638.h" - -#elif defined (__MSP430F5358__) -#include "msp430f5358.h" - -#elif defined (__MSP430F5359__) -#include "msp430f5359.h" - -#elif defined (__MSP430F5658__) -#include "msp430f5658.h" - -#elif defined (__MSP430F5659__) -#include "msp430f5659.h" - -#elif defined (__MSP430F6458__) -#include "msp430f6458.h" - -#elif defined (__MSP430F6459__) -#include "msp430f6459.h" - -#elif defined (__MSP430F6658__) -#include "msp430f6658.h" - -#elif defined (__MSP430F6659__) -#include "msp430f6659.h" - -#elif defined (__MSP430FG6425__) -#include "msp430fg6425.h" - -#elif defined (__MSP430FG6426__) -#include "msp430fg6426.h" - -#elif defined (__MSP430FG6625__) -#include "msp430fg6625.h" - -#elif defined (__MSP430FG6626__) -#include "msp430fg6626.h" - -#elif defined (__MSP430L092__) -#include "msp430l092.h" - -#elif defined (__MSP430C091__) -#include "msp430c091.h" - -#elif defined (__MSP430C092__) -#include "msp430c092.h" - -#elif defined (__MSP430F5131__) -#include "msp430f5131.h" - -#elif defined (__MSP430F5151__) -#include "msp430f5151.h" - -#elif defined (__MSP430F5171__) -#include "msp430f5171.h" - -#elif defined (__MSP430F5132__) -#include "msp430f5132.h" - -#elif defined (__MSP430F5152__) -#include "msp430f5152.h" - -#elif defined (__MSP430F5172__) -#include "msp430f5172.h" - -#elif defined (__MSP430F6720__) -#include "msp430f6720.h" - -#elif defined (__MSP430F6721__) -#include "msp430f6721.h" - -#elif defined (__MSP430F6723__) -#include "msp430f6723.h" - -#elif defined (__MSP430F6724__) -#include "msp430f6724.h" - -#elif defined (__MSP430F6725__) -#include "msp430f6725.h" - -#elif defined (__MSP430F6726__) -#include "msp430f6726.h" - -#elif defined (__MSP430F6730__) -#include "msp430f6730.h" - -#elif defined (__MSP430F6731__) -#include "msp430f6731.h" - -#elif defined (__MSP430F6733__) -#include "msp430f6733.h" - -#elif defined (__MSP430F6734__) -#include "msp430f6734.h" - -#elif defined (__MSP430F6735__) -#include "msp430f6735.h" - -#elif defined (__MSP430F6736__) -#include "msp430f6736.h" - -#elif defined (__MSP430F67621__) -#include "msp430f67621.h" - -#elif defined (__MSP430F67641__) -#include "msp430f67641.h" - -#elif defined (__MSP430F6720A__) -#include "msp430f6720a.h" - -#elif defined (__MSP430F6721A__) -#include "msp430f6721a.h" - -#elif defined (__MSP430F6723A__) -#include "msp430f6723a.h" - -#elif defined (__MSP430F6724A__) -#include "msp430f6724a.h" - -#elif defined (__MSP430F6725A__) -#include "msp430f6725a.h" - -#elif defined (__MSP430F6726A__) -#include "msp430f6726a.h" - -#elif defined (__MSP430F6730A__) -#include "msp430f6730a.h" - -#elif defined (__MSP430F6731A__) -#include "msp430f6731a.h" - -#elif defined (__MSP430F6733A__) -#include "msp430f6733a.h" - -#elif defined (__MSP430F6734A__) -#include "msp430f6734a.h" - -#elif defined (__MSP430F6735A__) -#include "msp430f6735a.h" - -#elif defined (__MSP430F6736A__) -#include "msp430f6736a.h" - -#elif defined (__MSP430F67621A__) -#include "msp430f67621a.h" - -#elif defined (__MSP430F67641A__) -#include "msp430f67641a.h" - -#elif defined (__MSP430F67451__) -#include "msp430f67451.h" - -#elif defined (__MSP430F67651__) -#include "msp430f67651.h" - -#elif defined (__MSP430F67751__) -#include "msp430f67751.h" - -#elif defined (__MSP430F67461__) -#include "msp430f67461.h" - -#elif defined (__MSP430F67661__) -#include "msp430f67661.h" - -#elif defined (__MSP430F67761__) -#include "msp430f67761.h" - -#elif defined (__MSP430F67471__) -#include "msp430f67471.h" - -#elif defined (__MSP430F67671__) -#include "msp430f67671.h" - -#elif defined (__MSP430F67771__) -#include "msp430f67771.h" - -#elif defined (__MSP430F67481__) -#include "msp430f67481.h" - -#elif defined (__MSP430F67681__) -#include "msp430f67681.h" - -#elif defined (__MSP430F67781__) -#include "msp430f67781.h" - -#elif defined (__MSP430F67491__) -#include "msp430f67491.h" - -#elif defined (__MSP430F67691__) -#include "msp430f67691.h" - -#elif defined (__MSP430F67791__) -#include "msp430f67791.h" - -#elif defined (__MSP430F6745__) -#include "msp430f6745.h" - -#elif defined (__MSP430F6765__) -#include "msp430f6765.h" - -#elif defined (__MSP430F6775__) -#include "msp430f6775.h" - -#elif defined (__MSP430F6746__) -#include "msp430f6746.h" - -#elif defined (__MSP430F6766__) -#include "msp430f6766.h" - -#elif defined (__MSP430F6776__) -#include "msp430f6776.h" - -#elif defined (__MSP430F6747__) -#include "msp430f6747.h" - -#elif defined (__MSP430F6767__) -#include "msp430f6767.h" - -#elif defined (__MSP430F6777__) -#include "msp430f6777.h" - -#elif defined (__MSP430F6748__) -#include "msp430f6748.h" - -#elif defined (__MSP430F6768__) -#include "msp430f6768.h" - -#elif defined (__MSP430F6778__) -#include "msp430f6778.h" - -#elif defined (__MSP430F6749__) -#include "msp430f6749.h" - -#elif defined (__MSP430F6769__) -#include "msp430f6769.h" - -#elif defined (__MSP430F6779__) -#include "msp430f6779.h" - -#elif defined (__MSP430F67451A__) -#include "msp430f67451a.h" - -#elif defined (__MSP430F67651A__) -#include "msp430f67651a.h" - -#elif defined (__MSP430F67751A__) -#include "msp430f67751a.h" - -#elif defined (__MSP430F67461A__) -#include "msp430f67461a.h" - -#elif defined (__MSP430F67661A__) -#include "msp430f67661a.h" - -#elif defined (__MSP430F67761A__) -#include "msp430f67761a.h" - -#elif defined (__MSP430F67471A__) -#include "msp430f67471a.h" - -#elif defined (__MSP430F67671A__) -#include "msp430f67671a.h" - -#elif defined (__MSP430F67771A__) -#include "msp430f67771a.h" - -#elif defined (__MSP430F67481A__) -#include "msp430f67481a.h" - -#elif defined (__MSP430F67681A__) -#include "msp430f67681a.h" - -#elif defined (__MSP430F67781A__) -#include "msp430f67781a.h" - -#elif defined (__MSP430F67491A__) -#include "msp430f67491a.h" - -#elif defined (__MSP430F67691A__) -#include "msp430f67691a.h" - -#elif defined (__MSP430F67791A__) -#include "msp430f67791a.h" - -#elif defined (__MSP430F6745A__) -#include "msp430f6745a.h" - -#elif defined (__MSP430F6765A__) -#include "msp430f6765a.h" - -#elif defined (__MSP430F6775A__) -#include "msp430f6775a.h" - -#elif defined (__MSP430F6746A__) -#include "msp430f6746a.h" - -#elif defined (__MSP430F6766A__) -#include "msp430f6766a.h" - -#elif defined (__MSP430F6776A__) -#include "msp430f6776a.h" - -#elif defined (__MSP430F6747A__) -#include "msp430f6747a.h" - -#elif defined (__MSP430F6767A__) -#include "msp430f6767a.h" - -#elif defined (__MSP430F6777A__) -#include "msp430f6777a.h" - -#elif defined (__MSP430F6748A__) -#include "msp430f6748a.h" - -#elif defined (__MSP430F6768A__) -#include "msp430f6768a.h" - -#elif defined (__MSP430F6778A__) -#include "msp430f6778a.h" - -#elif defined (__MSP430F6749A__) -#include "msp430f6749a.h" - -#elif defined (__MSP430F6769A__) -#include "msp430f6769a.h" - -#elif defined (__MSP430F6779A__) -#include "msp430f6779a.h" - -#elif defined (__MSP430FR5720__) -#include "msp430fr5720.h" - -#elif defined (__MSP430FR5721__) -#include "msp430fr5721.h" - -#elif defined (__MSP430FR5722__) -#include "msp430fr5722.h" - -#elif defined (__MSP430FR5723__) -#include "msp430fr5723.h" - -#elif defined (__MSP430FR5724__) -#include "msp430fr5724.h" - -#elif defined (__MSP430FR5725__) -#include "msp430fr5725.h" - -#elif defined (__MSP430FR5726__) -#include "msp430fr5726.h" - -#elif defined (__MSP430FR5727__) -#include "msp430fr5727.h" - -#elif defined (__MSP430FR5728__) -#include "msp430fr5728.h" - -#elif defined (__MSP430FR5729__) -#include "msp430fr5729.h" - -#elif defined (__MSP430FR5730__) -#include "msp430fr5730.h" - -#elif defined (__MSP430FR5731__) -#include "msp430fr5731.h" - -#elif defined (__MSP430FR5732__) -#include "msp430fr5732.h" - -#elif defined (__MSP430FR5733__) -#include "msp430fr5733.h" - -#elif defined (__MSP430FR5734__) -#include "msp430fr5734.h" - -#elif defined (__MSP430FR5735__) -#include "msp430fr5735.h" - -#elif defined (__MSP430FR5736__) -#include "msp430fr5736.h" - -#elif defined (__MSP430FR5737__) -#include "msp430fr5737.h" - -#elif defined (__MSP430FR5738__) -#include "msp430fr5738.h" - -#elif defined (__MSP430FR5739__) -#include "msp430fr5739.h" - -#elif defined (__MSP430G2211__) -#include "msp430g2211.h" - -#elif defined (__MSP430G2201__) -#include "msp430g2201.h" - -#elif defined (__MSP430G2111__) -#include "msp430g2111.h" - -#elif defined (__MSP430G2101__) -#include "msp430g2101.h" - -#elif defined (__MSP430G2001__) -#include "msp430g2001.h" - -#elif defined (__MSP430G2231__) -#include "msp430g2231.h" - -#elif defined (__MSP430G2221__) -#include "msp430g2221.h" - -#elif defined (__MSP430G2131__) -#include "msp430g2131.h" - -#elif defined (__MSP430G2121__) -#include "msp430g2121.h" - -#elif defined (__MSP430AFE221__) -#include "msp430afe221.h" - -#elif defined (__MSP430AFE231__) -#include "msp430afe231.h" - -#elif defined (__MSP430AFE251__) -#include "msp430afe251.h" - -#elif defined (__MSP430AFE222__) -#include "msp430afe222.h" - -#elif defined (__MSP430AFE232__) -#include "msp430afe232.h" - -#elif defined (__MSP430AFE252__) -#include "msp430afe252.h" - -#elif defined (__MSP430AFE223__) -#include "msp430afe223.h" - -#elif defined (__MSP430AFE233__) -#include "msp430afe233.h" - -#elif defined (__MSP430AFE253__) -#include "msp430afe253.h" - -#elif defined (__MSP430G2102__) -#include "msp430g2102.h" - -#elif defined (__MSP430G2202__) -#include "msp430g2202.h" - -#elif defined (__MSP430G2302__) -#include "msp430g2302.h" - -#elif defined (__MSP430G2402__) -#include "msp430g2402.h" - -#elif defined (__MSP430G2132__) -#include "msp430g2132.h" - -#elif defined (__MSP430G2232__) -#include "msp430g2232.h" - -#elif defined (__MSP430G2332__) -#include "msp430g2332.h" - -#elif defined (__MSP430G2432__) -#include "msp430g2432.h" - -#elif defined (__MSP430G2112__) -#include "msp430g2112.h" - -#elif defined (__MSP430G2212__) -#include "msp430g2212.h" - -#elif defined (__MSP430G2312__) -#include "msp430g2312.h" - -#elif defined (__MSP430G2412__) -#include "msp430g2412.h" - -#elif defined (__MSP430G2152__) -#include "msp430g2152.h" - -#elif defined (__MSP430G2252__) -#include "msp430g2252.h" - -#elif defined (__MSP430G2352__) -#include "msp430g2352.h" - -#elif defined (__MSP430G2452__) -#include "msp430g2452.h" - -#elif defined (__MSP430G2113__) -#include "msp430g2113.h" - -#elif defined (__MSP430G2213__) -#include "msp430g2213.h" - -#elif defined (__MSP430G2313__) -#include "msp430g2313.h" - -#elif defined (__MSP430G2413__) -#include "msp430g2413.h" - -#elif defined (__MSP430G2513__) -#include "msp430g2513.h" - -#elif defined (__MSP430G2153__) -#include "msp430g2153.h" - -#elif defined (__MSP430G2253__) -#include "msp430g2253.h" - -#elif defined (__MSP430G2353__) -#include "msp430g2353.h" - -#elif defined (__MSP430G2453__) -#include "msp430g2453.h" - -#elif defined (__MSP430G2553__) -#include "msp430g2553.h" - -#elif defined (__MSP430G2203__) -#include "msp430g2203.h" - -#elif defined (__MSP430G2303__) -#include "msp430g2303.h" - -#elif defined (__MSP430G2403__) -#include "msp430g2403.h" - -#elif defined (__MSP430G2233__) -#include "msp430g2233.h" - -#elif defined (__MSP430G2333__) -#include "msp430g2333.h" - -#elif defined (__MSP430G2433__) -#include "msp430g2433.h" - -#elif defined (__MSP430G2533__) -#include "msp430g2533.h" - -#elif defined (__MSP430TCH5E__) -#include "msp430tch5e.h" - -#elif defined (__MSP430G2444__) -#include "msp430g2444.h" - -#elif defined (__MSP430G2544__) -#include "msp430g2544.h" - -#elif defined (__MSP430G2744__) -#include "msp430g2744.h" - -#elif defined (__MSP430G2755__) -#include "msp430g2755.h" - -#elif defined (__MSP430G2855__) -#include "msp430g2855.h" - -#elif defined (__MSP430G2955__) -#include "msp430g2955.h" - -#elif defined (__MSP430G2230__) -#include "msp430g2230.h" - -#elif defined (__MSP430G2210__) -#include "msp430g2210.h" - -#elif defined (__MSP430BT5190__) -#include "msp430bt5190.h" - -#elif defined (__MSP430FR5857__) -#include "msp430fr5857.h" - -#elif defined (__MSP430FR5858__) -#include "msp430fr5858.h" - -#elif defined (__MSP430FR5859__) -#include "msp430fr5859.h" - -#elif defined (__MSP430FR5847__) -#include "msp430fr5847.h" - -#elif defined (__MSP430FR58471__) -#include "msp430fr58471.h" - -#elif defined (__MSP430FR5848__) -#include "msp430fr5848.h" - -#elif defined (__MSP430FR5849__) -#include "msp430fr5849.h" - -#elif defined (__MSP430FR5867__) -#include "msp430fr5867.h" - -#elif defined (__MSP430FR58671__) -#include "msp430fr58671.h" - -#elif defined (__MSP430FR5868__) -#include "msp430fr5868.h" - -#elif defined (__MSP430FR5869__) -#include "msp430fr5869.h" - -#elif defined (__MSP430FR5957__) -#include "msp430fr5957.h" - -#elif defined (__MSP430FR5958__) -#include "msp430fr5958.h" - -#elif defined (__MSP430FR5959__) -#include "msp430fr5959.h" - -#elif defined (__MSP430FR5947__) -#include "msp430fr5947.h" - -#elif defined (__MSP430FR59471__) -#include "msp430fr59471.h" - -#elif defined (__MSP430FR5948__) -#include "msp430fr5948.h" - -#elif defined (__MSP430FR5949__) -#include "msp430fr5949.h" - -#elif defined (__MSP430FR5967__) -#include "msp430fr5967.h" - -#elif defined (__MSP430FR5968__) -#include "msp430fr5968.h" - -#elif defined (__MSP430FR5969__) -#include "msp430fr5969.h" - -#elif defined (__MSP430FR59691__) -#include "msp430fr59691.h" - -#elif defined (__MSP430FR5962__) -#include "msp430fr5962.h" - -#elif defined (__MSP430FR5964__) -#include "msp430fr5964.h" - -#elif defined (__MSP430FR5992__) -#include "msp430fr5992.h" - -#elif defined (__MSP430FR5994__) -#include "msp430fr5994.h" - -#elif defined (__MSP430FR59941__) -#include "msp430fr59941.h" - -#elif defined (__MSP430i2020__) -#include "msp430i2020.h" - -#elif defined (__MSP430i2021__) -#include "msp430i2021.h" - -#elif defined (__MSP430i2030__) -#include "msp430i2030.h" - -#elif defined (__MSP430i2031__) -#include "msp430i2031.h" - -#elif defined (__MSP430i2040__) -#include "msp430i2040.h" - -#elif defined (__MSP430i2041__) -#include "msp430i2041.h" - -#elif defined (__RF430FRL152H__) -#include "rf430frl152h.h" - -#elif defined (__RF430FRL153H__) -#include "rf430frl153h.h" - -#elif defined (__RF430FRL154H__) -#include "rf430frl154h.h" - -#elif defined (__RF430FRL152H_ROM__) -#include "rf430frl152h_rom.h" - -#elif defined (__RF430FRL153H_ROM__) -#include "rf430frl153h_rom.h" - -#elif defined (__RF430FRL154H_ROM__) -#include "rf430frl154h_rom.h" - -#elif defined (__RF430F5175__) -#include "rf430f5175.h" - -#elif defined (__RF430F5155__) -#include "rf430f5155.h" - -#elif defined (__RF430F5144__) -#include "rf430f5144.h" - -#elif defined (__MSP430FR69271__) -#include "msp430fr69271.h" - -#elif defined (__MSP430FR68791__) -#include "msp430fr68791.h" - -#elif defined (__MSP430FR69791__) -#include "msp430fr69791.h" - -#elif defined (__MSP430FR6927__) -#include "msp430fr6927.h" - -#elif defined (__MSP430FR6928__) -#include "msp430fr6928.h" - -#elif defined (__MSP430FR6877__) -#include "msp430fr6877.h" - -#elif defined (__MSP430FR6977__) -#include "msp430fr6977.h" - -#elif defined (__MSP430FR6879__) -#include "msp430fr6879.h" - -#elif defined (__MSP430FR6979__) -#include "msp430fr6979.h" - -#elif defined (__MSP430FR58891__) -#include "msp430fr58891.h" - -#elif defined (__MSP430FR68891__) -#include "msp430fr68891.h" - -#elif defined (__MSP430FR59891__) -#include "msp430fr59891.h" - -#elif defined (__MSP430FR69891__) -#include "msp430fr69891.h" - -#elif defined (__MSP430FR5887__) -#include "msp430fr5887.h" - -#elif defined (__MSP430FR5888__) -#include "msp430fr5888.h" - -#elif defined (__MSP430FR5889__) -#include "msp430fr5889.h" - -#elif defined (__MSP430FR6887__) -#include "msp430fr6887.h" - -#elif defined (__MSP430FR6888__) -#include "msp430fr6888.h" - -#elif defined (__MSP430FR6889__) -#include "msp430fr6889.h" - -#elif defined (__MSP430FR5986__) -#include "msp430fr5986.h" - -#elif defined (__MSP430FR5987__) -#include "msp430fr5987.h" - -#elif defined (__MSP430FR5988__) -#include "msp430fr5988.h" - -#elif defined (__MSP430FR5989__) -#include "msp430fr5989.h" - -#elif defined (__MSP430FR6987__) -#include "msp430fr6987.h" - -#elif defined (__MSP430FR6988__) -#include "msp430fr6988.h" - -#elif defined (__MSP430FR6989__) -#include "msp430fr6989.h" - -#elif defined (__MSP430FR5922__) -#include "msp430fr5922.h" - -#elif defined (__MSP430FR5870__) -#include "msp430fr5870.h" - -#elif defined (__MSP430FR5970__) -#include "msp430fr5970.h" - -#elif defined (__MSP430FR5872__) -#include "msp430fr5872.h" - -#elif defined (__MSP430FR5972__) -#include "msp430fr5972.h" - -#elif defined (__MSP430FR6820__) -#include "msp430fr6820.h" - -#elif defined (__MSP430FR6920__) -#include "msp430fr6920.h" - -#elif defined (__MSP430FR6822__) -#include "msp430fr6822.h" - -#elif defined (__MSP430FR6922__) -#include "msp430fr6922.h" - -#elif defined (__MSP430FR6870__) -#include "msp430fr6870.h" - -#elif defined (__MSP430FR6970__) -#include "msp430fr6970.h" - -#elif defined (__MSP430FR6872__) -#include "msp430fr6872.h" - -#elif defined (__MSP430FR6972__) -#include "msp430fr6972.h" - -#elif defined (__MSP430FR59221__) -#include "msp430fr59221.h" - -#elif defined (__MSP430FR58721__) -#include "msp430fr58721.h" - -#elif defined (__MSP430FR59721__) -#include "msp430fr59721.h" - -#elif defined (__MSP430FR68221__) -#include "msp430fr68221.h" - -#elif defined (__MSP430FR69221__) -#include "msp430fr69221.h" - -#elif defined (__MSP430FR68721__) -#include "msp430fr68721.h" - -#elif defined (__MSP430FR69721__) -#include "msp430fr69721.h" - -#elif defined (__MSP430SL5438A__) -#include "msp430sl5438a.h" - -#elif defined (__MSP430FR4131__) -#include "msp430fr4131.h" - -#elif defined (__MSP430FR4132__) -#include "msp430fr4132.h" - -#elif defined (__MSP430FR4133__) -#include "msp430fr4133.h" - -#elif defined (__MSP430FR2032__) -#include "msp430fr2032.h" - -#elif defined (__MSP430FR2033__) -#include "msp430fr2033.h" - -#elif defined (__MSP430FR2000__) -#include "msp430fr2000.h" - -#elif defined (__MSP430FR2100__) -#include "msp430fr2100.h" - -#elif defined (__MSP430FR2110__) -#include "msp430fr2110.h" - -#elif defined (__MSP430FR2111__) -#include "msp430fr2111.h" - -#elif defined (__MSP430FR2310__) -#include "msp430fr2310.h" - -#elif defined (__MSP430FR2311__) -#include "msp430fr2311.h" - -#elif defined (__MSP430FR2422__) -#include "msp430fr2422.h" - -#elif defined (__MSP430FR2433__) -#include "msp430fr2433.h" - -#elif defined (__MSP430FR2512__) -#include "msp430fr2512.h" - -#elif defined (__MSP430FR2522__) -#include "msp430fr2522.h" - -#elif defined (__MSP430FR2532__) -#include "msp430fr2532.h" - -#elif defined (__MSP430FR2533__) -#include "msp430fr2533.h" - -#elif defined (__MSP430FR2632__) -#include "msp430fr2632.h" - -#elif defined (__MSP430FR2633__) -#include "msp430fr2633.h" - -#elif defined (__MSP430F5252__) -#include "msp430f5252.h" - -#elif defined (__MSP430F5253__) -#include "msp430f5253.h" - -#elif defined (__MSP430F5254__) -#include "msp430f5254.h" - -#elif defined (__MSP430F5255__) -#include "msp430f5255.h" - -#elif defined (__MSP430F5256__) -#include "msp430f5256.h" - -#elif defined (__MSP430F5257__) -#include "msp430f5257.h" - -#elif defined (__MSP430F5258__) -#include "msp430f5258.h" - -#elif defined (__MSP430F5259__) -#include "msp430f5259.h" - -#elif defined (__MSP430FR6035__) -#include "msp430fr6035.h" - -#elif defined (__MSP430FR6037__) -#include "msp430fr6037.h" - -#elif defined (__MSP430FR60371__) -#include "msp430fr60371.h" - -#elif defined (__MSP430FR6045__) -#include "msp430fr6045.h" - -#elif defined (__MSP430FR6047__) -#include "msp430fr6047.h" - -#elif defined (__MSP430FR60471__) -#include "msp430fr60471.h" - -#elif defined (__MSP430FR5041__) -#include "msp430fr5041.h" - -#elif defined (__MSP430FR5043__) -#include "msp430fr5043.h" - -#elif defined (__MSP430FR50431__) -#include "msp430fr50431.h" - -#elif defined (__MSP430FR6041__) -#include "msp430fr6041.h" - -#elif defined (__MSP430FR6043__) -#include "msp430fr6043.h" - -#elif defined (__MSP430FR60431__) -#include "msp430fr60431.h" - -#elif defined (__MSP430FR2153__) -#include "msp430fr2153.h" - -#elif defined (__MSP430FR2155__) -#include "msp430fr2155.h" - -#elif defined (__MSP430FR2353__) -#include "msp430fr2353.h" - -#elif defined (__MSP430FR2355__) -#include "msp430fr2355.h" - -#elif defined (__MSP430FR2475__) -#include "msp430fr2475.h" - -#elif defined (__MSP430FR2476__) -#include "msp430fr2476.h" - -#elif defined (__MSP430FR2675__) -#include "msp430fr2675.h" - -#elif defined (__MSP430FR2676__) -#include "msp430fr2676.h" - -#elif defined (__MSP430XGENERIC__) -#include "msp430xgeneric.h" - -#elif defined (__MSP430F5XX_6XXGENERIC__) -#include "msp430f5xx_6xxgeneric.h" - -#elif defined (__MSP430FR5XX_6XXGENERIC__) -#include "msp430fr5xx_6xxgeneric.h" - -#elif defined (__MSP430FR2XX_4XXGENERIC__) -#include "msp430fr2xx_4xxgeneric.h" - -#elif defined (__MSP430FR57XXGENERIC__) -#include "msp430fr57xxgeneric.h" - -#elif defined (__MSP430I2XXGENERIC__) -#include "msp430i2xxgeneric.h" - -/******************************************************************** - * msp430 generic - ********************************************************************/ -#elif defined (__MSP430GENERIC__) -#error "msp430 generic device does not have a default include file" - -#elif defined (__MSP430XGENERIC__) -#error "msp430X generic device does not have a default include file" - - -/******************************************************************** - * - ********************************************************************/ -#else -#error "Failed to match a default include file" -#endif - -#endif /* #ifndef __msp430 */ - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.h b/hw/bsp/msp_exp430f5529lp/msp430f5529.h deleted file mode 100644 index e7e5d31fa..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529.h +++ /dev/null @@ -1,4789 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/******************************************************************** -* -* Standard register and bit definitions for the Texas Instruments -* MSP430 microcontroller. -* -* This file supports assembler and C development for -* MSP430F5529 devices. -* -* Texas Instruments, Version 1.4 -* -* Rev. 1.0, Setup -* Rev. 1.1, Fixed Error in DMA Trigger Definitons -* Rev. 1.2, fixed SYSUNIV_BUSIFG definition -* fixed wrong bit definition in PM5CTL0 (LOCKLPM5) -* Rev. 1.3, Changed access type of DMAxSZ registers to word only -* Rev. 1.4 Changed access type of TimerA/B registers to word only -* -********************************************************************/ - -#ifndef __MSP430F5529 -#define __MSP430F5529 - -#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ -#define __MSP430F5XX_6XX_FAMILY__ - -#define __MSP430_HEADER_VERSION__ 1207 - -#ifdef __cplusplus -extern "C" { -#endif - - -/*----------------------------------------------------------------------------*/ -/* PERIPHERAL FILE MAP */ -/*----------------------------------------------------------------------------*/ - -#define __MSP430_TI_HEADERS__ - -#include <iomacros.h> - - -/************************************************************ -* STANDARD BITS -************************************************************/ - -#define BIT0 (0x0001) -#define BIT1 (0x0002) -#define BIT2 (0x0004) -#define BIT3 (0x0008) -#define BIT4 (0x0010) -#define BIT5 (0x0020) -#define BIT6 (0x0040) -#define BIT7 (0x0080) -#define BIT8 (0x0100) -#define BIT9 (0x0200) -#define BITA (0x0400) -#define BITB (0x0800) -#define BITC (0x1000) -#define BITD (0x2000) -#define BITE (0x4000) -#define BITF (0x8000) - -/************************************************************ -* STATUS REGISTER BITS -************************************************************/ - -#define C (0x0001) -#define Z (0x0002) -#define N (0x0004) -#define V (0x0100) -#define GIE (0x0008) -#define CPUOFF (0x0010) -#define OSCOFF (0x0020) -#define SCG0 (0x0040) -#define SCG1 (0x0080) - -/* Low Power Modes coded with Bits 4-7 in SR */ - -#ifndef __STDC__ /* Begin #defines for assembler */ -#define LPM0 (CPUOFF) -#define LPM1 (SCG0+CPUOFF) -#define LPM2 (SCG1+CPUOFF) -#define LPM3 (SCG1+SCG0+CPUOFF) -#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) -/* End #defines for assembler */ - -#else /* Begin #defines for C */ -#define LPM0_bits (CPUOFF) -#define LPM1_bits (SCG0+CPUOFF) -#define LPM2_bits (SCG1+CPUOFF) -#define LPM3_bits (SCG1+SCG0+CPUOFF) -#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) - -#include "in430.h" - -#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ -#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ -#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ -#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ -#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ -#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ -#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ -#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ -#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ -#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ -#endif /* End #defines for C */ - -/************************************************************ -* PERIPHERAL FILE MAP -************************************************************/ - -/************************************************************ -* ADC12 PLUS -************************************************************/ -#define __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_ADC12_PLUS__ 0x0700 -#define ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ - -sfr_w(ADC12CTL0); /* ADC12+ Control 0 */ -sfr_b(ADC12CTL0_L); /* ADC12+ Control 0 */ -sfr_b(ADC12CTL0_H); /* ADC12+ Control 0 */ -sfr_w(ADC12CTL1); /* ADC12+ Control 1 */ -sfr_b(ADC12CTL1_L); /* ADC12+ Control 1 */ -sfr_b(ADC12CTL1_H); /* ADC12+ Control 1 */ -sfr_w(ADC12CTL2); /* ADC12+ Control 2 */ -sfr_b(ADC12CTL2_L); /* ADC12+ Control 2 */ -sfr_b(ADC12CTL2_H); /* ADC12+ Control 2 */ -sfr_w(ADC12IFG); /* ADC12+ Interrupt Flag */ -sfr_b(ADC12IFG_L); /* ADC12+ Interrupt Flag */ -sfr_b(ADC12IFG_H); /* ADC12+ Interrupt Flag */ -sfr_w(ADC12IE); /* ADC12+ Interrupt Enable */ -sfr_b(ADC12IE_L); /* ADC12+ Interrupt Enable */ -sfr_b(ADC12IE_H); /* ADC12+ Interrupt Enable */ -sfr_w(ADC12IV); /* ADC12+ Interrupt Vector Word */ -sfr_b(ADC12IV_L); /* ADC12+ Interrupt Vector Word */ -sfr_b(ADC12IV_H); /* ADC12+ Interrupt Vector Word */ - -sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */ -sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */ -sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */ -sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */ -sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */ -sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */ -sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */ -sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */ -sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */ -sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */ -sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */ -sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */ -sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */ -sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */ -sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */ -sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */ -sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */ -sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */ -sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */ -sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */ -sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */ -sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */ -sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */ -sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */ -sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */ -sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */ -sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */ -sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */ -sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */ -sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */ -sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */ -sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */ -sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */ -sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */ -sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */ -sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */ -sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */ -sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */ -sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */ -sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */ -sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */ -sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */ -sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */ -sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */ -sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */ -sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */ -sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */ -sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */ -#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ -#ifndef __STDC__ -#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ -#else -#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ -#endif - -sfr_b(ADC12MCTL0); /* ADC12 Memory Control 0 */ -sfr_b(ADC12MCTL1); /* ADC12 Memory Control 1 */ -sfr_b(ADC12MCTL2); /* ADC12 Memory Control 2 */ -sfr_b(ADC12MCTL3); /* ADC12 Memory Control 3 */ -sfr_b(ADC12MCTL4); /* ADC12 Memory Control 4 */ -sfr_b(ADC12MCTL5); /* ADC12 Memory Control 5 */ -sfr_b(ADC12MCTL6); /* ADC12 Memory Control 6 */ -sfr_b(ADC12MCTL7); /* ADC12 Memory Control 7 */ -sfr_b(ADC12MCTL8); /* ADC12 Memory Control 8 */ -sfr_b(ADC12MCTL9); /* ADC12 Memory Control 9 */ -sfr_b(ADC12MCTL10); /* ADC12 Memory Control 10 */ -sfr_b(ADC12MCTL11); /* ADC12 Memory Control 11 */ -sfr_b(ADC12MCTL12); /* ADC12 Memory Control 12 */ -sfr_b(ADC12MCTL13); /* ADC12 Memory Control 13 */ -sfr_b(ADC12MCTL14); /* ADC12 Memory Control 14 */ -sfr_b(ADC12MCTL15); /* ADC12 Memory Control 15 */ -#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ -#ifndef __STDC__ -#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ -#else -#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ -#endif - -/* ADC12CTL0 Control Bits */ -#define ADC12SC (0x0001) /* ADC12 Start Conversion */ -#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ -#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ -#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ -#define ADC12ON (0x0010) /* ADC12 On/enable */ -#define ADC12REFON (0x0020) /* ADC12 Reference on */ -#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ -#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ -#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ - -/* ADC12CTL0 Control Bits */ -#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ -#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ -#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ -#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ -#define ADC12ON_L (0x0010) /* ADC12 On/enable */ -#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ -#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ -#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ - -/* ADC12CTL0 Control Bits */ -#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ - -#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ -#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ -#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ -#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ -#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ -#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ -#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ -#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ -#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ -#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ -#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ -#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ -#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ -#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ -#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ -#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ - -#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ -#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ -#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ -#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ -#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ -#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ -#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ -#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ -#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ -#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ -#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ -#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ -#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ -#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ -#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ -#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12BUSY (0x0001) /* ADC12 Busy */ -#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ -#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ -#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ -#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ -#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ -#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ -#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ -#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ -#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ -#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ -#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ -#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ -#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ -#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ -#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ -#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ -#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ -#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ -#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ -#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ -#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ -#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ - -/* ADC12CTL1 Control Bits */ -#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ -#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ -#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ -#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ -#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ -#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ -#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ -#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ - -#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ -#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ -#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ -#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ - -#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ -#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ -#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ -#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ - -#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ -#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ -#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ -#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ -#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ -#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ -#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ -#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ - -#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ -#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ -#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ -#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ - -#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ -#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ -#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ -#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ -#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ -#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ -#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ -#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ -#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ -#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ -#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ -#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ -#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ -#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ -#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ -#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ - -/* ADC12CTL2 Control Bits */ -#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ -#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ -#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ -#define ADC12DF (0x0008) /* ADC12+ Data Format */ -#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ -#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ -#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ -#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ - -/* ADC12CTL2 Control Bits */ -#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ -#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ -#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ -#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ -#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ -#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ -#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ - -/* ADC12CTL2 Control Bits */ -#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ - -#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ -#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ -#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ -#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ - -/* ADC12MCTLx Control Bits */ -#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ -#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ -#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ -#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ -#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ -#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ -#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ -#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ - -#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ -#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ -#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ -#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ -#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ -#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ -#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ -#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ -#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ -#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ -#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ -#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ -#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ -#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ -#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ -#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ - -#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */ -#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */ -#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */ -#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */ -#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */ -#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */ -#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */ -#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */ - -#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ -#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ -#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ -#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ -#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ -#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ -#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ -#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ -#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ -#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ -#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ -#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ -#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ -#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ -#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ -#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ - -#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ -#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ -#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ -#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ -#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ -#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ -#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ -#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ - -#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ -#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ -#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ -#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ -#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ -#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ -#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ -#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ - -#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ -#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ -#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ -#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ -#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ -#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ -#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ -#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ -#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ -#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ -#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ -#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ -#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ -#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ -#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ -#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ - -#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ -#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ -#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ -#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ -#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ -#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ -#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ -#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ - -#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ -#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ -#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ -#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ -#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ -#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ -#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ -#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ - -/* ADC12IV Definitions */ -#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ -#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ -#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ -#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ -#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ -#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ -#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ -#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ -#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ -#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ -#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ -#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ -#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ -#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ -#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ -#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ -#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ -#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ -#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ - -/************************************************************ -* Comparator B -************************************************************/ -#define __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_COMPB__ 0x08C0 -#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ - -sfr_w(CBCTL0); /* Comparator B Control Register 0 */ -sfr_b(CBCTL0_L); /* Comparator B Control Register 0 */ -sfr_b(CBCTL0_H); /* Comparator B Control Register 0 */ -sfr_w(CBCTL1); /* Comparator B Control Register 1 */ -sfr_b(CBCTL1_L); /* Comparator B Control Register 1 */ -sfr_b(CBCTL1_H); /* Comparator B Control Register 1 */ -sfr_w(CBCTL2); /* Comparator B Control Register 2 */ -sfr_b(CBCTL2_L); /* Comparator B Control Register 2 */ -sfr_b(CBCTL2_H); /* Comparator B Control Register 2 */ -sfr_w(CBCTL3); /* Comparator B Control Register 3 */ -sfr_b(CBCTL3_L); /* Comparator B Control Register 3 */ -sfr_b(CBCTL3_H); /* Comparator B Control Register 3 */ -sfr_w(CBINT); /* Comparator B Interrupt Register */ -sfr_b(CBINT_L); /* Comparator B Interrupt Register */ -sfr_b(CBINT_H); /* Comparator B Interrupt Register */ -sfr_w(CBIV); /* Comparator B Interrupt Vector Word */ - -/* CBCTL0 Control Bits */ -#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ -#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ -#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ -#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ -#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ -#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ -#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ -#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ - -/* CBCTL0 Control Bits */ -#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ -#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ -#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ -#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ - -/* CBCTL0 Control Bits */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ -#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ -#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ -#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ - -#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ -#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ -#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ -#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ -#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ -#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ -#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ -#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ -#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ -#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ -#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ -#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ -#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ -#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ -#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ -#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ - -#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ -#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ -#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ -#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ -#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ -#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ -#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ -#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ -#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ -#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ -#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ -#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ -#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ -#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ -#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ -#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ - -/* CBCTL1 Control Bits */ -#define CBOUT (0x0001) /* Comp. B Output */ -#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ -#define CBF (0x0004) /* Comp. B Enable Output Filter */ -#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ -#define CBSHORT (0x0010) /* Comp. B Input Short */ -#define CBEX (0x0020) /* Comp. B Exchange Inputs */ -#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ -#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ -#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ -#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ -#define CBON (0x0400) /* Comp. B enable */ -#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ -#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBCTL1 Control Bits */ -#define CBOUT_L (0x0001) /* Comp. B Output */ -#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ -#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ -#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ -#define CBSHORT_L (0x0010) /* Comp. B Input Short */ -#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ -#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ -#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBCTL1 Control Bits */ -#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ -#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ -#define CBON_H (0x0004) /* Comp. B enable */ -#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ -#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ -#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ -#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ -#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ - -#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ -#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ -#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ -#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ - -/* CBCTL2 Control Bits */ -#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ -#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ -#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ -#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ -#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ -#define CBRSEL (0x0020) /* Comp. B Reference select */ -#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ -#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ -#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ -#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ -#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ -#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ -#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ -#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ -#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ -#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ - -/* CBCTL2 Control Bits */ -#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ -#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ -#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ -#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ -#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ -#define CBRSEL_L (0x0020) /* Comp. B Reference select */ -#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ -#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ - -/* CBCTL2 Control Bits */ -#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ -#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ -#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ -#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ -#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ -#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ -#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ -#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ - -#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ -#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ -#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ -#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ -#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ -#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ -#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ -#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ -#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ -#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ -#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ -#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ -#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ -#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ -#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ -#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ -#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ -#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ -#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ -#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ -#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ -#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ -#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ -#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ -#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ -#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ -#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ -#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ -#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ -#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ -#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ -#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ - -#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ -#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ -#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ -#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ - -#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ -#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ -#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ -#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ -#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ -#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ -#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ -#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ -#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ -#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ -#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ -#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ -#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ -#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ -#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ -#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ -#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ -#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ -#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ -#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ -#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ -#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ -#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ -#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ -#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ -#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ -#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ -#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ -#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ -#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ -#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ -#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ - -#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ -#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ -#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ -#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ - -#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ -#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ -#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ -#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ -#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ -#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ -#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ -#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ -#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ -#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ -#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ -#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ -#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ -#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ -#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ -#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ - -#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ -#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ -#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ -#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ -#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ -#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ -#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ -#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ - -#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ -#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ -#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ -#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ -#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ -#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ -#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ -#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ - -/* CBINT Control Bits */ -#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ -#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -#define CBIE (0x0100) /* Comp. B Interrupt Enable */ -#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBINT Control Bits */ -#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ -#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBINT Control Bits */ -//#define RESERVED (0x0004) /* Comp. B */ -//#define RESERVED (0x0008) /* Comp. B */ -//#define RESERVED (0x0010) /* Comp. B */ -//#define RESERVED (0x0020) /* Comp. B */ -//#define RESERVED (0x0040) /* Comp. B */ -//#define RESERVED (0x0080) /* Comp. B */ -#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ -#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ -//#define RESERVED (0x0400) /* Comp. B */ -//#define RESERVED (0x0800) /* Comp. B */ -//#define RESERVED (0x1000) /* Comp. B */ -//#define RESERVED (0x2000) /* Comp. B */ -//#define RESERVED (0x4000) /* Comp. B */ -//#define RESERVED (0x8000) /* Comp. B */ - -/* CBIV Definitions */ -#define CBIV_NONE (0x0000) /* No Interrupt pending */ -#define CBIV_CBIFG (0x0002) /* CBIFG */ -#define CBIV_CBIIFG (0x0004) /* CBIIFG */ - -/************************************************************* -* CRC Module -*************************************************************/ -#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_CRC__ 0x0150 -#define CRC_BASE __MSP430_BASEADDRESS_CRC__ - -sfr_w(CRCDI); /* CRC Data In Register */ -sfr_b(CRCDI_L); /* CRC Data In Register */ -sfr_b(CRCDI_H); /* CRC Data In Register */ -sfr_w(CRCDIRB); /* CRC data in reverse byte Register */ -sfr_b(CRCDIRB_L); /* CRC data in reverse byte Register */ -sfr_b(CRCDIRB_H); /* CRC data in reverse byte Register */ -sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register */ -sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register */ -sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register */ -sfr_w(CRCRESR); /* CRC reverse result Register */ -sfr_b(CRCRESR_L); /* CRC reverse result Register */ -sfr_b(CRCRESR_H); /* CRC reverse result Register */ - -/************************************************************ -* DMA_X -************************************************************/ -#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500 -#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ - -sfr_w(DMACTL0); /* DMA Module Control 0 */ -sfr_w(DMACTL1); /* DMA Module Control 1 */ -sfr_w(DMACTL2); /* DMA Module Control 2 */ -sfr_w(DMACTL3); /* DMA Module Control 3 */ -sfr_w(DMACTL4); /* DMA Module Control 4 */ -sfr_w(DMAIV); /* DMA Interrupt Vector Word */ - -sfr_w(DMA0CTL); /* DMA Channel 0 Control */ -sfr_l(DMA0SA); /* DMA Channel 0 Source Address */ -sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */ -sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */ -sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */ -sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */ - -sfr_w(DMA1CTL); /* DMA Channel 1 Control */ -sfr_l(DMA1SA); /* DMA Channel 1 Source Address */ -sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */ -sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */ -sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */ -sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */ - -sfr_w(DMA2CTL); /* DMA Channel 2 Control */ -sfr_l(DMA2SA); /* DMA Channel 2 Source Address */ -sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */ -sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */ -sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */ -sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */ - -/* DMACTL0 Control Bits */ -#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ -#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ -#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ -#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ -#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ -#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ -#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ -#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ -#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ -#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ - -/* DMACTL01 Control Bits */ -#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ -#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ -#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ -#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ -#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ - -/* DMACTL4 Control Bits */ -#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ -#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ -#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ - -/* DMAxCTL Control Bits */ -#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ -#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ -#define DMAIE (0x0004) /* DMA interrupt enable */ -#define DMAIFG (0x0008) /* DMA interrupt flag */ -#define DMAEN (0x0010) /* DMA enable */ -#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ -#define DMASRCBYTE (0x0040) /* DMA source byte */ -#define DMADSTBYTE (0x0080) /* DMA destination byte */ -#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ -#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ -#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ -#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ -#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ -#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ -#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ - -#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ -#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ -#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ -#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ - -#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ -#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ -#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ -#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ - -#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ -#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ -#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ -#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ - -#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ -#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ -#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ -#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ -#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ -#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ -#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ -#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ - -/* DMAIV Definitions */ -#define DMAIV_NONE (0x0000) /* No Interrupt pending */ -#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ -#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ -#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ - -#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ -#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ -#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ -#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ -#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ -#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ -#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ -#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ -#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ -#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ -#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ -#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ -#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ -#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ -#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ -#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ -#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ -#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ -#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ -#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ -#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: USB ready */ -#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ -#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ -#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ -#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ -#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ -#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ -#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ -#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ -#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ -#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ -#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ -#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ -#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ -#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ -#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ -#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ -#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ -#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ -#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ -#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ -#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ -#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ -#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ -#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ -#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ -#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ -#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ -#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ -#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ -#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ -#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ -#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ -#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ -#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ -#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ -#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ -#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ -#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ -#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ -#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ -#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ -#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ -#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ -#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ -#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ -#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: USB ready */ -#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ -#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ -#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ -#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA0TSEL__TA2CCR2 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ -#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ -#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ -#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ -#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ -#define DMA0TSEL__RES14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ -#define DMA0TSEL__RES15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ -#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ -#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ -#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ -#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ -#define DMA0TSEL__USCIA1RX (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ -#define DMA0TSEL__USCIA1TX (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ -#define DMA0TSEL__USCIB1RX (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ -#define DMA0TSEL__USCIB1TX (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ -#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ -#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ -#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ -#define DMA0TSEL__USB_FNRXD (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ -#define DMA0TSEL__USB_READY (0x001C) /* DMA channel 0 transfer select 28: USB ready */ -#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ -#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ -#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ -#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA1TSEL__TA2CCR2 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ -#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ -#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ -#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ -#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ -#define DMA1TSEL__RES14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ -#define DMA1TSEL__RES15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ -#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ -#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ -#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ -#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ -#define DMA1TSEL__USCIA1RX (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ -#define DMA1TSEL__USCIA1TX (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ -#define DMA1TSEL__USCIB1RX (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ -#define DMA1TSEL__USCIB1TX (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ -#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ -#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ -#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ -#define DMA1TSEL__USB_FNRXD (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ -#define DMA1TSEL__USB_READY (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ -#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ -#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ -#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ - -#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ -#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ -#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ -#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ -#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ -#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ -#define DMA2TSEL__TA2CCR2 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ -#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ -#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ -#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ -#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ -#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ -#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ -#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ -#define DMA2TSEL__RES14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ -#define DMA2TSEL__RES15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ -#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ -#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ -#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ -#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ -#define DMA2TSEL__USCIA1RX (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ -#define DMA2TSEL__USCIA1TX (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ -#define DMA2TSEL__USCIB1RX (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ -#define DMA2TSEL__USCIB1TX (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ -#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ -#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ -#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ -#define DMA2TSEL__USB_FNRXD (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ -#define DMA2TSEL__USB_READY (0x001C) /* DMA channel 2 transfer select 28: USB ready */ -#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ -#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ -#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ - -/************************************************************* -* Flash Memory -*************************************************************/ -#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_FLASH__ 0x0140 -#define FLASH_BASE __MSP430_BASEADDRESS_FLASH__ - -sfr_w(FCTL1); /* FLASH Control 1 */ -sfr_b(FCTL1_L); /* FLASH Control 1 */ -sfr_b(FCTL1_H); /* FLASH Control 1 */ -//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */ -sfr_w(FCTL3); /* FLASH Control 3 */ -sfr_b(FCTL3_L); /* FLASH Control 3 */ -sfr_b(FCTL3_H); /* FLASH Control 3 */ -sfr_w(FCTL4); /* FLASH Control 4 */ -sfr_b(FCTL4_L); /* FLASH Control 4 */ -sfr_b(FCTL4_H); /* FLASH Control 4 */ - -#define FRPW (0x9600) /* Flash password returned by read */ -#define FWPW (0xA500) /* Flash password for write */ -#define FXPW (0x3300) /* for use with XOR instruction */ -#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ -#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ -#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ - -/* FCTL1 Control Bits */ -//#define RESERVED (0x0001) /* Reserved */ -#define ERASE (0x0002) /* Enable bit for Flash segment erase */ -#define MERAS (0x0004) /* Enable bit for Flash mass erase */ -//#define RESERVED (0x0008) /* Reserved */ -//#define RESERVED (0x0010) /* Reserved */ -#define SWRT (0x0020) /* Smart Write enable */ -#define WRT (0x0040) /* Enable bit for Flash write */ -#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ - -/* FCTL1 Control Bits */ -//#define RESERVED (0x0001) /* Reserved */ -#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ -#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ -//#define RESERVED (0x0008) /* Reserved */ -//#define RESERVED (0x0010) /* Reserved */ -#define SWRT_L (0x0020) /* Smart Write enable */ -#define WRT_L (0x0040) /* Enable bit for Flash write */ -#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ - -/* FCTL3 Control Bits */ -#define BUSY (0x0001) /* Flash busy: 1 */ -#define KEYV (0x0002) /* Flash Key violation flag */ -#define ACCVIFG (0x0004) /* Flash Access violation flag */ -#define WAIT (0x0008) /* Wait flag for segment write */ -#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ -#define EMEX (0x0020) /* Flash Emergency Exit */ -#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ -//#define RESERVED (0x0080) /* Reserved */ - -/* FCTL3 Control Bits */ -#define BUSY_L (0x0001) /* Flash busy: 1 */ -#define KEYV_L (0x0002) /* Flash Key violation flag */ -#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ -#define WAIT_L (0x0008) /* Wait flag for segment write */ -#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ -#define EMEX_L (0x0020) /* Flash Emergency Exit */ -#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ -//#define RESERVED (0x0080) /* Reserved */ - -/* FCTL4 Control Bits */ -#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ -#define MGR0 (0x0010) /* Marginal read 0 mode. */ -#define MGR1 (0x0020) /* Marginal read 1 mode. */ -#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ - -/* FCTL4 Control Bits */ -#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ -#define MGR0_L (0x0010) /* Marginal read 0 mode. */ -#define MGR1_L (0x0020) /* Marginal read 1 mode. */ -#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ - -/************************************************************ -* HARDWARE MULTIPLIER 32Bit -************************************************************/ -#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_MPY32__ 0x04C0 -#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ - -sfr_w(MPY); /* Multiply Unsigned/Operand 1 */ -sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */ -sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */ -sfr_w(MPYS); /* Multiply Signed/Operand 1 */ -sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */ -sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */ -sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */ -sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */ -sfr_w(OP2); /* Operand 2 */ -sfr_b(OP2_L); /* Operand 2 */ -sfr_b(OP2_H); /* Operand 2 */ -sfr_w(RESLO); /* Result Low Word */ -sfr_b(RESLO_L); /* Result Low Word */ -sfr_b(RESLO_H); /* Result Low Word */ -sfr_w(RESHI); /* Result High Word */ -sfr_b(RESHI_L); /* Result High Word */ -sfr_b(RESHI_H); /* Result High Word */ -sfr_w(SUMEXT); /* Sum Extend */ -sfr_b(SUMEXT_L); /* Sum Extend */ -sfr_b(SUMEXT_H); /* Sum Extend */ - -sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */ -sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */ -sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */ -sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */ -sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */ -sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */ -sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */ -sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */ -sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */ -sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */ -sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */ -sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */ -sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */ -sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */ -sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */ -sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */ -sfr_w(OP2L); /* 32-bit operand 2 - low word */ -sfr_b(OP2L_L); /* 32-bit operand 2 - low word */ -sfr_b(OP2L_H); /* 32-bit operand 2 - low word */ -sfr_w(OP2H); /* 32-bit operand 2 - high word */ -sfr_b(OP2H_L); /* 32-bit operand 2 - high word */ -sfr_b(OP2H_H); /* 32-bit operand 2 - high word */ -sfr_w(RES0); /* 32x32-bit result 0 - least significant word */ -sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */ -sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */ -sfr_w(RES1); /* 32x32-bit result 1 */ -sfr_b(RES1_L); /* 32x32-bit result 1 */ -sfr_b(RES1_H); /* 32x32-bit result 1 */ -sfr_w(RES2); /* 32x32-bit result 2 */ -sfr_b(RES2_L); /* 32x32-bit result 2 */ -sfr_b(RES2_H); /* 32x32-bit result 2 */ -sfr_w(RES3); /* 32x32-bit result 3 - most significant word */ -sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */ -sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */ -sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */ -sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */ -sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */ - -#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ -#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ -#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ -#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ -#define OP2_B OP2_L /* Operand 2 (Byte Access) */ -#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ -#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ -#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ -#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ -#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ -#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ -#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ -#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ -#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ -#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ - -/* MPY32CTL0 Control Bits */ -#define MPYC (0x0001) /* Carry of the multiplier */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYFRAC (0x0004) /* Fractional mode */ -#define MPYSAT (0x0008) /* Saturation mode */ -#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ -#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ -#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ -#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ -#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ -#define MPYDLY32 (0x0200) /* Delayed write mode */ - -/* MPY32CTL0 Control Bits */ -#define MPYC_L (0x0001) /* Carry of the multiplier */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYFRAC_L (0x0004) /* Fractional mode */ -#define MPYSAT_L (0x0008) /* Saturation mode */ -#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ -#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ -#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ -#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ - -/* MPY32CTL0 Control Bits */ -//#define RESERVED (0x0002) /* Reserved */ -#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ -#define MPYDLY32_H (0x0002) /* Delayed write mode */ - -#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ -#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ -#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ -#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ -#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ -#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ -#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ -#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ - -/************************************************************ -* DIGITAL I/O Port1/2 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200 -#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ -#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200 -#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ -#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200 -#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ -#define __MSP430_HAS_P1SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P2SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PASEL__ /* Define for DriverLib */ - -sfr_w(PAIN); /* Port A Input */ -sfr_b(PAIN_L); /* Port A Input */ -sfr_b(PAIN_H); /* Port A Input */ -sfr_w(PAOUT); /* Port A Output */ -sfr_b(PAOUT_L); /* Port A Output */ -sfr_b(PAOUT_H); /* Port A Output */ -sfr_w(PADIR); /* Port A Direction */ -sfr_b(PADIR_L); /* Port A Direction */ -sfr_b(PADIR_H); /* Port A Direction */ -sfr_w(PAREN); /* Port A Resistor Enable */ -sfr_b(PAREN_L); /* Port A Resistor Enable */ -sfr_b(PAREN_H); /* Port A Resistor Enable */ -sfr_w(PADS); /* Port A Drive Strenght */ -sfr_b(PADS_L); /* Port A Drive Strenght */ -sfr_b(PADS_H); /* Port A Drive Strenght */ -sfr_w(PASEL); /* Port A Selection */ -sfr_b(PASEL_L); /* Port A Selection */ -sfr_b(PASEL_H); /* Port A Selection */ -sfr_w(PAIES); /* Port A Interrupt Edge Select */ -sfr_b(PAIES_L); /* Port A Interrupt Edge Select */ -sfr_b(PAIES_H); /* Port A Interrupt Edge Select */ -sfr_w(PAIE); /* Port A Interrupt Enable */ -sfr_b(PAIE_L); /* Port A Interrupt Enable */ -sfr_b(PAIE_H); /* Port A Interrupt Enable */ -sfr_w(PAIFG); /* Port A Interrupt Flag */ -sfr_b(PAIFG_L); /* Port A Interrupt Flag */ -sfr_b(PAIFG_H); /* Port A Interrupt Flag */ - - -sfr_w(P1IV); /* Port 1 Interrupt Vector Word */ -sfr_w(P2IV); /* Port 2 Interrupt Vector Word */ -#define P1IN (PAIN_L) /* Port 1 Input */ -#define P1OUT (PAOUT_L) /* Port 1 Output */ -#define P1DIR (PADIR_L) /* Port 1 Direction */ -#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ -#define P1DS (PADS_L) /* Port 1 Drive Strenght */ -#define P1SEL (PASEL_L) /* Port 1 Selection */ -#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ -#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ -#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ - -//Definitions for P1IV -#define P1IV_NONE (0x0000) /* No Interrupt pending */ -#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ -#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ -#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ -#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ -#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ -#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ -#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ -#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ - -#define P2IN (PAIN_H) /* Port 2 Input */ -#define P2OUT (PAOUT_H) /* Port 2 Output */ -#define P2DIR (PADIR_H) /* Port 2 Direction */ -#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ -#define P2DS (PADS_H) /* Port 2 Drive Strenght */ -#define P2SEL (PASEL_H) /* Port 2 Selection */ -#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ -#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ -#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ - -//Definitions for P2IV -#define P2IV_NONE (0x0000) /* No Interrupt pending */ -#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ -#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ -#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ -#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ -#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ -#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ -#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ -#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ - - -/************************************************************ -* DIGITAL I/O Port3/4 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220 -#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ -#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220 -#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ -#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220 -#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ -#define __MSP430_HAS_P3SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P4SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PBSEL__ /* Define for DriverLib */ - -sfr_w(PBIN); /* Port B Input */ -sfr_b(PBIN_L); /* Port B Input */ -sfr_b(PBIN_H); /* Port B Input */ -sfr_w(PBOUT); /* Port B Output */ -sfr_b(PBOUT_L); /* Port B Output */ -sfr_b(PBOUT_H); /* Port B Output */ -sfr_w(PBDIR); /* Port B Direction */ -sfr_b(PBDIR_L); /* Port B Direction */ -sfr_b(PBDIR_H); /* Port B Direction */ -sfr_w(PBREN); /* Port B Resistor Enable */ -sfr_b(PBREN_L); /* Port B Resistor Enable */ -sfr_b(PBREN_H); /* Port B Resistor Enable */ -sfr_w(PBDS); /* Port B Drive Strenght */ -sfr_b(PBDS_L); /* Port B Drive Strenght */ -sfr_b(PBDS_H); /* Port B Drive Strenght */ -sfr_w(PBSEL); /* Port B Selection */ -sfr_b(PBSEL_L); /* Port B Selection */ -sfr_b(PBSEL_H); /* Port B Selection */ - - -#define P3IN (PBIN_L) /* Port 3 Input */ -#define P3OUT (PBOUT_L) /* Port 3 Output */ -#define P3DIR (PBDIR_L) /* Port 3 Direction */ -#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ -#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ -#define P3SEL (PBSEL_L) /* Port 3 Selection */ - -#define P4IN (PBIN_H) /* Port 4 Input */ -#define P4OUT (PBOUT_H) /* Port 4 Output */ -#define P4DIR (PBDIR_H) /* Port 4 Direction */ -#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ -#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ -#define P4SEL (PBSEL_H) /* Port 4 Selection */ - - -/************************************************************ -* DIGITAL I/O Port5/6 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240 -#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ -#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240 -#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__ -#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240 -#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ -#define __MSP430_HAS_P5SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P6SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PCSEL__ /* Define for DriverLib */ - -sfr_w(PCIN); /* Port C Input */ -sfr_b(PCIN_L); /* Port C Input */ -sfr_b(PCIN_H); /* Port C Input */ -sfr_w(PCOUT); /* Port C Output */ -sfr_b(PCOUT_L); /* Port C Output */ -sfr_b(PCOUT_H); /* Port C Output */ -sfr_w(PCDIR); /* Port C Direction */ -sfr_b(PCDIR_L); /* Port C Direction */ -sfr_b(PCDIR_H); /* Port C Direction */ -sfr_w(PCREN); /* Port C Resistor Enable */ -sfr_b(PCREN_L); /* Port C Resistor Enable */ -sfr_b(PCREN_H); /* Port C Resistor Enable */ -sfr_w(PCDS); /* Port C Drive Strenght */ -sfr_b(PCDS_L); /* Port C Drive Strenght */ -sfr_b(PCDS_H); /* Port C Drive Strenght */ -sfr_w(PCSEL); /* Port C Selection */ -sfr_b(PCSEL_L); /* Port C Selection */ -sfr_b(PCSEL_H); /* Port C Selection */ - - -#define P5IN (PCIN_L) /* Port 5 Input */ -#define P5OUT (PCOUT_L) /* Port 5 Output */ -#define P5DIR (PCDIR_L) /* Port 5 Direction */ -#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ -#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ -#define P5SEL (PCSEL_L) /* Port 5 Selection */ - -#define P6IN (PCIN_H) /* Port 6 Input */ -#define P6OUT (PCOUT_H) /* Port 6 Output */ -#define P6DIR (PCDIR_H) /* Port 6 Direction */ -#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ -#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ -#define P6SEL (PCSEL_H) /* Port 6 Selection */ - - -/************************************************************ -* DIGITAL I/O Port7/8 Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260 -#define P7_BASE __MSP430_BASEADDRESS_PORT7_R__ -#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260 -#define P8_BASE __MSP430_BASEADDRESS_PORT8_R__ -#define __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260 -#define PD_BASE __MSP430_BASEADDRESS_PORTD_R__ -#define __MSP430_HAS_P7SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_P8SEL__ /* Define for DriverLib */ -#define __MSP430_HAS_PDSEL__ /* Define for DriverLib */ - -sfr_w(PDIN); /* Port D Input */ -sfr_b(PDIN_L); /* Port D Input */ -sfr_b(PDIN_H); /* Port D Input */ -sfr_w(PDOUT); /* Port D Output */ -sfr_b(PDOUT_L); /* Port D Output */ -sfr_b(PDOUT_H); /* Port D Output */ -sfr_w(PDDIR); /* Port D Direction */ -sfr_b(PDDIR_L); /* Port D Direction */ -sfr_b(PDDIR_H); /* Port D Direction */ -sfr_w(PDREN); /* Port D Resistor Enable */ -sfr_b(PDREN_L); /* Port D Resistor Enable */ -sfr_b(PDREN_H); /* Port D Resistor Enable */ -sfr_w(PDDS); /* Port D Drive Strenght */ -sfr_b(PDDS_L); /* Port D Drive Strenght */ -sfr_b(PDDS_H); /* Port D Drive Strenght */ -sfr_w(PDSEL); /* Port D Selection */ -sfr_b(PDSEL_L); /* Port D Selection */ -sfr_b(PDSEL_H); /* Port D Selection */ - - -#define P7IN (PDIN_L) /* Port 7 Input */ -#define P7OUT (PDOUT_L) /* Port 7 Output */ -#define P7DIR (PDDIR_L) /* Port 7 Direction */ -#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ -#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ -#define P7SEL (PDSEL_L) /* Port 7 Selection */ - -#define P8IN (PDIN_H) /* Port 8 Input */ -#define P8OUT (PDOUT_H) /* Port 8 Output */ -#define P8DIR (PDDIR_H) /* Port 8 Direction */ -#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ -#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ -#define P8SEL (PDSEL_H) /* Port 8 Selection */ - - -/************************************************************ -* DIGITAL I/O PortJ Pull up / Pull down Resistors -************************************************************/ -#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320 -#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ - -sfr_w(PJIN); /* Port J Input */ -sfr_b(PJIN_L); /* Port J Input */ -sfr_b(PJIN_H); /* Port J Input */ -sfr_w(PJOUT); /* Port J Output */ -sfr_b(PJOUT_L); /* Port J Output */ -sfr_b(PJOUT_H); /* Port J Output */ -sfr_w(PJDIR); /* Port J Direction */ -sfr_b(PJDIR_L); /* Port J Direction */ -sfr_b(PJDIR_H); /* Port J Direction */ -sfr_w(PJREN); /* Port J Resistor Enable */ -sfr_b(PJREN_L); /* Port J Resistor Enable */ -sfr_b(PJREN_H); /* Port J Resistor Enable */ -sfr_w(PJDS); /* Port J Drive Strenght */ -sfr_b(PJDS_L); /* Port J Drive Strenght */ -sfr_b(PJDS_H); /* Port J Drive Strenght */ - -/************************************************************ -* PORT MAPPING CONTROLLER -************************************************************/ -#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0 -#define PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ - -sfr_w(PMAPKEYID); /* Port Mapping Key register */ -sfr_b(PMAPKEYID_L); /* Port Mapping Key register */ -sfr_b(PMAPKEYID_H); /* Port Mapping Key register */ -sfr_w(PMAPCTL); /* Port Mapping control register */ -sfr_b(PMAPCTL_L); /* Port Mapping control register */ -sfr_b(PMAPCTL_H); /* Port Mapping control register */ - -#define PMAPKEY (0x2D52) /* Port Mapping Key */ -#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ -#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ - -/* PMAPCTL Control Bits */ -#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ -#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ - -/* PMAPCTL Control Bits */ -#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ -#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ - -/************************************************************ -* PORT 4 MAPPING CONTROLLER -************************************************************/ -#define __MSP430_HAS_PORT4_MAPPING__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PORT4_MAPPING__ 0x01E0 -#define P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__ - -sfr_w(P4MAP01); /* Port P4.0/1 mapping register */ -sfr_b(P4MAP01_L); /* Port P4.0/1 mapping register */ -sfr_b(P4MAP01_H); /* Port P4.0/1 mapping register */ -sfr_w(P4MAP23); /* Port P4.2/3 mapping register */ -sfr_b(P4MAP23_L); /* Port P4.2/3 mapping register */ -sfr_b(P4MAP23_H); /* Port P4.2/3 mapping register */ -sfr_w(P4MAP45); /* Port P4.4/5 mapping register */ -sfr_b(P4MAP45_L); /* Port P4.4/5 mapping register */ -sfr_b(P4MAP45_H); /* Port P4.4/5 mapping register */ -sfr_w(P4MAP67); /* Port P4.6/7 mapping register */ -sfr_b(P4MAP67_L); /* Port P4.6/7 mapping register */ -sfr_b(P4MAP67_H); /* Port P4.6/7 mapping register */ - -#define P4MAP0 P4MAP01_L /* Port P4.0 mapping register */ -#define P4MAP1 P4MAP01_H /* Port P4.1 mapping register */ -#define P4MAP2 P4MAP23_L /* Port P4.2 mapping register */ -#define P4MAP3 P4MAP23_H /* Port P4.3 mapping register */ -#define P4MAP4 P4MAP45_L /* Port P4.4 mapping register */ -#define P4MAP5 P4MAP45_H /* Port P4.5 mapping register */ -#define P4MAP6 P4MAP67_L /* Port P4.6 mapping register */ -#define P4MAP7 P4MAP67_H /* Port P4.7 mapping register */ - -#define PM_NONE 0 -#define PM_CBOUT0 1 -#define PM_TB0CLK 1 -#define PM_ADC12CLK 2 -#define PM_DMAE0 2 -#define PM_SVMOUT 3 -#define PM_TB0OUTH 3 -#define PM_TB0CCR0A 4 -#define PM_TB0CCR1A 5 -#define PM_TB0CCR2A 6 -#define PM_TB0CCR3A 7 -#define PM_TB0CCR4A 8 -#define PM_TB0CCR5A 9 -#define PM_TB0CCR6A 10 -#define PM_UCA1RXD 11 -#define PM_UCA1SOMI 11 -#define PM_UCA1TXD 12 -#define PM_UCA1SIMO 12 -#define PM_UCA1CLK 13 -#define PM_UCB1STE 13 -#define PM_UCB1SOMI 14 -#define PM_UCB1SCL 14 -#define PM_UCB1SIMO 15 -#define PM_UCB1SDA 15 -#define PM_UCB1CLK 16 -#define PM_UCA1STE 16 -#define PM_CBOUT1 17 -#define PM_MCLK 18 -#define PM_ANALOG 31 - -/************************************************************ -* PMM - Power Management System -************************************************************/ -#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_PMM__ 0x0120 -#define PMM_BASE __MSP430_BASEADDRESS_PMM__ - -sfr_w(PMMCTL0); /* PMM Control 0 */ -sfr_b(PMMCTL0_L); /* PMM Control 0 */ -sfr_b(PMMCTL0_H); /* PMM Control 0 */ -sfr_w(PMMCTL1); /* PMM Control 1 */ -sfr_b(PMMCTL1_L); /* PMM Control 1 */ -sfr_b(PMMCTL1_H); /* PMM Control 1 */ -sfr_w(SVSMHCTL); /* SVS and SVM high side control register */ -sfr_b(SVSMHCTL_L); /* SVS and SVM high side control register */ -sfr_b(SVSMHCTL_H); /* SVS and SVM high side control register */ -sfr_w(SVSMLCTL); /* SVS and SVM low side control register */ -sfr_b(SVSMLCTL_L); /* SVS and SVM low side control register */ -sfr_b(SVSMLCTL_H); /* SVS and SVM low side control register */ -sfr_w(SVSMIO); /* SVSIN and SVSOUT control register */ -sfr_b(SVSMIO_L); /* SVSIN and SVSOUT control register */ -sfr_b(SVSMIO_H); /* SVSIN and SVSOUT control register */ -sfr_w(PMMIFG); /* PMM Interrupt Flag */ -sfr_b(PMMIFG_L); /* PMM Interrupt Flag */ -sfr_b(PMMIFG_H); /* PMM Interrupt Flag */ -sfr_w(PMMRIE); /* PMM and RESET Interrupt Enable */ -sfr_b(PMMRIE_L); /* PMM and RESET Interrupt Enable */ -sfr_b(PMMRIE_H); /* PMM and RESET Interrupt Enable */ -sfr_w(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */ -sfr_b(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */ -sfr_b(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */ - -#define PMMPW (0xA500) /* PMM Register Write Password */ -#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ - -/* PMMCTL0 Control Bits */ -#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ -#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ -#define PMMSWBOR (0x0004) /* PMM Software BOR */ -#define PMMSWPOR (0x0008) /* PMM Software POR */ -#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ -#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ - -/* PMMCTL0 Control Bits */ -#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ -#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ -#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ -#define PMMSWPOR_L (0x0008) /* PMM Software POR */ -#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ -#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ - -#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ -#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ -#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ -#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ - -/* PMMCTL1 Control Bits */ -#define PMMREFMD (0x0001) /* PMM Reference Mode */ -#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ -#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ - -/* PMMCTL1 Control Bits */ -#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ -#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ -#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ - -/* SVSMHCTL Control Bits */ -#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ -#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ -#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ -#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ -#define SVSHMD (0x0010) /* SVS high side mode */ -#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ -#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ -#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ -#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ -#define SVSHE (0x0400) /* SVS high side enable */ -#define SVSHFP (0x0800) /* SVS high side full performace mode */ -#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ -#define SVMHE (0x4000) /* SVM high side enable */ -#define SVMHFP (0x8000) /* SVM high side full performace mode */ - -/* SVSMHCTL Control Bits */ -#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ -#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ -#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ -#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ -#define SVSHMD_L (0x0010) /* SVS high side mode */ -#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ -#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ - -/* SVSMHCTL Control Bits */ -#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ -#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ -#define SVSHE_H (0x0004) /* SVS high side enable */ -#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ -#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ -#define SVMHE_H (0x0040) /* SVM high side enable */ -#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ - -#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ -#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ -#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ -#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ -#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ -#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ -#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ -#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ - -#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ -#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ -#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ -#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ - -/* SVSMLCTL Control Bits */ -#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ -#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ -#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ -#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ -#define SVSLMD (0x0010) /* SVS low side mode */ -#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ -#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ -#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ -#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ -#define SVSLE (0x0400) /* SVS low side enable */ -#define SVSLFP (0x0800) /* SVS low side full performace mode */ -#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ -#define SVMLE (0x4000) /* SVM low side enable */ -#define SVMLFP (0x8000) /* SVM low side full performace mode */ - -/* SVSMLCTL Control Bits */ -#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ -#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ -#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ -#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ -#define SVSLMD_L (0x0010) /* SVS low side mode */ -#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ -#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ - -/* SVSMLCTL Control Bits */ -#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ -#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ -#define SVSLE_H (0x0004) /* SVS low side enable */ -#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ -#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ -#define SVMLE_H (0x0040) /* SVM low side enable */ -#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ - -#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ -#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ -#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ -#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ -#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ -#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ -#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ -#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ - -#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ -#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ -#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ -#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ - -/* SVSMIO Control Bits */ -#define SVMLOE (0x0008) /* SVM low side output enable */ -#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ -#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ -#define SVMHOE (0x0800) /* SVM high side output enable */ -#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ - -/* SVSMIO Control Bits */ -#define SVMLOE_L (0x0008) /* SVM low side output enable */ -#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ -#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ - -/* SVSMIO Control Bits */ -#define SVMHOE_H (0x0008) /* SVM high side output enable */ -#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ - -/* PMMIFG Control Bits */ -#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ -#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ -#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ -#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ -#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ -#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ -#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ -#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ -#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ -#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ -#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ -#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ - -/* PMMIFG Control Bits */ -#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ -#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ -#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ -#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ -#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ -#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ - -/* PMMIFG Control Bits */ -#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ -#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ -#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ -#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ -#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ -#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ - -#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ - -/* PMMIE and RESET Control Bits */ -#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ -#define SVMLIE (0x0002) /* SVM low side interrupt enable */ -#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ -#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ -#define SVMHIE (0x0020) /* SVM high side interrupt enable */ -#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ -#define SVSLPE (0x0100) /* SVS low side POR enable */ -#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ -#define SVSHPE (0x1000) /* SVS high side POR enable */ -#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ - -/* PMMIE and RESET Control Bits */ -#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ -#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ -#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ -#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ -#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ -#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ - -/* PMMIE and RESET Control Bits */ -#define SVSLPE_H (0x0001) /* SVS low side POR enable */ -#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ -#define SVSHPE_H (0x0010) /* SVS high side POR enable */ -#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ - -/* PM5CTL0 Power Mode 5 Control Bits */ -#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -/* PM5CTL0 Power Mode 5 Control Bits */ -#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ - -/************************************************************* -* RAM Control Module -*************************************************************/ -#define __MSP430_HAS_RC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_RC__ 0x0158 -#define RAM_BASE __MSP430_BASEADDRESS_RC__ - -sfr_w(RCCTL0); /* Ram Controller Control Register */ -sfr_b(RCCTL0_L); /* Ram Controller Control Register */ -sfr_b(RCCTL0_H); /* Ram Controller Control Register */ - -/* RCCTL0 Control Bits */ -#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ -#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ -#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ -#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ -#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ - -/* RCCTL0 Control Bits */ -#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ -#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ -#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ -#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ -#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ - -#define RCKEY (0x5A00) - -/************************************************************ -* Shared Reference -************************************************************/ -#define __MSP430_HAS_REF__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_REF__ 0x01B0 -#define REF_BASE __MSP430_BASEADDRESS_REF__ - -sfr_w(REFCTL0); /* REF Shared Reference control register 0 */ -sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */ -sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */ - -/* REFCTL0 Control Bits */ -#define REFON (0x0001) /* REF Reference On */ -#define REFOUT (0x0002) /* REF Reference output Buffer On */ -//#define RESERVED (0x0004) /* Reserved */ -#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ -#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ -#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFMSTR (0x0080) /* REF Master Control */ -#define REFGENACT (0x0100) /* REF Reference generator active */ -#define REFBGACT (0x0200) /* REF Reference bandgap active */ -#define REFGENBUSY (0x0400) /* REF Reference generator busy */ -#define BGMODE (0x0800) /* REF Bandgap mode */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -/* REFCTL0 Control Bits */ -#define REFON_L (0x0001) /* REF Reference On */ -#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ -//#define RESERVED (0x0004) /* Reserved */ -#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ -#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ -#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFMSTR_L (0x0080) /* REF Master Control */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -/* REFCTL0 Control Bits */ -//#define RESERVED (0x0004) /* Reserved */ -//#define RESERVED (0x0040) /* Reserved */ -#define REFGENACT_H (0x0001) /* REF Reference generator active */ -#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ -#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ -#define BGMODE_H (0x0008) /* REF Bandgap mode */ -//#define RESERVED (0x1000) /* Reserved */ -//#define RESERVED (0x2000) /* Reserved */ -//#define RESERVED (0x4000) /* Reserved */ -//#define RESERVED (0x8000) /* Reserved */ - -#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ -#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ -#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ -#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ - -/************************************************************ -* Real Time Clock -************************************************************/ -#define __MSP430_HAS_RTC__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_RTC__ 0x04A0 -#define RTC_A_BASE __MSP430_BASEADDRESS_RTC__ - -sfr_w(RTCCTL01); /* Real Timer Control 0/1 */ -sfr_b(RTCCTL01_L); /* Real Timer Control 0/1 */ -sfr_b(RTCCTL01_H); /* Real Timer Control 0/1 */ -sfr_w(RTCCTL23); /* Real Timer Control 2/3 */ -sfr_b(RTCCTL23_L); /* Real Timer Control 2/3 */ -sfr_b(RTCCTL23_H); /* Real Timer Control 2/3 */ -sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */ -sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */ -sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */ -sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */ -sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */ -sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */ -sfr_w(RTCPS); /* Real Timer Prescale Timer Control */ -sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */ -sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */ -sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */ -sfr_w(RTCTIM0); /* Real Time Clock Time 0 */ -sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */ -sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */ -sfr_w(RTCTIM1); /* Real Time Clock Time 1 */ -sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */ -sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */ -sfr_w(RTCDATE); /* Real Time Clock Date */ -sfr_b(RTCDATE_L); /* Real Time Clock Date */ -sfr_b(RTCDATE_H); /* Real Time Clock Date */ -sfr_w(RTCYEAR); /* Real Time Clock Year */ -sfr_b(RTCYEAR_L); /* Real Time Clock Year */ -sfr_b(RTCYEAR_H); /* Real Time Clock Year */ -sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */ -sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */ -sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */ -sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */ -sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */ -sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */ - -#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ -#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ -#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ -#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ -#define RTCNT12 RTCTIM0 -#define RTCNT34 RTCTIM1 -#define RTCNT1 RTCTIM0_L -#define RTCNT2 RTCTIM0_H -#define RTCNT3 RTCTIM1_L -#define RTCNT4 RTCTIM1_H -#define RTCSEC RTCTIM0_L -#define RTCMIN RTCTIM0_H -#define RTCHOUR RTCTIM1_L -#define RTCDOW RTCTIM1_H -#define RTCDAY RTCDATE_L -#define RTCMON RTCDATE_H -#define RTCYEARL RTCYEAR_L -#define RTCYEARH RTCYEAR_H -#define RT0PS RTCPS_L -#define RT1PS RTCPS_H -#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ -#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ -#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ -#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ - -/* RTCCTL01 Control Bits */ -#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ -#define RTCHOLD (0x4000) /* RTC Hold */ -#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ -#define RTCRDY (0x1000) /* RTC Ready */ -#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ -#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ -#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ -#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ -//#define Reserved (0x0080) -#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ -#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ -#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ -//#define Reserved (0x0008) -#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ -#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ -#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ - -/* RTCCTL01 Control Bits */ -//#define Reserved (0x0080) -#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ -#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ -#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ -//#define Reserved (0x0008) -#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ -#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ -#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ - -/* RTCCTL01 Control Bits */ -#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ -#define RTCHOLD_H (0x0040) /* RTC Hold */ -#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ -#define RTCRDY_H (0x0010) /* RTC Ready */ -#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ -#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ -#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ -#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ -//#define Reserved (0x0080) -//#define Reserved (0x0008) - -#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ -#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ -#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ -#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ -#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ -#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ -#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ -#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ -#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ -#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ -#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ -#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ -#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ -#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ -#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ - -/* RTCCTL23 Control Bits */ -#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ -#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ -#define RTCCALS (0x0080) /* RTC Calibration Sign */ -//#define Reserved (0x0040) -#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ -#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ -#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ -#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ -#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ -#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ - -/* RTCCTL23 Control Bits */ -#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ -//#define Reserved (0x0040) -#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ -#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ -#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ -#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ -#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ -#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ - -/* RTCCTL23 Control Bits */ -#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ -#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ -//#define Reserved (0x0040) - -#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ -#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ -#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ -#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ - -#define RTCAE (0x80) /* Real Time Clock Alarm enable */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ -#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ -#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ -#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ -#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ -#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ -#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ -#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -//#define Reserved (0x0400) -//#define Reserved (0x0200) -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ -#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ -#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ -#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ -#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ - -/* RTCPS0CTL Control Bits */ -//#define Reserved (0x8000) -#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ -#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ -#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ -#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) - -#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ -#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ -#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ -#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ -#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ -#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ -#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ -#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ - -#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ -#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ -#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ -#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ -#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ -#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ -#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ -#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ - -/* RTCPS1CTL Control Bits */ -#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ -#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ -#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ -#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ -#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ -#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ -#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ -#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ -#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ - -/* RTCPS1CTL Control Bits */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) -#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ -#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ -#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ -#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ -#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ - -/* RTCPS1CTL Control Bits */ -#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ -#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ -#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ -#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ -#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ -//#define Reserved (0x0400) -//#define Reserved (0x0200) -#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ -//#define Reserved (0x0080) -//#define Reserved (0x0040) -//#define Reserved (0x0020) - -#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ -#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ -#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ -#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ -#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ -#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ -#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ -#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ - -#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ -#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ -#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ -#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ -#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ -#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ -#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ -#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ - -#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ -#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ -#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ -#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ - -/* RTC Definitions */ -#define RTCIV_NONE (0x0000) /* No Interrupt pending */ -#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ -#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ -#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ -#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ -#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ - -/* Legacy Definitions */ -#define RTC_NONE (0x0000) /* No Interrupt pending */ -#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ -#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ -#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ -#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ -#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ - -/************************************************************ -* SFR - Special Function Register Module -************************************************************/ -#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_SFR__ 0x0100 -#define SFR_BASE __MSP430_BASEADDRESS_SFR__ - -sfr_w(SFRIE1); /* Interrupt Enable 1 */ -sfr_b(SFRIE1_L); /* Interrupt Enable 1 */ -sfr_b(SFRIE1_H); /* Interrupt Enable 1 */ - -/* SFRIE1 Control Bits */ -#define WDTIE (0x0001) /* WDT Interrupt Enable */ -#define OFIE (0x0002) /* Osc Fault Enable */ -//#define Reserved (0x0004) -#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ -#define NMIIE (0x0010) /* NMI Interrupt Enable */ -#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ -#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ -#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ - -#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ -#define OFIE_L (0x0002) /* Osc Fault Enable */ -//#define Reserved (0x0004) -#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ -#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ -#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ -#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ -#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ - -sfr_w(SFRIFG1); /* Interrupt Flag 1 */ -sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */ -sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */ -/* SFRIFG1 Control Bits */ -#define WDTIFG (0x0001) /* WDT Interrupt Flag */ -#define OFIFG (0x0002) /* Osc Fault Flag */ -//#define Reserved (0x0004) -#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ -#define NMIIFG (0x0010) /* NMI Interrupt Flag */ -//#define Reserved (0x0020) -#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ -#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ - -#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ -#define OFIFG_L (0x0002) /* Osc Fault Flag */ -//#define Reserved (0x0004) -#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ -#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ -//#define Reserved (0x0020) -#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ -#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ - -sfr_w(SFRRPCR); /* RESET Pin Control Register */ -sfr_b(SFRRPCR_L); /* RESET Pin Control Register */ -sfr_b(SFRRPCR_H); /* RESET Pin Control Register */ -/* SFRRPCR Control Bits */ -#define SYSNMI (0x0001) /* NMI select */ -#define SYSNMIIES (0x0002) /* NMI edge select */ -#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ -#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ - -#define SYSNMI_L (0x0001) /* NMI select */ -#define SYSNMIIES_L (0x0002) /* NMI edge select */ -#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ -#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ - -/************************************************************ -* SYS - System Module -************************************************************/ -#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_SYS__ 0x0180 -#define SYS_BASE __MSP430_BASEADDRESS_SYS__ - -sfr_w(SYSCTL); /* System control */ -sfr_b(SYSCTL_L); /* System control */ -sfr_b(SYSCTL_H); /* System control */ -sfr_w(SYSBSLC); /* Boot strap configuration area */ -sfr_b(SYSBSLC_L); /* Boot strap configuration area */ -sfr_b(SYSBSLC_H); /* Boot strap configuration area */ -sfr_w(SYSJMBC); /* JTAG mailbox control */ -sfr_b(SYSJMBC_L); /* JTAG mailbox control */ -sfr_b(SYSJMBC_H); /* JTAG mailbox control */ -sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */ -sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */ -sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */ -sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */ -sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */ -sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */ -sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */ -sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */ -sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */ -sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */ -sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */ -sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */ - -sfr_w(SYSBERRIV); /* Bus Error vector generator */ -sfr_b(SYSBERRIV_L); /* Bus Error vector generator */ -sfr_b(SYSBERRIV_H); /* Bus Error vector generator */ -sfr_w(SYSUNIV); /* User NMI vector generator */ -sfr_b(SYSUNIV_L); /* User NMI vector generator */ -sfr_b(SYSUNIV_H); /* User NMI vector generator */ -sfr_w(SYSSNIV); /* System NMI vector generator */ -sfr_b(SYSSNIV_L); /* System NMI vector generator */ -sfr_b(SYSSNIV_H); /* System NMI vector generator */ -sfr_w(SYSRSTIV); /* Reset vector generator */ -sfr_b(SYSRSTIV_L); /* Reset vector generator */ -sfr_b(SYSRSTIV_H); /* Reset vector generator */ - -/* SYSCTL Control Bits */ -#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ -//#define RESERVED (0x0002) /* SYS - Reserved */ -#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ -#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSCTL Control Bits */ -#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ -//#define RESERVED (0x0002) /* SYS - Reserved */ -#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ -#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSBSLC Control Bits */ -#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ -#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ -#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ -#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ - -/* SYSBSLC Control Bits */ -#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ -#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ -#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ - -/* SYSBSLC Control Bits */ -//#define RESERVED (0x0008) /* SYS - Reserved */ -//#define RESERVED (0x0010) /* SYS - Reserved */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -//#define RESERVED (0x0040) /* SYS - Reserved */ -//#define RESERVED (0x0080) /* SYS - Reserved */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ -#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ - -/* SYSJMBC Control Bits */ -#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ -#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ -#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ -#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ -#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ -#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - -/* SYSJMBC Control Bits */ -#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ -#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ -#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ -#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ -#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ -//#define RESERVED (0x0020) /* SYS - Reserved */ -#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ -#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ -//#define RESERVED (0x0100) /* SYS - Reserved */ -//#define RESERVED (0x0200) /* SYS - Reserved */ -//#define RESERVED (0x0400) /* SYS - Reserved */ -//#define RESERVED (0x0800) /* SYS - Reserved */ -//#define RESERVED (0x1000) /* SYS - Reserved */ -//#define RESERVED (0x2000) /* SYS - Reserved */ -//#define RESERVED (0x4000) /* SYS - Reserved */ -//#define RESERVED (0x8000) /* SYS - Reserved */ - - -/* SYSUNIV Definitions */ -#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ -#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ -#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */ -#define SYSUNIV_BUSIFG (0x0008) /* SYSUNIV : Bus Error */ -#define SYSUNIV_SYSBUSIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIFG (legacy) */ - -/* SYSSNIV Definitions */ -#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */ -#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */ -#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */ -#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */ -#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */ -#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */ -#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */ -#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */ -#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */ - -/* SYSRSTIV Definitions */ -#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ -#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ -#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ -#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ -#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ -#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ -#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */ -#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */ -#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */ -#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */ -#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ -#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ -#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ -#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */ -//#define RESERVED (0x001C) /* SYSRSTIV : Reserved */ -#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ -#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */ - -/************************************************************ -* Timer0_A5 -************************************************************/ -#define __MSP430_HAS_T0A5__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T0A5__ 0x0340 -#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ - -sfr_w(TA0CTL); /* Timer0_A5 Control */ -sfr_w(TA0CCTL0); /* Timer0_A5 Capture/Compare Control 0 */ -sfr_w(TA0CCTL1); /* Timer0_A5 Capture/Compare Control 1 */ -sfr_w(TA0CCTL2); /* Timer0_A5 Capture/Compare Control 2 */ -sfr_w(TA0CCTL3); /* Timer0_A5 Capture/Compare Control 3 */ -sfr_w(TA0CCTL4); /* Timer0_A5 Capture/Compare Control 4 */ -sfr_w(TA0R); /* Timer0_A5 */ -sfr_w(TA0CCR0); /* Timer0_A5 Capture/Compare 0 */ -sfr_w(TA0CCR1); /* Timer0_A5 Capture/Compare 1 */ -sfr_w(TA0CCR2); /* Timer0_A5 Capture/Compare 2 */ -sfr_w(TA0CCR3); /* Timer0_A5 Capture/Compare 3 */ -sfr_w(TA0CCR4); /* Timer0_A5 Capture/Compare 4 */ -sfr_w(TA0IV); /* Timer0_A5 Interrupt Vector Word */ -sfr_w(TA0EX0); /* Timer0_A5 Expansion Register 0 */ - -/* TAxCTL Control Bits */ -#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ -#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ -#define ID1 (0x0080) /* Timer A clock input divider 1 */ -#define ID0 (0x0040) /* Timer A clock input divider 0 */ -#define MC1 (0x0020) /* Timer A mode control 1 */ -#define MC0 (0x0010) /* Timer A mode control 0 */ -#define TACLR (0x0004) /* Timer A counter clear */ -#define TAIE (0x0002) /* Timer A counter interrupt enable */ -#define TAIFG (0x0001) /* Timer A counter interrupt flag */ - -#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ -#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ -#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ -#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ -#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ -#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ -#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ -#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ -#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ -#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ -#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ -#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ -#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ -#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ -#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ -#define MC__CONTINOUS (0x0020) /* Legacy define */ -#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ -#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ -#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ -#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ -#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ -#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ -#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ -#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ -#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ - -/* TAxCCTLx Control Bits */ -#define CM1 (0x8000) /* Capture mode 1 */ -#define CM0 (0x4000) /* Capture mode 0 */ -#define CCIS1 (0x2000) /* Capture input select 1 */ -#define CCIS0 (0x1000) /* Capture input select 0 */ -#define SCS (0x0800) /* Capture sychronize */ -#define SCCI (0x0400) /* Latched capture signal (read) */ -#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ -#define OUTMOD2 (0x0080) /* Output mode 2 */ -#define OUTMOD1 (0x0040) /* Output mode 1 */ -#define OUTMOD0 (0x0020) /* Output mode 0 */ -#define CCIE (0x0010) /* Capture/compare interrupt enable */ -#define CCI (0x0008) /* Capture input signal (read) */ -#define OUT (0x0004) /* PWM Output signal if output mode 0 */ -#define COV (0x0002) /* Capture/compare overflow flag */ -#define CCIFG (0x0001) /* Capture/compare interrupt flag */ - -#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ -#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ -#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ -#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ -#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ -#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ -#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ -#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ -#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ -#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ -#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ -#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ -#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ -#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ -#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ -#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ - -/* TAxEX0 Control Bits */ -#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ -#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ -#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ - -#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ -#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ -#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ -#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ -#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ -#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ -#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ -#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ - -/* T0A5IV Definitions */ -#define TA0IV_NONE (0x0000) /* No Interrupt pending */ -#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ -#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ -#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */ -#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */ -#define TA0IV_5 (0x000A) /* Reserved */ -#define TA0IV_6 (0x000C) /* Reserved */ -#define TA0IV_TAIFG (0x000E) /* TA0IFG */ - -/* Legacy Defines */ -#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ -#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ -#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */ -#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */ -#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ - -/************************************************************ -* Timer1_A3 -************************************************************/ -#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T1A3__ 0x0380 -#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ - -sfr_w(TA1CTL); /* Timer1_A3 Control */ -sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */ -sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */ -sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */ -sfr_w(TA1R); /* Timer1_A3 */ -sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */ -sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */ -sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */ -sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */ -sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */ - -/* Bits are already defined within the Timer0_Ax */ - -/* TA1IV Definitions */ -#define TA1IV_NONE (0x0000) /* No Interrupt pending */ -#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ -#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ -#define TA1IV_3 (0x0006) /* Reserved */ -#define TA1IV_4 (0x0008) /* Reserved */ -#define TA1IV_5 (0x000A) /* Reserved */ -#define TA1IV_6 (0x000C) /* Reserved */ -#define TA1IV_TAIFG (0x000E) /* TA1IFG */ - -/* Legacy Defines */ -#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ -#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ -#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ - -/************************************************************ -* Timer2_A3 -************************************************************/ -#define __MSP430_HAS_T2A3__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T2A3__ 0x0400 -#define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__ - -sfr_w(TA2CTL); /* Timer2_A3 Control */ -sfr_w(TA2CCTL0); /* Timer2_A3 Capture/Compare Control 0 */ -sfr_w(TA2CCTL1); /* Timer2_A3 Capture/Compare Control 1 */ -sfr_w(TA2CCTL2); /* Timer2_A3 Capture/Compare Control 2 */ -sfr_w(TA2R); /* Timer2_A3 */ -sfr_w(TA2CCR0); /* Timer2_A3 Capture/Compare 0 */ -sfr_w(TA2CCR1); /* Timer2_A3 Capture/Compare 1 */ -sfr_w(TA2CCR2); /* Timer2_A3 Capture/Compare 2 */ -sfr_w(TA2IV); /* Timer2_A3 Interrupt Vector Word */ -sfr_w(TA2EX0); /* Timer2_A3 Expansion Register 0 */ - -/* Bits are already defined within the Timer0_Ax */ - -/* TA2IV Definitions */ -#define TA2IV_NONE (0x0000) /* No Interrupt pending */ -#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */ -#define TA2IV_TACCR2 (0x0004) /* TA2CCR2_CCIFG */ -#define TA2IV_3 (0x0006) /* Reserved */ -#define TA2IV_4 (0x0008) /* Reserved */ -#define TA2IV_5 (0x000A) /* Reserved */ -#define TA2IV_6 (0x000C) /* Reserved */ -#define TA2IV_TAIFG (0x000E) /* TA2IFG */ - -/* Legacy Defines */ -#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */ -#define TA2IV_TA2CCR2 (0x0004) /* TA2CCR2_CCIFG */ -#define TA2IV_TA2IFG (0x000E) /* TA2IFG */ - -/************************************************************ -* Timer0_B7 -************************************************************/ -#define __MSP430_HAS_T0B7__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_T0B7__ 0x03C0 -#define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__ - -sfr_w(TB0CTL); /* Timer0_B7 Control */ -sfr_w(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */ -sfr_w(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */ -sfr_w(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */ -sfr_w(TB0CCTL3); /* Timer0_B7 Capture/Compare Control 3 */ -sfr_w(TB0CCTL4); /* Timer0_B7 Capture/Compare Control 4 */ -sfr_w(TB0CCTL5); /* Timer0_B7 Capture/Compare Control 5 */ -sfr_w(TB0CCTL6); /* Timer0_B7 Capture/Compare Control 6 */ -sfr_w(TB0R); /* Timer0_B7 */ -sfr_w(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */ -sfr_w(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */ -sfr_w(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */ -sfr_w(TB0CCR3); /* Timer0_B7 Capture/Compare 3 */ -sfr_w(TB0CCR4); /* Timer0_B7 Capture/Compare 4 */ -sfr_w(TB0CCR5); /* Timer0_B7 Capture/Compare 5 */ -sfr_w(TB0CCR6); /* Timer0_B7 Capture/Compare 6 */ -sfr_w(TB0EX0); /* Timer0_B7 Expansion Register 0 */ -sfr_w(TB0IV); /* Timer0_B7 Interrupt Vector Word */ - -/* Legacy Type Definitions for TimerB */ -#define TBCTL TB0CTL /* Timer0_B7 Control */ -#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */ -#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */ -#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */ -#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */ -#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */ -#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */ -#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */ -#define TBR TB0R /* Timer0_B7 */ -#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */ -#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */ -#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */ -#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */ -#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */ -#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */ -#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */ -#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */ -#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */ -#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */ -#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */ - -/* TBxCTL Control Bits */ -#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ -#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ -#define CNTL1 (0x1000) /* Counter lenght 1 */ -#define CNTL0 (0x0800) /* Counter lenght 0 */ -#define TBSSEL1 (0x0200) /* Clock source 1 */ -#define TBSSEL0 (0x0100) /* Clock source 0 */ -#define TBCLR (0x0004) /* Timer0_B7 counter clear */ -#define TBIE (0x0002) /* Timer0_B7 interrupt enable */ -#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */ - -#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ -#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ - -#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ -#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ -#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ -#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ -#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ -#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ -#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ -#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ -#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ -#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ -#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ -#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ -#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ -#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ -#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ -#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ -#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */ -#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ -#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */ -#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */ -#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */ -#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */ -#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */ -#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */ -#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */ - -/* Additional Timer B Control Register bits are defined in Timer A */ -/* TBxCCTLx Control Bits */ -#define CLLD1 (0x0400) /* Compare latch load source 1 */ -#define CLLD0 (0x0200) /* Compare latch load source 0 */ - -#define SLSHR1 (0x0400) /* Compare latch load source 1 */ -#define SLSHR0 (0x0200) /* Compare latch load source 0 */ - -#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ -#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ -#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ -#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ - -#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ -#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ -#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ -#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ - -/* TBxEX0 Control Bits */ -#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */ -#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */ -#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */ - -#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ -#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ -#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ -#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ -#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ -#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ -#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ -#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ -#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ -#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ -#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ -#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ -#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ -#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ -#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ -#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ - -/* TB0IV Definitions */ -#define TB0IV_NONE (0x0000) /* No Interrupt pending */ -#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ -#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ -#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ -#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ -#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */ -#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */ -#define TB0IV_TBIFG (0x000E) /* TB0IFG */ - -/* Legacy Defines */ -#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */ -#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */ -#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */ -#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */ -#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */ -#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */ -#define TB0IV_TB0IFG (0x000E) /* TB0IFG */ - - -/************************************************************ -* USB -************************************************************/ -#define __MSP430_HAS_USB__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USB__ 0x0900 -#define USB_BASE __MSP430_BASEADDRESS_USB__ - -/* ========================================================================= */ -/* USB Configuration Registers */ -/* ========================================================================= */ -sfr_w(USBKEYID); /* USB Controller key register */ -sfr_b(USBKEYID_L); /* USB Controller key register */ -sfr_b(USBKEYID_H); /* USB Controller key register */ -sfr_w(USBCNF); /* USB Module configuration register */ -sfr_b(USBCNF_L); /* USB Module configuration register */ -sfr_b(USBCNF_H); /* USB Module configuration register */ -sfr_w(USBPHYCTL); /* USB PHY control register */ -sfr_b(USBPHYCTL_L); /* USB PHY control register */ -sfr_b(USBPHYCTL_H); /* USB PHY control register */ -sfr_w(USBPWRCTL); /* USB Power control register */ -sfr_b(USBPWRCTL_L); /* USB Power control register */ -sfr_b(USBPWRCTL_H); /* USB Power control register */ -sfr_w(USBPLLCTL); /* USB PLL control register */ -sfr_b(USBPLLCTL_L); /* USB PLL control register */ -sfr_b(USBPLLCTL_H); /* USB PLL control register */ -sfr_w(USBPLLDIVB); /* USB PLL Clock Divider Buffer control register */ -sfr_b(USBPLLDIVB_L); /* USB PLL Clock Divider Buffer control register */ -sfr_b(USBPLLDIVB_H); /* USB PLL Clock Divider Buffer control register */ -sfr_w(USBPLLIR); /* USB PLL Interrupt control register */ -sfr_b(USBPLLIR_L); /* USB PLL Interrupt control register */ -sfr_b(USBPLLIR_H); /* USB PLL Interrupt control register */ - -#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ -#define USBKEY (0x9628) /* USB Control Register key */ - -/* USBCNF Control Bits */ -#define USB_EN (0x0001) /* USB - Module enable */ -#define PUR_EN (0x0002) /* USB - PUR pin enable */ -#define PUR_IN (0x0004) /* USB - PUR pin input value */ -#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */ -#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBCNF Control Bits */ -#define USB_EN_L (0x0001) /* USB - Module enable */ -#define PUR_EN_L (0x0002) /* USB - PUR pin enable */ -#define PUR_IN_L (0x0004) /* USB - PUR pin input value */ -#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */ -#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */ -#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */ -#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */ -#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */ -//#define RESERVED (0x0010) /* USB - */ -#define PUOPE (0x0020) /* USB - USB Port Output Enable */ -//#define RESERVED (0x0040) /* USB - */ -#define PUSEL (0x0080) /* USB - USB Port Function Select */ -#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */ -#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */ -#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */ -#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */ -//#define RESERVED (0x0010) /* USB - */ -#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */ -//#define RESERVED (0x0040) /* USB - */ -#define PUSEL_L (0x0080) /* USB - USB Port Function Select */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPHYCTL Control Bits */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0100) /* USB - */ -//#define RESERVED (0x0200) /* USB - */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */ -#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */ - -/* USBPWRCTL Control Bits */ -#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */ -#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ -#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ -#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */ -#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */ -#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */ -#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */ -//#define RESERVED (0x0080) /* USB - */ -#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */ -#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */ -#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */ -#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */ -#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPWRCTL Control Bits */ -#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */ -#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ -#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ -#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */ -#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */ -#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */ -#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPWRCTL Control Bits */ -//#define RESERVED (0x0080) /* USB - */ -#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */ -#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */ -#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */ -#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */ -#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */ -#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */ -#define UPLLEN (0x0100) /* USB - PLL enable */ -#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */ -#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLCTL Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -#define UPLLEN_H (0x0001) /* USB - PLL enable */ -#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */ -//#define RESERVED (0x0400) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */ -#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */ -#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */ -#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */ - -#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */ -#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */ -#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */ - -/* USBPLLDIVB Control Bits */ -#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ -#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ -#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ -#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ -#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ -#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */ -#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */ -#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLDIVB Control Bits */ -#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ -#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ -#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ -#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ -#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ -#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLDIVB Control Bits */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */ -#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */ -#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ -#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ -#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ -#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ -#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ -#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ -#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ -#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ -#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ -#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ -#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ -#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ -#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ -#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ -#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ -#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ -#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ -#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ -#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ -#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ -#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ -#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ -#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ -#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ -#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ -#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ -#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ -#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ -#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ -#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ -#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ -#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ -#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ -#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ -#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ -#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ -#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ -#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ -#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ -#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ -#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ -#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ -#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ - -/* USBPLLIR Control Bits */ -#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */ -#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */ -#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */ -#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */ -#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLIR Control Bits */ -#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */ -#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */ -#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* USBPLLIR Control Bits */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */ -#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */ -#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */ -//#define RESERVED (0x0800) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ -//#define RESERVED (0x2000) /* USB - */ -//#define RESERVED (0x4000) /* USB - */ -//#define RESERVED (0x8000) /* USB - */ - -/* ========================================================================= */ -/* USB Control Registers */ -/* ========================================================================= */ -sfr_b(USBIEPCNF_0); /* USB Input endpoint_0: Configuration */ -sfr_b(USBIEPCNT_0); /* USB Input endpoint_0: Byte Count */ -sfr_b(USBOEPCNF_0); /* USB Output endpoint_0: Configuration */ -sfr_b(USBOEPCNT_0); /* USB Output endpoint_0: byte count */ -sfr_b(USBIEPIE); /* USB Input endpoint interrupt enable flags */ -sfr_b(USBOEPIE); /* USB Output endpoint interrupt enable flags */ -sfr_b(USBIEPIFG); /* USB Input endpoint interrupt flags */ -sfr_b(USBOEPIFG); /* USB Output endpoint interrupt flags */ -sfr_w(USBVECINT); /* USB Vector interrupt register */ -sfr_b(USBVECINT_L); /* USB Vector interrupt register */ -sfr_b(USBVECINT_H); /* USB Vector interrupt register */ -sfr_w(USBMAINT); /* USB maintenance register */ -sfr_b(USBMAINT_L); /* USB maintenance register */ -sfr_b(USBMAINT_H); /* USB maintenance register */ -sfr_w(USBTSREG); /* USB Time Stamp register */ -sfr_b(USBTSREG_L); /* USB Time Stamp register */ -sfr_b(USBTSREG_H); /* USB Time Stamp register */ -sfr_w(USBFN); /* USB Frame number */ -sfr_b(USBFN_L); /* USB Frame number */ -sfr_b(USBFN_H); /* USB Frame number */ -sfr_b(USBCTL); /* USB control register */ -sfr_b(USBIE); /* USB interrupt enable register */ -sfr_b(USBIFG); /* USB interrupt flag register */ -sfr_b(USBFUNADR); /* USB Function address register */ - -#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ - -/* USBIEPCNF_0 Control Bits */ -/* USBOEPCNF_0 Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0001) /* USB - */ -#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */ -#define STALL (0x0008) /* USB - Stall Condition */ -//#define RESERVED (0x0010) /* USB - */ -#define TOGGLE (0x0020) /* USB - Toggle Bit */ -//#define RESERVED (0x0040) /* USB - */ -#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */ - -/* USBIEPBCNT_0 Control Bits */ -/* USBOEPBCNT_0 Control Bits */ -#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */ -#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */ -#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */ -#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -#define NAK (0x0080) /* USB - No Acknowledge Status Bit */ - -/* USBMAINT Control Bits */ -#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */ -#define UTIE (0x0002) /* USB - Timer Interrupt Enable */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */ -#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */ -#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */ -#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */ -//#define RESERVED (0x1000) /* USB - */ -#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */ -#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */ -#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */ - -/* USBMAINT Control Bits */ -#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */ -#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -//#define RESERVED (0x1000) /* USB - */ - -/* USBMAINT Control Bits */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -//#define RESERVED (0x0020) /* USB - */ -//#define RESERVED (0x0040) /* USB - */ -//#define RESERVED (0x0080) /* USB - */ -#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */ -#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */ -#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */ -#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */ -//#define RESERVED (0x1000) /* USB - */ -#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */ -#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */ -#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */ - -#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */ -#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */ -#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */ -#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */ - -#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */ -#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */ -#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */ -#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */ -#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */ -#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */ -#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */ -#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */ - -/* USBCTL Control Bits */ -#define DIR (0x0001) /* USB - Data Response Bit */ -//#define RESERVED (0x0002) /* USB - */ -//#define RESERVED (0x0004) /* USB - */ -//#define RESERVED (0x0008) /* USB - */ -#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */ -#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */ -#define FEN (0x0040) /* USB - Function Enable Bit */ -//#define RESERVED (0x0080) /* USB - */ - -/* USBIE Control Bits */ -#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */ -//#define RESERVED (0x0002) /* USB - */ -#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */ -#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */ -#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */ - -/* USBIFG Control Bits */ -#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */ -//#define RESERVED (0x0002) /* USB - */ -#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */ -//#define RESERVED (0x0008) /* USB - */ -//#define RESERVED (0x0010) /* USB - */ -#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */ -#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */ -#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */ - -//values of USBVECINT when USB-interrupt occured -#define USBVECINT_NONE 0x00 -#define USBVECINT_PWR_DROP 0x02 -#define USBVECINT_PLL_LOCK 0x04 -#define USBVECINT_PLL_SIGNAL 0x06 -#define USBVECINT_PLL_RANGE 0x08 -#define USBVECINT_PWR_VBUSOn 0x0A -#define USBVECINT_PWR_VBUSOff 0x0C -#define USBVECINT_USB_TIMESTAMP 0x10 -#define USBVECINT_INPUT_ENDPOINT0 0x12 -#define USBVECINT_OUTPUT_ENDPOINT0 0x14 -#define USBVECINT_RSTR 0x16 -#define USBVECINT_SUSR 0x18 -#define USBVECINT_RESR 0x1A -#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 -#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 -#define USBVECINT_INPUT_ENDPOINT1 0x24 -#define USBVECINT_INPUT_ENDPOINT2 0x26 -#define USBVECINT_INPUT_ENDPOINT3 0x28 -#define USBVECINT_INPUT_ENDPOINT4 0x2A -#define USBVECINT_INPUT_ENDPOINT5 0x2C -#define USBVECINT_INPUT_ENDPOINT6 0x2E -#define USBVECINT_INPUT_ENDPOINT7 0x30 -#define USBVECINT_OUTPUT_ENDPOINT1 0x32 -#define USBVECINT_OUTPUT_ENDPOINT2 0x34 -#define USBVECINT_OUTPUT_ENDPOINT3 0x36 -#define USBVECINT_OUTPUT_ENDPOINT4 0x38 -#define USBVECINT_OUTPUT_ENDPOINT5 0x3A -#define USBVECINT_OUTPUT_ENDPOINT6 0x3C -#define USBVECINT_OUTPUT_ENDPOINT7 0x3E - - -/* ========================================================================= */ -/* USB Operation Registers */ -/* ========================================================================= */ - -sfr_b(USBIEPSIZXY_7); /* Input Endpoint_7: X/Y-buffer size */ -sfr_b(USBIEPBCTY_7); /* Input Endpoint_7: Y-byte count */ -sfr_b(USBIEPBBAY_7); /* Input Endpoint_7: Y-buffer base addr. */ -//sfrb Spare (0x23FC) /* Not used */ -//sfrb Spare (0x23FB) /* Not used */ -sfr_b(USBIEPBCTX_7); /* Input Endpoint_7: X-byte count */ -sfr_b(USBIEPBBAX_7); /* Input Endpoint_7: X-buffer base addr. */ -sfr_b(USBIEPCNF_7); /* Input Endpoint_7: Configuration */ -sfr_b(USBIEPSIZXY_6); /* Input Endpoint_6: X/Y-buffer size */ -sfr_b(USBIEPBCTY_6); /* Input Endpoint_6: Y-byte count */ -sfr_b(USBIEPBBAY_6); /* Input Endpoint_6: Y-buffer base addr. */ -//sfrb Spare (0x23F4) /* Not used */ -//sfrb Spare (0x23F3) /* Not used */ -sfr_b(USBIEPBCTX_6); /* Input Endpoint_6: X-byte count */ -sfr_b(USBIEPBBAX_6); /* Input Endpoint_6: X-buffer base addr. */ -sfr_b(USBIEPCNF_6); /* Input Endpoint_6: Configuration */ -sfr_b(USBIEPSIZXY_5); /* Input Endpoint_5: X/Y-buffer size */ -sfr_b(USBIEPBCTY_5); /* Input Endpoint_5: Y-byte count */ -sfr_b(USBIEPBBAY_5); /* Input Endpoint_5: Y-buffer base addr. */ -//sfrb Spare (0x23EC) /* Not used */ -//sfrb Spare (0x23EB) /* Not used */ -sfr_b(USBIEPBCTX_5); /* Input Endpoint_5: X-byte count */ -sfr_b(USBIEPBBAX_5); /* Input Endpoint_5: X-buffer base addr. */ -sfr_b(USBIEPCNF_5); /* Input Endpoint_5: Configuration */ -sfr_b(USBIEPSIZXY_4); /* Input Endpoint_4: X/Y-buffer size */ -sfr_b(USBIEPBCTY_4); /* Input Endpoint_4: Y-byte count */ -sfr_b(USBIEPBBAY_4); /* Input Endpoint_4: Y-buffer base addr. */ -//sfrb Spare (0x23E4) /* Not used */ -//sfrb Spare (0x23E3) /* Not used */ -sfr_b(USBIEPBCTX_4); /* Input Endpoint_4: X-byte count */ -sfr_b(USBIEPBBAX_4); /* Input Endpoint_4: X-buffer base addr. */ -sfr_b(USBIEPCNF_4); /* Input Endpoint_4: Configuration */ -sfr_b(USBIEPSIZXY_3); /* Input Endpoint_3: X/Y-buffer size */ -sfr_b(USBIEPBCTY_3); /* Input Endpoint_3: Y-byte count */ -sfr_b(USBIEPBBAY_3); /* Input Endpoint_3: Y-buffer base addr. */ -//sfrb Spare (0x23DC) /* Not used */ -//sfrb Spare (0x23DB) /* Not used */ -sfr_b(USBIEPBCTX_3); /* Input Endpoint_3: X-byte count */ -sfr_b(USBIEPBBAX_3); /* Input Endpoint_3: X-buffer base addr. */ -sfr_b(USBIEPCNF_3); /* Input Endpoint_3: Configuration */ -sfr_b(USBIEPSIZXY_2); /* Input Endpoint_2: X/Y-buffer size */ -sfr_b(USBIEPBCTY_2); /* Input Endpoint_2: Y-byte count */ -sfr_b(USBIEPBBAY_2); /* Input Endpoint_2: Y-buffer base addr. */ -//sfrb Spare (0x23D4) /* Not used */ -//sfrb Spare (0x23D3) /* Not used */ -sfr_b(USBIEPBCTX_2); /* Input Endpoint_2: X-byte count */ -sfr_b(USBIEPBBAX_2); /* Input Endpoint_2: X-buffer base addr. */ -sfr_b(USBIEPCNF_2); /* Input Endpoint_2: Configuration */ -sfr_b(USBIEPSIZXY_1); /* Input Endpoint_1: X/Y-buffer size */ -sfr_b(USBIEPBCTY_1); /* Input Endpoint_1: Y-byte count */ -sfr_b(USBIEPBBAY_1); /* Input Endpoint_1: Y-buffer base addr. */ -//sfrb Spare (0x23CC) /* Not used */ -//sfrb Spare (0x23CB) /* Not used */ -sfr_b(USBIEPBCTX_1); /* Input Endpoint_1: X-byte count */ -sfr_b(USBIEPBBAX_1); /* Input Endpoint_1: X-buffer base addr. */ -sfr_b(USBIEPCNF_1); /* Input Endpoint_1: Configuration */ -//sfrb (0x23C7) /* */ -//sfrb RESERVED (0x1C00) /* */ -//sfrb (0x23C0) /* */ -sfr_b(USBOEPSIZXY_7); /* Output Endpoint_7: X/Y-buffer size */ -sfr_b(USBOEPBCTY_7); /* Output Endpoint_7: Y-byte count */ -sfr_b(USBOEPBBAY_7); /* Output Endpoint_7: Y-buffer base addr. */ -//sfrb Spare (0x23BC) /* Not used */ -//sfrb Spare (0x23BB) /* Not used */ -sfr_b(USBOEPBCTX_7); /* Output Endpoint_7: X-byte count */ -sfr_b(USBOEPBBAX_7); /* Output Endpoint_7: X-buffer base addr. */ -sfr_b(USBOEPCNF_7); /* Output Endpoint_7: Configuration */ -sfr_b(USBOEPSIZXY_6); /* Output Endpoint_6: X/Y-buffer size */ -sfr_b(USBOEPBCTY_6); /* Output Endpoint_6: Y-byte count */ -sfr_b(USBOEPBBAY_6); /* Output Endpoint_6: Y-buffer base addr. */ -//sfrb Spare (0x23B4) /* Not used */ -//sfrb Spare (0x23B3) /* Not used */ -sfr_b(USBOEPBCTX_6); /* Output Endpoint_6: X-byte count */ -sfr_b(USBOEPBBAX_6); /* Output Endpoint_6: X-buffer base addr. */ -sfr_b(USBOEPCNF_6); /* Output Endpoint_6: Configuration */ -sfr_b(USBOEPSIZXY_5); /* Output Endpoint_5: X/Y-buffer size */ -sfr_b(USBOEPBCTY_5); /* Output Endpoint_5: Y-byte count */ -sfr_b(USBOEPBBAY_5); /* Output Endpoint_5: Y-buffer base addr. */ -//sfrb Spare (0x23AC) /* Not used */ -//sfrb Spare (0x23AB) /* Not used */ -sfr_b(USBOEPBCTX_5); /* Output Endpoint_5: X-byte count */ -sfr_b(USBOEPBBAX_5); /* Output Endpoint_5: X-buffer base addr. */ -sfr_b(USBOEPCNF_5); /* Output Endpoint_5: Configuration */ -sfr_b(USBOEPSIZXY_4); /* Output Endpoint_4: X/Y-buffer size */ -sfr_b(USBOEPBCTY_4); /* Output Endpoint_4: Y-byte count */ -sfr_b(USBOEPBBAY_4); /* Output Endpoint_4: Y-buffer base addr. */ -//sfrb Spare (0x23A4) /* Not used */ -//sfrb Spare (0x23A3) /* Not used */ -sfr_b(USBOEPBCTX_4); /* Output Endpoint_4: X-byte count */ -sfr_b(USBOEPBBAX_4); /* Output Endpoint_4: X-buffer base addr. */ -sfr_b(USBOEPCNF_4); /* Output Endpoint_4: Configuration */ -sfr_b(USBOEPSIZXY_3); /* Output Endpoint_3: X/Y-buffer size */ -sfr_b(USBOEPBCTY_3); /* Output Endpoint_3: Y-byte count */ -sfr_b(USBOEPBBAY_3); /* Output Endpoint_3: Y-buffer base addr. */ -//sfrb Spare (0x239C) /* Not used */ -//sfrb Spare (0x239B) /* Not used */ -sfr_b(USBOEPBCTX_3); /* Output Endpoint_3: X-byte count */ -sfr_b(USBOEPBBAX_3); /* Output Endpoint_3: X-buffer base addr. */ -sfr_b(USBOEPCNF_3); /* Output Endpoint_3: Configuration */ -sfr_b(USBOEPSIZXY_2); /* Output Endpoint_2: X/Y-buffer size */ -sfr_b(USBOEPBCTY_2); /* Output Endpoint_2: Y-byte count */ -sfr_b(USBOEPBBAY_2); /* Output Endpoint_2: Y-buffer base addr. */ -//sfrb Spare (0x2394) /* Not used */ -//sfrb Spare (0x2393) /* Not used */ -sfr_b(USBOEPBCTX_2); /* Output Endpoint_2: X-byte count */ -sfr_b(USBOEPBBAX_2); /* Output Endpoint_2: X-buffer base addr. */ -sfr_b(USBOEPCNF_2); /* Output Endpoint_2: Configuration */ -sfr_b(USBOEPSIZXY_1); /* Output Endpoint_1: X/Y-buffer size */ -sfr_b(USBOEPBCTY_1); /* Output Endpoint_1: Y-byte count */ -sfr_b(USBOEPBBAY_1); /* Output Endpoint_1: Y-buffer base addr. */ -//sfrb Spare (0x238C) /* Not used */ -//sfrb Spare (0x238B) /* Not used */ -sfr_b(USBOEPBCTX_1); /* Output Endpoint_1: X-byte count */ -sfr_b(USBOEPBBAX_1); /* Output Endpoint_1: X-buffer base addr. */ -sfr_b(USBOEPCNF_1); /* Output Endpoint_1: Configuration */ -sfr_b(USBSUBLK); /* Setup Packet Block */ -sfr_b(USBIEP0BUF); /* Input endpoint_0 buffer */ -sfr_b(USBOEP0BUF); /* Output endpoint_0 buffer */ -sfr_b(USBTOPBUFF); /* Top of buffer space */ -// (1904 Bytes) /* Buffer space */ -sfr_b(USBSTABUFF); /* Start of buffer space */ - -/* USBIEPCNF_n Control Bits */ -/* USBOEPCNF_n Control Bits */ -//#define RESERVED (0x0001) /* USB - */ -//#define RESERVED (0x0001) /* USB - */ -#define DBUF (0x0010) /* USB - Double Buffer Enable */ -//#define RESERVED (0x0040) /* USB - */ - -/* USBIEPBCNT_n Control Bits */ -/* USBOEPBCNT_n Control Bits */ -#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */ -#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */ -#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */ -/************************************************************ -* UNIFIED CLOCK SYSTEM -************************************************************/ -#define __MSP430_HAS_UCS__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_UCS__ 0x0160 -#define UCS_BASE __MSP430_BASEADDRESS_UCS__ - -sfr_w(UCSCTL0); /* UCS Control Register 0 */ -sfr_b(UCSCTL0_L); /* UCS Control Register 0 */ -sfr_b(UCSCTL0_H); /* UCS Control Register 0 */ -sfr_w(UCSCTL1); /* UCS Control Register 1 */ -sfr_b(UCSCTL1_L); /* UCS Control Register 1 */ -sfr_b(UCSCTL1_H); /* UCS Control Register 1 */ -sfr_w(UCSCTL2); /* UCS Control Register 2 */ -sfr_b(UCSCTL2_L); /* UCS Control Register 2 */ -sfr_b(UCSCTL2_H); /* UCS Control Register 2 */ -sfr_w(UCSCTL3); /* UCS Control Register 3 */ -sfr_b(UCSCTL3_L); /* UCS Control Register 3 */ -sfr_b(UCSCTL3_H); /* UCS Control Register 3 */ -sfr_w(UCSCTL4); /* UCS Control Register 4 */ -sfr_b(UCSCTL4_L); /* UCS Control Register 4 */ -sfr_b(UCSCTL4_H); /* UCS Control Register 4 */ -sfr_w(UCSCTL5); /* UCS Control Register 5 */ -sfr_b(UCSCTL5_L); /* UCS Control Register 5 */ -sfr_b(UCSCTL5_H); /* UCS Control Register 5 */ -sfr_w(UCSCTL6); /* UCS Control Register 6 */ -sfr_b(UCSCTL6_L); /* UCS Control Register 6 */ -sfr_b(UCSCTL6_H); /* UCS Control Register 6 */ -sfr_w(UCSCTL7); /* UCS Control Register 7 */ -sfr_b(UCSCTL7_L); /* UCS Control Register 7 */ -sfr_b(UCSCTL7_H); /* UCS Control Register 7 */ -sfr_w(UCSCTL8); /* UCS Control Register 8 */ -sfr_b(UCSCTL8_L); /* UCS Control Register 8 */ -sfr_b(UCSCTL8_H); /* UCS Control Register 8 */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ -#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ -#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ -#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ -#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ -#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ -#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ -#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ -#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ -#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ -#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ -#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ -#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ -#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL0 Control Bits */ -//#define RESERVED (0x0001) /* RESERVED */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ -#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ -#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ -#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ -#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL1 Control Bits */ -#define DISMOD (0x0001) /* Disable Modulation */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ -#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ -#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL1 Control Bits */ -#define DISMOD_L (0x0001) /* Disable Modulation */ -//#define RESERVED (0x0002) /* RESERVED */ -//#define RESERVED (0x0004) /* RESERVED */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ -#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ -#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ -#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ -#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ -#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ -#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ -#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ -#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ -#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ - -/* UCSCTL2 Control Bits */ -#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ -#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ -#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ -#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ -#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ -#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ -#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ -#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ -#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ -#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ -#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ -#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL2 Control Bits */ -#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ -#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ -#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ -#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ -#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ -#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ -#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ -#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL2 Control Bits */ -#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ -#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ -#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ -#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ -#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ -#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ -#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ -#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ -#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ -#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ -#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ -#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ -#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ -#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ -#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ - -/* UCSCTL3 Control Bits */ -#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ -#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ -#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ -#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ -#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL3 Control Bits */ -#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ -#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ -#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ -#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ -#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ -#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ -#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ -#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ -#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ -#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ -#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ -#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ -#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ -#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ -#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ -#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ -#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ -#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ -#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ -#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ -#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ -#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ -#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ -#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ -#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ -#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ -#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ - -/* UCSCTL4 Control Bits */ -#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ -#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ -#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ -#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ -#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ -#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ -#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL4 Control Bits */ -#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ -#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ -#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ -#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ -#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL4 Control Bits */ -//#define RESERVED (0x0008) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ -#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ -#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define SELM_0 (0x0000) /* MCLK Source Select 0 */ -#define SELM_1 (0x0001) /* MCLK Source Select 1 */ -#define SELM_2 (0x0002) /* MCLK Source Select 2 */ -#define SELM_3 (0x0003) /* MCLK Source Select 3 */ -#define SELM_4 (0x0004) /* MCLK Source Select 4 */ -#define SELM_5 (0x0005) /* MCLK Source Select 5 */ -#define SELM_6 (0x0006) /* MCLK Source Select 6 */ -#define SELM_7 (0x0007) /* MCLK Source Select 7 */ -#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ -#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ -#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ -#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ -#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ -#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ - -#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ -#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ -#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ -#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ -#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ -#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ -#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ -#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ -#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ -#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ -#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ -#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ -#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ -#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ - -#define SELA_0 (0x0000) /* ACLK Source Select 0 */ -#define SELA_1 (0x0100) /* ACLK Source Select 1 */ -#define SELA_2 (0x0200) /* ACLK Source Select 2 */ -#define SELA_3 (0x0300) /* ACLK Source Select 3 */ -#define SELA_4 (0x0400) /* ACLK Source Select 4 */ -#define SELA_5 (0x0500) /* ACLK Source Select 5 */ -#define SELA_6 (0x0600) /* ACLK Source Select 6 */ -#define SELA_7 (0x0700) /* ACLK Source Select 7 */ -#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ -#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ -#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ -#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ -#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ -#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ - -/* UCSCTL5 Control Bits */ -#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ -#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ -#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ -#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ -#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ -#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ -#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ -#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ -#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL5 Control Bits */ -#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ -#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ -#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ -//#define RESERVED (0x0008) /* RESERVED */ -#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ -#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ -#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL5 Control Bits */ -//#define RESERVED (0x0008) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ -#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ -#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ -//#define RESERVED (0x0800) /* RESERVED */ -#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ -#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ -#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ -//#define RESERVED (0x8000) /* RESERVED */ - -#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ -#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ -#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ -#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ -#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ -#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ -#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ -#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ -#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ -#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ -#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ -#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ -#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ -#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ - -#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ -#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ -#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ -#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ -#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ -#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ -#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ -#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ -#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ -#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ -#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ -#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ -#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ -#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ - -#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ -#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ -#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ -#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ -#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ -#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ -#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ -#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ -#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ -#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ -#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ -#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ -#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ -#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ - -#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ -#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ -#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ -#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ -#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ -#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ -#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ -#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ -#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ -#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ -#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ -#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ -#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ -#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ - -/* UCSCTL6 Control Bits */ -#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ -#define SMCLKOFF (0x0002) /* SMCLK Off */ -#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ -#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ -#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ -#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ -#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ -#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ -#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ -//#define RESERVED (0x2000) /* RESERVED */ -#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ -#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ - -/* UCSCTL6 Control Bits */ -#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ -#define SMCLKOFF_L (0x0002) /* SMCLK Off */ -#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ -#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ -#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ -#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ -#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ -#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ - -/* UCSCTL6 Control Bits */ -#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ -//#define RESERVED (0x2000) /* RESERVED */ -#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ -#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ - -#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ -#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ -#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ -#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ -#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ -#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ -#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ -#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ -#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ -#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ -#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ -#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ - -/* UCSCTL7 Control Bits */ -#define DCOFFG (0x0001) /* DCO Fault Flag */ -#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ -//#define RESERVED (0x0004) /* RESERVED */ -#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL7 Control Bits */ -#define DCOFFG_L (0x0001) /* DCO Fault Flag */ -#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ -//#define RESERVED (0x0004) /* RESERVED */ -#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL8 Control Bits */ -#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ -#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ -#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ -#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/* UCSCTL8 Control Bits */ -#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ -#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ -#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ -#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ -//#define RESERVED (0x0010) /* RESERVED */ -//#define RESERVED (0x0020) /* RESERVED */ -//#define RESERVED (0x0040) /* RESERVED */ -//#define RESERVED (0x0080) /* RESERVED */ -//#define RESERVED (0x0100) /* RESERVED */ -//#define RESERVED (0x0200) /* RESERVED */ -//#define RESERVED (0x0400) /* RESERVED */ -//#define RESERVED (0x0800) /* RESERVED */ -//#define RESERVED (0x1000) /* RESERVED */ -//#define RESERVED (0x2000) /* RESERVED */ -//#define RESERVED (0x4000) /* RESERVED */ -//#define RESERVED (0x8000) /* RESERVED */ - -/************************************************************ -* USCI A0 -************************************************************/ -#define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0 -#define USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ - -sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */ -sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */ -sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */ -#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ -#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ -sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */ -sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */ -sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */ -#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ -#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ -sfr_b(UCA0MCTL); /* USCI A0 Modulation Control */ -sfr_b(UCA0STAT); /* USCI A0 Status Register */ -sfr_b(UCA0RXBUF); /* USCI A0 Receive Buffer */ -sfr_b(UCA0TXBUF); /* USCI A0 Transmit Buffer */ -sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */ -sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */ -sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */ -sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */ -#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ -#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ -sfr_w(UCA0ICTL); /* USCI A0 Interrupt Enable Register */ -sfr_b(UCA0ICTL_L); /* USCI A0 Interrupt Enable Register */ -sfr_b(UCA0ICTL_H); /* USCI A0 Interrupt Enable Register */ -#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ -#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ -sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */ - - -/************************************************************ -* USCI B0 -************************************************************/ -#define __MSP430_HAS_USCI_B0__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_B0__ 0x05E0 -#define USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ - - -sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */ -sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */ -sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */ -#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ -#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ -sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */ -sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */ -sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */ -#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ -#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ -sfr_b(UCB0STAT); /* USCI B0 Status Register */ -sfr_b(UCB0RXBUF); /* USCI B0 Receive Buffer */ -sfr_b(UCB0TXBUF); /* USCI B0 Transmit Buffer */ -sfr_w(UCB0I2COA); /* USCI B0 I2C Own Address */ -sfr_b(UCB0I2COA_L); /* USCI B0 I2C Own Address */ -sfr_b(UCB0I2COA_H); /* USCI B0 I2C Own Address */ -sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */ -sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */ -sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */ -sfr_w(UCB0ICTL); /* USCI B0 Interrupt Enable Register */ -sfr_b(UCB0ICTL_L); /* USCI B0 Interrupt Enable Register */ -sfr_b(UCB0ICTL_H); /* USCI B0 Interrupt Enable Register */ -#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */ -#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */ -sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */ - -// UCAxCTL0 UART-Mode Control Bits -#define UCPEN (0x80) /* Async. Mode: Parity enable */ -#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ -#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ -#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ -#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ -#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ -#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ -#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ - -// UCxxCTL0 SPI-Mode Control Bits -#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ -#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ -#define UCMST (0x08) /* Sync. Mode: Master Select */ - -// UCBxCTL0 I2C-Mode Control Bits -#define UCA10 (0x80) /* 10-bit Address Mode */ -#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ -#define UCMM (0x20) /* Multi-Master Environment */ -//#define res (0x10) /* reserved */ -#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ -#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ -#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ -#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ - -// UCAxCTL1 UART-Mode Control Bits -#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ -#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ -#define UCRXEIE (0x20) /* RX Error interrupt enable */ -#define UCBRKIE (0x10) /* Break interrupt enable */ -#define UCDORM (0x08) /* Dormant (Sleep) Mode */ -#define UCTXADDR (0x04) /* Send next Data as Address */ -#define UCTXBRK (0x02) /* Send next Data as Break */ -#define UCSWRST (0x01) /* USCI Software Reset */ - -// UCxxCTL1 SPI-Mode Control Bits -//#define res (0x20) /* reserved */ -//#define res (0x10) /* reserved */ -//#define res (0x08) /* reserved */ -//#define res (0x04) /* reserved */ -//#define res (0x02) /* reserved */ - -// UCBxCTL1 I2C-Mode Control Bits -//#define res (0x20) /* reserved */ -#define UCTR (0x10) /* Transmit/Receive Select/Flag */ -#define UCTXNACK (0x08) /* Transmit NACK */ -#define UCTXSTP (0x04) /* Transmit STOP */ -#define UCTXSTT (0x02) /* Transmit START */ -#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ -#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ -#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ -#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ -#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ -#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ -#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ - -/* UCAxMCTL Control Bits */ -#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ -#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ -#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ -#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ -#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ -#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ -#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ -#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ - -#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ -#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ -#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ -#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ -#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ -#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ -#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ -#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ -#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ -#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ -#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ -#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ -#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ -#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ -#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ -#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ - -#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ -#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ -#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ -#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ -#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ -#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ -#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ -#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ - -/* UCAxSTAT Control Bits */ -#define UCLISTEN (0x80) /* USCI Listen mode */ -#define UCFE (0x40) /* USCI Frame Error Flag */ -#define UCOE (0x20) /* USCI Overrun Error Flag */ -#define UCPE (0x10) /* USCI Parity Error Flag */ -#define UCBRK (0x08) /* USCI Break received */ -#define UCRXERR (0x04) /* USCI RX Error Flag */ -#define UCADDR (0x02) /* USCI Address received Flag */ -#define UCBUSY (0x01) /* USCI Busy Flag */ -#define UCIDLE (0x02) /* USCI Idle line detected Flag */ - -/* UCBxSTAT Control Bits */ -#define UCSCLLOW (0x40) /* SCL low */ -#define UCGC (0x20) /* General Call address received Flag */ -#define UCBBUSY (0x10) /* Bus Busy Flag */ - -/* UCAxIRTCTL Control Bits */ -#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ -#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ -#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ -#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ -#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ -#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ -#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ -#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ - -/* UCAxIRRCTL Control Bits */ -#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ -#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ -#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ -#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ -#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ -#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ -#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ -#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ - -/* UCAxABCTL Control Bits */ -//#define res (0x80) /* reserved */ -//#define res (0x40) /* reserved */ -#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ -#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ -#define UCSTOE (0x08) /* Sync-Field Timeout error */ -#define UCBTOE (0x04) /* Break Timeout error */ -//#define res (0x02) /* reserved */ -#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ - -/* UCBxI2COA Control Bits */ -#define UCGCEN (0x8000) /* I2C General Call enable */ -#define UCOA9 (0x0200) /* I2C Own Address 9 */ -#define UCOA8 (0x0100) /* I2C Own Address 8 */ -#define UCOA7 (0x0080) /* I2C Own Address 7 */ -#define UCOA6 (0x0040) /* I2C Own Address 6 */ -#define UCOA5 (0x0020) /* I2C Own Address 5 */ -#define UCOA4 (0x0010) /* I2C Own Address 4 */ -#define UCOA3 (0x0008) /* I2C Own Address 3 */ -#define UCOA2 (0x0004) /* I2C Own Address 2 */ -#define UCOA1 (0x0002) /* I2C Own Address 1 */ -#define UCOA0 (0x0001) /* I2C Own Address 0 */ - -/* UCBxI2COA Control Bits */ -#define UCOA7_L (0x0080) /* I2C Own Address 7 */ -#define UCOA6_L (0x0040) /* I2C Own Address 6 */ -#define UCOA5_L (0x0020) /* I2C Own Address 5 */ -#define UCOA4_L (0x0010) /* I2C Own Address 4 */ -#define UCOA3_L (0x0008) /* I2C Own Address 3 */ -#define UCOA2_L (0x0004) /* I2C Own Address 2 */ -#define UCOA1_L (0x0002) /* I2C Own Address 1 */ -#define UCOA0_L (0x0001) /* I2C Own Address 0 */ - -/* UCBxI2COA Control Bits */ -#define UCGCEN_H (0x0080) /* I2C General Call enable */ -#define UCOA9_H (0x0002) /* I2C Own Address 9 */ -#define UCOA8_H (0x0001) /* I2C Own Address 8 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA9 (0x0200) /* I2C Slave Address 9 */ -#define UCSA8 (0x0100) /* I2C Slave Address 8 */ -#define UCSA7 (0x0080) /* I2C Slave Address 7 */ -#define UCSA6 (0x0040) /* I2C Slave Address 6 */ -#define UCSA5 (0x0020) /* I2C Slave Address 5 */ -#define UCSA4 (0x0010) /* I2C Slave Address 4 */ -#define UCSA3 (0x0008) /* I2C Slave Address 3 */ -#define UCSA2 (0x0004) /* I2C Slave Address 2 */ -#define UCSA1 (0x0002) /* I2C Slave Address 1 */ -#define UCSA0 (0x0001) /* I2C Slave Address 0 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ -#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ -#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ -#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ -#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ -#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ -#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ -#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ - -/* UCBxI2CSA Control Bits */ -#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ -#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ - -/* UCAxIE Control Bits */ -#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ -#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ - -/* UCBxIE Control Bits */ -#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ -#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ -#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ -#define UCSTTIE (0x0004) /* START Condition interrupt enable */ -#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ -#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ - -/* UCAxIFG Control Bits */ -#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ -#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ - -/* UCBxIFG Control Bits */ -#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ -#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ -#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ -#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ -#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ -#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ - -/* USCI Interrupt Vector Definitions */ -#define USCI_NONE (0x0000) /* No Interrupt pending */ -#define USCI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */ -#define USCI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */ -#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */ -#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */ -#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/ -#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/ -#define USCI_I2C_UCRXIFG (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG */ -#define USCI_I2C_UCTXIFG (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG */ - -/************************************************************ -* USCI A1 -************************************************************/ -#define __MSP430_HAS_USCI_A1__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_A1__ 0x0600 -#define USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__ - -sfr_w(UCA1CTLW0); /* USCI A1 Control Word Register 0 */ -sfr_b(UCA1CTLW0_L); /* USCI A1 Control Word Register 0 */ -sfr_b(UCA1CTLW0_H); /* USCI A1 Control Word Register 0 */ -#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ -#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ -sfr_w(UCA1BRW); /* USCI A1 Baud Word Rate 0 */ -sfr_b(UCA1BRW_L); /* USCI A1 Baud Word Rate 0 */ -sfr_b(UCA1BRW_H); /* USCI A1 Baud Word Rate 0 */ -#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ -#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ -sfr_b(UCA1MCTL); /* USCI A1 Modulation Control */ -sfr_b(UCA1STAT); /* USCI A1 Status Register */ -sfr_b(UCA1RXBUF); /* USCI A1 Receive Buffer */ -sfr_b(UCA1TXBUF); /* USCI A1 Transmit Buffer */ -sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */ -sfr_w(UCA1IRCTL); /* USCI A1 IrDA Transmit Control */ -sfr_b(UCA1IRCTL_L); /* USCI A1 IrDA Transmit Control */ -sfr_b(UCA1IRCTL_H); /* USCI A1 IrDA Transmit Control */ -#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ -#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ -sfr_w(UCA1ICTL); /* USCI A1 Interrupt Enable Register */ -sfr_b(UCA1ICTL_L); /* USCI A1 Interrupt Enable Register */ -sfr_b(UCA1ICTL_H); /* USCI A1 Interrupt Enable Register */ -#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */ -#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */ -sfr_w(UCA1IV); /* USCI A1 Interrupt Vector Register */ - - -/************************************************************ -* USCI B1 -************************************************************/ -#define __MSP430_HAS_USCI_B1__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_USCI_B1__ 0x0620 -#define USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__ - - -sfr_w(UCB1CTLW0); /* USCI B1 Control Word Register 0 */ -sfr_b(UCB1CTLW0_L); /* USCI B1 Control Word Register 0 */ -sfr_b(UCB1CTLW0_H); /* USCI B1 Control Word Register 0 */ -#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */ -#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */ -sfr_w(UCB1BRW); /* USCI B1 Baud Word Rate 0 */ -sfr_b(UCB1BRW_L); /* USCI B1 Baud Word Rate 0 */ -sfr_b(UCB1BRW_H); /* USCI B1 Baud Word Rate 0 */ -#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */ -#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */ -sfr_b(UCB1STAT); /* USCI B1 Status Register */ -sfr_b(UCB1RXBUF); /* USCI B1 Receive Buffer */ -sfr_b(UCB1TXBUF); /* USCI B1 Transmit Buffer */ -sfr_w(UCB1I2COA); /* USCI B1 I2C Own Address */ -sfr_b(UCB1I2COA_L); /* USCI B1 I2C Own Address */ -sfr_b(UCB1I2COA_H); /* USCI B1 I2C Own Address */ -sfr_w(UCB1I2CSA); /* USCI B1 I2C Slave Address */ -sfr_b(UCB1I2CSA_L); /* USCI B1 I2C Slave Address */ -sfr_b(UCB1I2CSA_H); /* USCI B1 I2C Slave Address */ -sfr_w(UCB1ICTL); /* USCI B1 Interrupt Enable Register */ -sfr_b(UCB1ICTL_L); /* USCI B1 Interrupt Enable Register */ -sfr_b(UCB1ICTL_H); /* USCI B1 Interrupt Enable Register */ -#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */ -#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */ -sfr_w(UCB1IV); /* USCI B1 Interrupt Vector Register */ - -/************************************************************ -* WATCHDOG TIMER A -************************************************************/ -#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ -#define __MSP430_BASEADDRESS_WDT_A__ 0x0150 -#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ - -sfr_w(WDTCTL); /* Watchdog Timer Control */ -sfr_b(WDTCTL_L); /* Watchdog Timer Control */ -sfr_b(WDTCTL_H); /* Watchdog Timer Control */ -/* The bit names have been prefixed with "WDT" */ -/* WDTCTL Control Bits */ -#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ -#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ -#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ -#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ -#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ -#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ -#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ -#define WDTHOLD (0x0080) /* WDT - Timer hold */ - -/* WDTCTL Control Bits */ -#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ -#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ -#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ -#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ -#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ -#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ -#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ -#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ - -#define WDTPW (0x5A00) - -#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ -#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ -#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ -#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ -#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ -#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ -#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ -#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ -#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ -#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ -#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ -#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ -#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ -#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ -#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ -#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ - -#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ -#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ -#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ -#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ -#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ -#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ -#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ - -/* WDT-interval times [1ms] coded with Bits 0-2 */ -/* WDT is clocked by fSMCLK (assumed 1MHz) */ -#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ -#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ -#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ -#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ -/* WDT is clocked by fACLK (assumed 32KHz) */ -#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ -#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ -#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ -#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ -/* Watchdog mode -> reset after expired time */ -/* WDT is clocked by fSMCLK (assumed 1MHz) */ -#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ -#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ -#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ -#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ -/* WDT is clocked by fACLK (assumed 32KHz) */ -#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ -#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ -#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ -#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ - - -/************************************************************ -* TLV Descriptors -************************************************************/ -#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ -#define TLV_BASE __MSP430_BASEADDRESS_TLV__ - -#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ -#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ -#define TLV_START (0x1A08) /* Start Address of the TLV structure */ -#define TLV_END (0x1AFF) /* End Address of the TLV structure */ - -#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ -#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ -#define TLV_Reserved3 (0x03) /* Future usage */ -#define TLV_Reserved4 (0x04) /* Future usage */ -#define TLV_BLANK (0x05) /* Blank descriptor */ -#define TLV_Reserved6 (0x06) /* Future usage */ -#define TLV_Reserved7 (0x07) /* Serial Number */ -#define TLV_DIERECORD (0x08) /* Die Record */ -#define TLV_ADCCAL (0x11) /* ADC12 calibration */ -#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ -#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ -#define TLV_REFCAL (0x12) /* REF calibration */ -#define TLV_TAGEXT (0xFE) /* Tag extender */ -#define TLV_TAGEND (0xFF) // Tag End of Table - -/************************************************************ -* Interrupt Vectors (offset from 0xFF80) -************************************************************/ - - -#define RTC_VECTOR (42) /* 0xFFD2 RTC */ -#define PORT2_VECTOR (43) /* 0xFFD4 Port 2 */ -#define TIMER2_A1_VECTOR (44) /* 0xFFD6 Timer2_A5 CC1-4, TA */ -#define TIMER2_A0_VECTOR (45) /* 0xFFD8 Timer2_A5 CC0 */ -#define USCI_B1_VECTOR (46) /* 0xFFDA USCI B1 Receive/Transmit */ -#define USCI_A1_VECTOR (47) /* 0xFFDC USCI A1 Receive/Transmit */ -#define PORT1_VECTOR (48) /* 0xFFDE Port 1 */ -#define TIMER1_A1_VECTOR (49) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ -#define TIMER1_A0_VECTOR (50) /* 0xFFE2 Timer1_A3 CC0 */ -#define DMA_VECTOR (51) /* 0xFFE4 DMA */ -#define USB_UBM_VECTOR (52) /* 0xFFE6 USB Timer / cable event / USB reset */ -#define TIMER0_A1_VECTOR (53) /* 0xFFE8 Timer0_A5 CC1-4, TA */ -#define TIMER0_A0_VECTOR (54) /* 0xFFEA Timer0_A5 CC0 */ -#define ADC12_VECTOR (55) /* 0xFFEC ADC */ -#define USCI_B0_VECTOR (56) /* 0xFFEE USCI B0 Receive/Transmit */ -#define USCI_A0_VECTOR (57) /* 0xFFF0 USCI A0 Receive/Transmit */ -#define WDT_VECTOR (58) /* 0xFFF2 Watchdog Timer */ -#define TIMER0_B1_VECTOR (59) /* 0xFFF4 Timer0_B7 CC1-6, TB */ -#define TIMER0_B0_VECTOR (60) /* 0xFFF6 Timer0_B7 CC0 */ -#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */ -#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */ -#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */ -#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ - -/************************************************************ -* End of Modules -************************************************************/ - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif /* #ifndef __MSP430F5529 */ - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529.ld deleted file mode 100644 index 6fe18de01..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529.ld +++ /dev/null @@ -1,457 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/* This file supports MSP430F5529 devices. */ -/* Version: 1.207 */ -/* Default linker script, for normal executables */ - -OUTPUT_ARCH(msp430) -ENTRY(_start) - -MEMORY { - SFR : ORIGIN = 0x0000, LENGTH = 0x0010 /* END=0x0010, size 16 */ - BSL : ORIGIN = 0x1000, LENGTH = 0x0800 - RAM : ORIGIN = 0x2400, LENGTH = 0x2000 /* END=0x43FF, size 8192 */ - USBRAM : ORIGIN = 0x1C00, LENGTH = 0x0800 - INFOMEM : ORIGIN = 0x1800, LENGTH = 0x0200 /* END=0x19FF, size 512 as 4 128-byte segments */ - INFOA : ORIGIN = 0x1980, LENGTH = 0x0080 /* END=0x19FF, size 128 */ - INFOB : ORIGIN = 0x1900, LENGTH = 0x0080 /* END=0x197F, size 128 */ - INFOC : ORIGIN = 0x1880, LENGTH = 0x0080 /* END=0x18FF, size 128 */ - INFOD : ORIGIN = 0x1800, LENGTH = 0x0080 /* END=0x187F, size 128 */ - ROM (rx) : ORIGIN = 0x4400, LENGTH = 0xBB80 /* END=0xFF7F, size 48000 */ - HIROM (rx) : ORIGIN = 0x00010000, LENGTH = 0x000143FF - VECT1 : ORIGIN = 0xFF80, LENGTH = 0x0002 - VECT2 : ORIGIN = 0xFF82, LENGTH = 0x0002 - VECT3 : ORIGIN = 0xFF84, LENGTH = 0x0002 - VECT4 : ORIGIN = 0xFF86, LENGTH = 0x0002 - VECT5 : ORIGIN = 0xFF88, LENGTH = 0x0002 - VECT6 : ORIGIN = 0xFF8A, LENGTH = 0x0002 - VECT7 : ORIGIN = 0xFF8C, LENGTH = 0x0002 - VECT8 : ORIGIN = 0xFF8E, LENGTH = 0x0002 - VECT9 : ORIGIN = 0xFF90, LENGTH = 0x0002 - VECT10 : ORIGIN = 0xFF92, LENGTH = 0x0002 - VECT11 : ORIGIN = 0xFF94, LENGTH = 0x0002 - VECT12 : ORIGIN = 0xFF96, LENGTH = 0x0002 - VECT13 : ORIGIN = 0xFF98, LENGTH = 0x0002 - VECT14 : ORIGIN = 0xFF9A, LENGTH = 0x0002 - VECT15 : ORIGIN = 0xFF9C, LENGTH = 0x0002 - VECT16 : ORIGIN = 0xFF9E, LENGTH = 0x0002 - VECT17 : ORIGIN = 0xFFA0, LENGTH = 0x0002 - VECT18 : ORIGIN = 0xFFA2, LENGTH = 0x0002 - VECT19 : ORIGIN = 0xFFA4, LENGTH = 0x0002 - VECT20 : ORIGIN = 0xFFA6, LENGTH = 0x0002 - VECT21 : ORIGIN = 0xFFA8, LENGTH = 0x0002 - VECT22 : ORIGIN = 0xFFAA, LENGTH = 0x0002 - VECT23 : ORIGIN = 0xFFAC, LENGTH = 0x0002 - VECT24 : ORIGIN = 0xFFAE, LENGTH = 0x0002 - VECT25 : ORIGIN = 0xFFB0, LENGTH = 0x0002 - VECT26 : ORIGIN = 0xFFB2, LENGTH = 0x0002 - VECT27 : ORIGIN = 0xFFB4, LENGTH = 0x0002 - VECT28 : ORIGIN = 0xFFB6, LENGTH = 0x0002 - VECT29 : ORIGIN = 0xFFB8, LENGTH = 0x0002 - VECT30 : ORIGIN = 0xFFBA, LENGTH = 0x0002 - VECT31 : ORIGIN = 0xFFBC, LENGTH = 0x0002 - VECT32 : ORIGIN = 0xFFBE, LENGTH = 0x0002 - VECT33 : ORIGIN = 0xFFC0, LENGTH = 0x0002 - VECT34 : ORIGIN = 0xFFC2, LENGTH = 0x0002 - VECT35 : ORIGIN = 0xFFC4, LENGTH = 0x0002 - VECT36 : ORIGIN = 0xFFC6, LENGTH = 0x0002 - VECT37 : ORIGIN = 0xFFC8, LENGTH = 0x0002 - VECT38 : ORIGIN = 0xFFCA, LENGTH = 0x0002 - VECT39 : ORIGIN = 0xFFCC, LENGTH = 0x0002 - VECT40 : ORIGIN = 0xFFCE, LENGTH = 0x0002 - VECT41 : ORIGIN = 0xFFD0, LENGTH = 0x0002 - VECT42 : ORIGIN = 0xFFD2, LENGTH = 0x0002 - VECT43 : ORIGIN = 0xFFD4, LENGTH = 0x0002 - VECT44 : ORIGIN = 0xFFD6, LENGTH = 0x0002 - VECT45 : ORIGIN = 0xFFD8, LENGTH = 0x0002 - VECT46 : ORIGIN = 0xFFDA, LENGTH = 0x0002 - VECT47 : ORIGIN = 0xFFDC, LENGTH = 0x0002 - VECT48 : ORIGIN = 0xFFDE, LENGTH = 0x0002 - VECT49 : ORIGIN = 0xFFE0, LENGTH = 0x0002 - VECT50 : ORIGIN = 0xFFE2, LENGTH = 0x0002 - VECT51 : ORIGIN = 0xFFE4, LENGTH = 0x0002 - VECT52 : ORIGIN = 0xFFE6, LENGTH = 0x0002 - VECT53 : ORIGIN = 0xFFE8, LENGTH = 0x0002 - VECT54 : ORIGIN = 0xFFEA, LENGTH = 0x0002 - VECT55 : ORIGIN = 0xFFEC, LENGTH = 0x0002 - VECT56 : ORIGIN = 0xFFEE, LENGTH = 0x0002 - VECT57 : ORIGIN = 0xFFF0, LENGTH = 0x0002 - VECT58 : ORIGIN = 0xFFF2, LENGTH = 0x0002 - VECT59 : ORIGIN = 0xFFF4, LENGTH = 0x0002 - VECT60 : ORIGIN = 0xFFF6, LENGTH = 0x0002 - VECT61 : ORIGIN = 0xFFF8, LENGTH = 0x0002 - VECT62 : ORIGIN = 0xFFFA, LENGTH = 0x0002 - VECT63 : ORIGIN = 0xFFFC, LENGTH = 0x0002 - RESETVEC : ORIGIN = 0xFFFE, LENGTH = 0x0002 -} - -SECTIONS -{ - __interrupt_vector_1 : { KEEP (*(__interrupt_vector_1 )) } > VECT1 - __interrupt_vector_2 : { KEEP (*(__interrupt_vector_2 )) } > VECT2 - __interrupt_vector_3 : { KEEP (*(__interrupt_vector_3 )) } > VECT3 - __interrupt_vector_4 : { KEEP (*(__interrupt_vector_4 )) } > VECT4 - __interrupt_vector_5 : { KEEP (*(__interrupt_vector_5 )) } > VECT5 - __interrupt_vector_6 : { KEEP (*(__interrupt_vector_6 )) } > VECT6 - __interrupt_vector_7 : { KEEP (*(__interrupt_vector_7 )) } > VECT7 - __interrupt_vector_8 : { KEEP (*(__interrupt_vector_8 )) } > VECT8 - __interrupt_vector_9 : { KEEP (*(__interrupt_vector_9 )) } > VECT9 - __interrupt_vector_10 : { KEEP (*(__interrupt_vector_10)) } > VECT10 - __interrupt_vector_11 : { KEEP (*(__interrupt_vector_11)) } > VECT11 - __interrupt_vector_12 : { KEEP (*(__interrupt_vector_12)) } > VECT12 - __interrupt_vector_13 : { KEEP (*(__interrupt_vector_13)) } > VECT13 - __interrupt_vector_14 : { KEEP (*(__interrupt_vector_14)) } > VECT14 - __interrupt_vector_15 : { KEEP (*(__interrupt_vector_15)) } > VECT15 - __interrupt_vector_16 : { KEEP (*(__interrupt_vector_16)) } > VECT16 - __interrupt_vector_17 : { KEEP (*(__interrupt_vector_17)) } > VECT17 - __interrupt_vector_18 : { KEEP (*(__interrupt_vector_18)) } > VECT18 - __interrupt_vector_19 : { KEEP (*(__interrupt_vector_19)) } > VECT19 - __interrupt_vector_20 : { KEEP (*(__interrupt_vector_20)) } > VECT20 - __interrupt_vector_21 : { KEEP (*(__interrupt_vector_21)) } > VECT21 - __interrupt_vector_22 : { KEEP (*(__interrupt_vector_22)) } > VECT22 - __interrupt_vector_23 : { KEEP (*(__interrupt_vector_23)) } > VECT23 - __interrupt_vector_24 : { KEEP (*(__interrupt_vector_24)) } > VECT24 - __interrupt_vector_25 : { KEEP (*(__interrupt_vector_25)) } > VECT25 - __interrupt_vector_26 : { KEEP (*(__interrupt_vector_26)) } > VECT26 - __interrupt_vector_27 : { KEEP (*(__interrupt_vector_27)) } > VECT27 - __interrupt_vector_28 : { KEEP (*(__interrupt_vector_28)) } > VECT28 - __interrupt_vector_29 : { KEEP (*(__interrupt_vector_29)) } > VECT29 - __interrupt_vector_30 : { KEEP (*(__interrupt_vector_30)) } > VECT30 - __interrupt_vector_31 : { KEEP (*(__interrupt_vector_31)) } > VECT31 - __interrupt_vector_32 : { KEEP (*(__interrupt_vector_32)) } > VECT32 - __interrupt_vector_33 : { KEEP (*(__interrupt_vector_33)) } > VECT33 - __interrupt_vector_34 : { KEEP (*(__interrupt_vector_34)) } > VECT34 - __interrupt_vector_35 : { KEEP (*(__interrupt_vector_35)) } > VECT35 - __interrupt_vector_36 : { KEEP (*(__interrupt_vector_36)) } > VECT36 - __interrupt_vector_37 : { KEEP (*(__interrupt_vector_37)) } > VECT37 - __interrupt_vector_38 : { KEEP (*(__interrupt_vector_38)) } > VECT38 - __interrupt_vector_39 : { KEEP (*(__interrupt_vector_39)) } > VECT39 - __interrupt_vector_40 : { KEEP (*(__interrupt_vector_40)) } > VECT40 - __interrupt_vector_41 : { KEEP (*(__interrupt_vector_41)) } > VECT41 - __interrupt_vector_42 : { KEEP (*(__interrupt_vector_42)) KEEP (*(__interrupt_vector_rtc)) } > VECT42 - __interrupt_vector_43 : { KEEP (*(__interrupt_vector_43)) KEEP (*(__interrupt_vector_port2)) } > VECT43 - __interrupt_vector_44 : { KEEP (*(__interrupt_vector_44)) KEEP (*(__interrupt_vector_timer2_a1)) } > VECT44 - __interrupt_vector_45 : { KEEP (*(__interrupt_vector_45)) KEEP (*(__interrupt_vector_timer2_a0)) } > VECT45 - __interrupt_vector_46 : { KEEP (*(__interrupt_vector_46)) KEEP (*(__interrupt_vector_usci_b1)) } > VECT46 - __interrupt_vector_47 : { KEEP (*(__interrupt_vector_47)) KEEP (*(__interrupt_vector_usci_a1)) } > VECT47 - __interrupt_vector_48 : { KEEP (*(__interrupt_vector_48)) KEEP (*(__interrupt_vector_port1)) } > VECT48 - __interrupt_vector_49 : { KEEP (*(__interrupt_vector_49)) KEEP (*(__interrupt_vector_timer1_a1)) } > VECT49 - __interrupt_vector_50 : { KEEP (*(__interrupt_vector_50)) KEEP (*(__interrupt_vector_timer1_a0)) } > VECT50 - __interrupt_vector_51 : { KEEP (*(__interrupt_vector_51)) KEEP (*(__interrupt_vector_dma)) } > VECT51 - __interrupt_vector_52 : { KEEP (*(__interrupt_vector_52)) KEEP (*(__interrupt_vector_usb_ubm)) } > VECT52 - __interrupt_vector_53 : { KEEP (*(__interrupt_vector_53)) KEEP (*(__interrupt_vector_timer0_a1)) } > VECT53 - __interrupt_vector_54 : { KEEP (*(__interrupt_vector_54)) KEEP (*(__interrupt_vector_timer0_a0)) } > VECT54 - __interrupt_vector_55 : { KEEP (*(__interrupt_vector_55)) KEEP (*(__interrupt_vector_adc12)) } > VECT55 - __interrupt_vector_56 : { KEEP (*(__interrupt_vector_56)) KEEP (*(__interrupt_vector_usci_b0)) } > VECT56 - __interrupt_vector_57 : { KEEP (*(__interrupt_vector_57)) KEEP (*(__interrupt_vector_usci_a0)) } > VECT57 - __interrupt_vector_58 : { KEEP (*(__interrupt_vector_58)) KEEP (*(__interrupt_vector_wdt)) } > VECT58 - __interrupt_vector_59 : { KEEP (*(__interrupt_vector_59)) KEEP (*(__interrupt_vector_timer0_b1)) } > VECT59 - __interrupt_vector_60 : { KEEP (*(__interrupt_vector_60)) KEEP (*(__interrupt_vector_timer0_b0)) } > VECT60 - __interrupt_vector_61 : { KEEP (*(__interrupt_vector_61)) KEEP (*(__interrupt_vector_comp_b)) } > VECT61 - __interrupt_vector_62 : { KEEP (*(__interrupt_vector_62)) KEEP (*(__interrupt_vector_unmi)) } > VECT62 - __interrupt_vector_63 : { KEEP (*(__interrupt_vector_63)) KEEP (*(__interrupt_vector_sysnmi)) } > VECT63 - __reset_vector : - { - KEEP (*(__interrupt_vector_64)) - KEEP (*(__interrupt_vector_reset)) - KEEP (*(.resetvec)) - } > RESETVEC - - .lower.rodata : - { - . = ALIGN(2); - *(.lower.rodata.* .lower.rodata) - } > ROM - - .rodata : - { - . = ALIGN(2); - *(.plt) - . = ALIGN(2); - *(.rodata .rodata.* .gnu.linkonce.r.* .const .const:*) - *(.rodata1) - KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) - PROVIDE (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - PROVIDE (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE (__init_array_end = .); - PROVIDE (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE (__fini_array_end = .); - } > ROM - - /* Note: This is a separate .rodata section for sections which are - read only but which older linkers treat as read-write. - This prevents older linkers from marking the entire .rodata - section as read-write. */ - .rodata2 : - { - . = ALIGN(2); - *(.eh_frame_hdr) - KEEP (*(.eh_frame)) - - /* gcc uses crtbegin.o to find the start of the constructors, so - we make sure it is first. Because this is a wildcard, it - doesn't matter if the user does not actually link against - crtbegin.o; the linker won't look for a file to match a - wildcard. The wildcard also means that it doesn't matter which - directory crtbegin.o is in. */ - KEEP (*crtbegin*.o(.ctors)) - - /* We don't want to include the .ctor section from from the - crtend.o file until after the sorted ctors. The .ctor section - from the crtend file contains the end of ctors marker and it - must be last */ - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - - KEEP (*crtbegin*.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } > ROM - - .upper.rodata : - { - *(.upper.rodata.* .upper.rodata) - } > HIROM - - .data : - { - . = ALIGN(2); - PROVIDE (__datastart = .); - *(.lower.data.* .lower.data) - - . = ALIGN(2); - *(.either.data.* .either.data) - - . = ALIGN(2); - KEEP (*(.jcr)) - *(.data.rel.ro.local) *(.data.rel.ro*) - *(.dynamic) - - . = ALIGN(2); - *(.data .data.* .gnu.linkonce.d.*) - KEEP (*(.gnu.linkonce.d.*personality*)) - SORT(CONSTRUCTORS) - *(.data1) - *(.got.plt) *(.got) - - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - . = ALIGN(2); - *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) - - . = ALIGN(2); - _edata = .; - PROVIDE (edata = .); - PROVIDE (__dataend = .); - } > RAM AT> ROM - - /* Note that crt0 assumes this is a multiple of two; all the - start/stop symbols are also assumed word-aligned. */ - PROVIDE(__romdatastart = LOADADDR(.data)); - PROVIDE (__romdatacopysize = SIZEOF(.data)); - - .bss : - { - . = ALIGN(2); - PROVIDE (__bssstart = .); - *(.lower.bss.* .lower.bss) - . = ALIGN(2); - *(.either.bss.* .either.bss) - *(.dynbss) - *(.sbss .sbss.*) - *(.bss .bss.* .gnu.linkonce.b.*) - . = ALIGN(2); - *(COMMON) - PROVIDE (__bssend = .); - } > RAM - PROVIDE (__bsssize = SIZEOF(.bss)); - - /* This section contains data that is not initialised during load - or application reset. */ - .noinit (NOLOAD) : - { - . = ALIGN(2); - PROVIDE (__noinit_start = .); - *(.noinit) - . = ALIGN(2); - PROVIDE (__noinit_end = .); - } > RAM - - /* We create this section so that "end" will always be in the - RAM region (matching .stack below), even if the .bss - section is empty. */ - .heap (NOLOAD) : - { - . = ALIGN(2); - __heap_start__ = .; - _end = __heap_start__; - PROVIDE (end = .); - KEEP (*(.heap)) - _end = .; - PROVIDE (end = .); - /* This word is here so that the section is not empty, and thus - not discarded by the linker. The actual value does not matter - and is ignored. */ - LONG(0); - __heap_end__ = .; - __HeapLimit = __heap_end__; - } > RAM - /* WARNING: Do not place anything in RAM here. - The heap section must be the last section in RAM and the stack - section must be placed at the very end of the RAM region. */ - - .stack (ORIGIN (RAM) + LENGTH(RAM)) : - { - PROVIDE (__stack = .); - *(.stack) - } - - /* This is just for crt0.S and interrupt handlers. */ - .lowtext : - { - PROVIDE (_start = .); - . = ALIGN(2); - KEEP (*(SORT(.crt_*))) - KEEP (*(.lowtext)) - } > ROM - - .lower.text : - { - . = ALIGN(2); - *(.lower.text.* .lower.text) - } > ROM - - .text : - { - . = ALIGN(2); - *(.text .stub .text.* .gnu.linkonce.t.* .text:*) - - KEEP (*(.text.*personality*)) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.interp .hash .dynsym .dynstr .gnu.version*) - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - . = ALIGN(2); - KEEP (*(.init)) - KEEP (*(.fini)) - KEEP (*(.tm_clone_table)) - } > ROM - - .upper.text : - { - . = ALIGN(2); - *(.upper.text.* .upper.text) - } > HIROM - - .infoA : {} > INFOA /* MSP430 INFO FLASH MEMORY SEGMENTS */ - .infoB : {} > INFOB - .infoC : {} > INFOC - .infoD : {} > INFOD - - /* Make sure that upper data sections are not used. */ - .upper : - { - *(.upper.bss.* .upper.bss) - *(.upper.data.* .upper.data) - ASSERT (SIZEOF(.upper) == 0, "This MCU does not support placing read/write data into high memory"); - } > HIROM - - /* The rest are all not normally part of the runtime image. */ - - .MSP430.attributes 0 : - { - KEEP (*(.MSP430.attributes)) - KEEP (*(.gnu.attributes)) - KEEP (*(__TI_build_attributes)) - } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1. */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions. */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2. */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2. */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions. */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - - /DISCARD/ : { *(.note.GNU-stack) } -} - - -/****************************************************************************/ -/* Include peripherals memory map */ -/****************************************************************************/ - -INCLUDE msp430f5529_symbols.ld - diff --git a/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld b/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld deleted file mode 100644 index 91448ad4f..000000000 --- a/hw/bsp/msp_exp430f5529lp/msp430f5529_symbols.ld +++ /dev/null @@ -1,867 +0,0 @@ -/* ============================================================================ */ -/* Copyright (c) 2019, Texas Instruments Incorporated */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of Texas Instruments Incorporated nor the names of */ -/* its contributors may be used to endorse or promote products derived */ -/* from this software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ -/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ -/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ -/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ -/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ -/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ -/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ============================================================================ */ - -/* This file supports MSP430F5529 devices. */ -/* Version: 1.207 */ - -/************************************************************ -* STANDARD BITS -************************************************************/ -/************************************************************ -* STATUS REGISTER BITS -************************************************************/ -/************************************************************ -* PERIPHERAL FILE MAP -************************************************************/ -/************************************************************ -* ADC12 PLUS -************************************************************/ -PROVIDE(ADC12CTL0 = 0x0700); -PROVIDE(ADC12CTL0_L = 0x0700); -PROVIDE(ADC12CTL0_H = 0x0701); -PROVIDE(ADC12CTL1 = 0x0702); -PROVIDE(ADC12CTL1_L = 0x0702); -PROVIDE(ADC12CTL1_H = 0x0703); -PROVIDE(ADC12CTL2 = 0x0704); -PROVIDE(ADC12CTL2_L = 0x0704); -PROVIDE(ADC12CTL2_H = 0x0705); -PROVIDE(ADC12IFG = 0x070A); -PROVIDE(ADC12IFG_L = 0x070A); -PROVIDE(ADC12IFG_H = 0x070B); -PROVIDE(ADC12IE = 0x070C); -PROVIDE(ADC12IE_L = 0x070C); -PROVIDE(ADC12IE_H = 0x070D); -PROVIDE(ADC12IV = 0x070E); -PROVIDE(ADC12IV_L = 0x070E); -PROVIDE(ADC12IV_H = 0x070F); -PROVIDE(ADC12MEM0 = 0x0720); -PROVIDE(ADC12MEM0_L = 0x0720); -PROVIDE(ADC12MEM0_H = 0x0721); -PROVIDE(ADC12MEM1 = 0x0722); -PROVIDE(ADC12MEM1_L = 0x0722); -PROVIDE(ADC12MEM1_H = 0x0723); -PROVIDE(ADC12MEM2 = 0x0724); -PROVIDE(ADC12MEM2_L = 0x0724); -PROVIDE(ADC12MEM2_H = 0x0725); -PROVIDE(ADC12MEM3 = 0x0726); -PROVIDE(ADC12MEM3_L = 0x0726); -PROVIDE(ADC12MEM3_H = 0x0727); -PROVIDE(ADC12MEM4 = 0x0728); -PROVIDE(ADC12MEM4_L = 0x0728); -PROVIDE(ADC12MEM4_H = 0x0729); -PROVIDE(ADC12MEM5 = 0x072A); -PROVIDE(ADC12MEM5_L = 0x072A); -PROVIDE(ADC12MEM5_H = 0x072B); -PROVIDE(ADC12MEM6 = 0x072C); -PROVIDE(ADC12MEM6_L = 0x072C); -PROVIDE(ADC12MEM6_H = 0x072D); -PROVIDE(ADC12MEM7 = 0x072E); -PROVIDE(ADC12MEM7_L = 0x072E); -PROVIDE(ADC12MEM7_H = 0x072F); -PROVIDE(ADC12MEM8 = 0x0730); -PROVIDE(ADC12MEM8_L = 0x0730); -PROVIDE(ADC12MEM8_H = 0x0731); -PROVIDE(ADC12MEM9 = 0x0732); -PROVIDE(ADC12MEM9_L = 0x0732); -PROVIDE(ADC12MEM9_H = 0x0733); -PROVIDE(ADC12MEM10 = 0x0734); -PROVIDE(ADC12MEM10_L = 0x0734); -PROVIDE(ADC12MEM10_H = 0x0735); -PROVIDE(ADC12MEM11 = 0x0736); -PROVIDE(ADC12MEM11_L = 0x0736); -PROVIDE(ADC12MEM11_H = 0x0737); -PROVIDE(ADC12MEM12 = 0x0738); -PROVIDE(ADC12MEM12_L = 0x0738); -PROVIDE(ADC12MEM12_H = 0x0739); -PROVIDE(ADC12MEM13 = 0x073A); -PROVIDE(ADC12MEM13_L = 0x073A); -PROVIDE(ADC12MEM13_H = 0x073B); -PROVIDE(ADC12MEM14 = 0x073C); -PROVIDE(ADC12MEM14_L = 0x073C); -PROVIDE(ADC12MEM14_H = 0x073D); -PROVIDE(ADC12MEM15 = 0x073E); -PROVIDE(ADC12MEM15_L = 0x073E); -PROVIDE(ADC12MEM15_H = 0x073F); -PROVIDE(ADC12MCTL0 = 0x0710); -PROVIDE(ADC12MCTL1 = 0x0711); -PROVIDE(ADC12MCTL2 = 0x0712); -PROVIDE(ADC12MCTL3 = 0x0713); -PROVIDE(ADC12MCTL4 = 0x0714); -PROVIDE(ADC12MCTL5 = 0x0715); -PROVIDE(ADC12MCTL6 = 0x0716); -PROVIDE(ADC12MCTL7 = 0x0717); -PROVIDE(ADC12MCTL8 = 0x0718); -PROVIDE(ADC12MCTL9 = 0x0719); -PROVIDE(ADC12MCTL10 = 0x071A); -PROVIDE(ADC12MCTL11 = 0x071B); -PROVIDE(ADC12MCTL12 = 0x071C); -PROVIDE(ADC12MCTL13 = 0x071D); -PROVIDE(ADC12MCTL14 = 0x071E); -PROVIDE(ADC12MCTL15 = 0x071F); -/************************************************************ -* Comparator B -************************************************************/ -PROVIDE(CBCTL0 = 0x08C0); -PROVIDE(CBCTL0_L = 0x08C0); -PROVIDE(CBCTL0_H = 0x08C1); -PROVIDE(CBCTL1 = 0x08C2); -PROVIDE(CBCTL1_L = 0x08C2); -PROVIDE(CBCTL1_H = 0x08C3); -PROVIDE(CBCTL2 = 0x08C4); -PROVIDE(CBCTL2_L = 0x08C4); -PROVIDE(CBCTL2_H = 0x08C5); -PROVIDE(CBCTL3 = 0x08C6); -PROVIDE(CBCTL3_L = 0x08C6); -PROVIDE(CBCTL3_H = 0x08C7); -PROVIDE(CBINT = 0x08CC); -PROVIDE(CBINT_L = 0x08CC); -PROVIDE(CBINT_H = 0x08CD); -PROVIDE(CBIV = 0x08CE); -/************************************************************* -* CRC Module -*************************************************************/ -PROVIDE(CRCDI = 0x0150); -PROVIDE(CRCDI_L = 0x0150); -PROVIDE(CRCDI_H = 0x0151); -PROVIDE(CRCDIRB = 0x0152); -PROVIDE(CRCDIRB_L = 0x0152); -PROVIDE(CRCDIRB_H = 0x0153); -PROVIDE(CRCINIRES = 0x0154); -PROVIDE(CRCINIRES_L = 0x0154); -PROVIDE(CRCINIRES_H = 0x0155); -PROVIDE(CRCRESR = 0x0156); -PROVIDE(CRCRESR_L = 0x0156); -PROVIDE(CRCRESR_H = 0x0157); -/************************************************************ -* DMA_X -************************************************************/ -PROVIDE(DMACTL0 = 0x0500); -PROVIDE(DMACTL1 = 0x0502); -PROVIDE(DMACTL2 = 0x0504); -PROVIDE(DMACTL3 = 0x0506); -PROVIDE(DMACTL4 = 0x0508); -PROVIDE(DMAIV = 0x050E); -PROVIDE(DMA0CTL = 0x0510); -PROVIDE(DMA0SA = 0x0512); -PROVIDE(DMA0SAL = 0x0512); -PROVIDE(DMA0DA = 0x0516); -PROVIDE(DMA0DAL = 0x0516); -PROVIDE(DMA0SZ = 0x051A); -PROVIDE(DMA1CTL = 0x0520); -PROVIDE(DMA1SA = 0x0522); -PROVIDE(DMA1SAL = 0x0522); -PROVIDE(DMA1DA = 0x0526); -PROVIDE(DMA1DAL = 0x0526); -PROVIDE(DMA1SZ = 0x052A); -PROVIDE(DMA2CTL = 0x0530); -PROVIDE(DMA2SA = 0x0532); -PROVIDE(DMA2SAL = 0x0532); -PROVIDE(DMA2DA = 0x0536); -PROVIDE(DMA2DAL = 0x0536); -PROVIDE(DMA2SZ = 0x053A); -/************************************************************* -* Flash Memory -*************************************************************/ -PROVIDE(FCTL1 = 0x0140); -PROVIDE(FCTL1_L = 0x0140); -PROVIDE(FCTL1_H = 0x0141); -PROVIDE(FCTL3 = 0x0144); -PROVIDE(FCTL3_L = 0x0144); -PROVIDE(FCTL3_H = 0x0145); -PROVIDE(FCTL4 = 0x0146); -PROVIDE(FCTL4_L = 0x0146); -PROVIDE(FCTL4_H = 0x0147); -/************************************************************ -* HARDWARE MULTIPLIER 32Bit -************************************************************/ -PROVIDE(MPY = 0x04C0); -PROVIDE(MPY_L = 0x04C0); -PROVIDE(MPY_H = 0x04C1); -PROVIDE(MPYS = 0x04C2); -PROVIDE(MPYS_L = 0x04C2); -PROVIDE(MPYS_H = 0x04C3); -PROVIDE(MAC = 0x04C4); -PROVIDE(MAC_L = 0x04C4); -PROVIDE(MAC_H = 0x04C5); -PROVIDE(MACS = 0x04C6); -PROVIDE(MACS_L = 0x04C6); -PROVIDE(MACS_H = 0x04C7); -PROVIDE(OP2 = 0x04C8); -PROVIDE(OP2_L = 0x04C8); -PROVIDE(OP2_H = 0x04C9); -PROVIDE(RESLO = 0x04CA); -PROVIDE(RESLO_L = 0x04CA); -PROVIDE(RESLO_H = 0x04CB); -PROVIDE(RESHI = 0x04CC); -PROVIDE(RESHI_L = 0x04CC); -PROVIDE(RESHI_H = 0x04CD); -PROVIDE(SUMEXT = 0x04CE); -PROVIDE(SUMEXT_L = 0x04CE); -PROVIDE(SUMEXT_H = 0x04CF); -PROVIDE(MPY32L = 0x04D0); -PROVIDE(MPY32L_L = 0x04D0); -PROVIDE(MPY32L_H = 0x04D1); -PROVIDE(MPY32H = 0x04D2); -PROVIDE(MPY32H_L = 0x04D2); -PROVIDE(MPY32H_H = 0x04D3); -PROVIDE(MPYS32L = 0x04D4); -PROVIDE(MPYS32L_L = 0x04D4); -PROVIDE(MPYS32L_H = 0x04D5); -PROVIDE(MPYS32H = 0x04D6); -PROVIDE(MPYS32H_L = 0x04D6); -PROVIDE(MPYS32H_H = 0x04D7); -PROVIDE(MAC32L = 0x04D8); -PROVIDE(MAC32L_L = 0x04D8); -PROVIDE(MAC32L_H = 0x04D9); -PROVIDE(MAC32H = 0x04DA); -PROVIDE(MAC32H_L = 0x04DA); -PROVIDE(MAC32H_H = 0x04DB); -PROVIDE(MACS32L = 0x04DC); -PROVIDE(MACS32L_L = 0x04DC); -PROVIDE(MACS32L_H = 0x04DD); -PROVIDE(MACS32H = 0x04DE); -PROVIDE(MACS32H_L = 0x04DE); -PROVIDE(MACS32H_H = 0x04DF); -PROVIDE(OP2L = 0x04E0); -PROVIDE(OP2L_L = 0x04E0); -PROVIDE(OP2L_H = 0x04E1); -PROVIDE(OP2H = 0x04E2); -PROVIDE(OP2H_L = 0x04E2); -PROVIDE(OP2H_H = 0x04E3); -PROVIDE(RES0 = 0x04E4); -PROVIDE(RES0_L = 0x04E4); -PROVIDE(RES0_H = 0x04E5); -PROVIDE(RES1 = 0x04E6); -PROVIDE(RES1_L = 0x04E6); -PROVIDE(RES1_H = 0x04E7); -PROVIDE(RES2 = 0x04E8); -PROVIDE(RES2_L = 0x04E8); -PROVIDE(RES2_H = 0x04E9); -PROVIDE(RES3 = 0x04EA); -PROVIDE(RES3_L = 0x04EA); -PROVIDE(RES3_H = 0x04EB); -PROVIDE(MPY32CTL0 = 0x04EC); -PROVIDE(MPY32CTL0_L = 0x04EC); -PROVIDE(MPY32CTL0_H = 0x04ED); -/************************************************************ -* DIGITAL I/O Port1/2 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PAIN = 0x0200); -PROVIDE(PAIN_L = 0x0200); -PROVIDE(PAIN_H = 0x0201); -PROVIDE(PAOUT = 0x0202); -PROVIDE(PAOUT_L = 0x0202); -PROVIDE(PAOUT_H = 0x0203); -PROVIDE(PADIR = 0x0204); -PROVIDE(PADIR_L = 0x0204); -PROVIDE(PADIR_H = 0x0205); -PROVIDE(PAREN = 0x0206); -PROVIDE(PAREN_L = 0x0206); -PROVIDE(PAREN_H = 0x0207); -PROVIDE(PADS = 0x0208); -PROVIDE(PADS_L = 0x0208); -PROVIDE(PADS_H = 0x0209); -PROVIDE(PASEL = 0x020A); -PROVIDE(PASEL_L = 0x020A); -PROVIDE(PASEL_H = 0x020B); -PROVIDE(PAIES = 0x0218); -PROVIDE(PAIES_L = 0x0218); -PROVIDE(PAIES_H = 0x0219); -PROVIDE(PAIE = 0x021A); -PROVIDE(PAIE_L = 0x021A); -PROVIDE(PAIE_H = 0x021B); -PROVIDE(PAIFG = 0x021C); -PROVIDE(PAIFG_L = 0x021C); -PROVIDE(PAIFG_H = 0x021D); -PROVIDE(P1IV = 0x020E); -PROVIDE(P2IV = 0x021E); -/************************************************************ -* DIGITAL I/O Port3/4 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PBIN = 0x0220); -PROVIDE(PBIN_L = 0x0220); -PROVIDE(PBIN_H = 0x0221); -PROVIDE(PBOUT = 0x0222); -PROVIDE(PBOUT_L = 0x0222); -PROVIDE(PBOUT_H = 0x0223); -PROVIDE(PBDIR = 0x0224); -PROVIDE(PBDIR_L = 0x0224); -PROVIDE(PBDIR_H = 0x0225); -PROVIDE(PBREN = 0x0226); -PROVIDE(PBREN_L = 0x0226); -PROVIDE(PBREN_H = 0x0227); -PROVIDE(PBDS = 0x0228); -PROVIDE(PBDS_L = 0x0228); -PROVIDE(PBDS_H = 0x0229); -PROVIDE(PBSEL = 0x022A); -PROVIDE(PBSEL_L = 0x022A); -PROVIDE(PBSEL_H = 0x022B); -/************************************************************ -* DIGITAL I/O Port5/6 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PCIN = 0x0240); -PROVIDE(PCIN_L = 0x0240); -PROVIDE(PCIN_H = 0x0241); -PROVIDE(PCOUT = 0x0242); -PROVIDE(PCOUT_L = 0x0242); -PROVIDE(PCOUT_H = 0x0243); -PROVIDE(PCDIR = 0x0244); -PROVIDE(PCDIR_L = 0x0244); -PROVIDE(PCDIR_H = 0x0245); -PROVIDE(PCREN = 0x0246); -PROVIDE(PCREN_L = 0x0246); -PROVIDE(PCREN_H = 0x0247); -PROVIDE(PCDS = 0x0248); -PROVIDE(PCDS_L = 0x0248); -PROVIDE(PCDS_H = 0x0249); -PROVIDE(PCSEL = 0x024A); -PROVIDE(PCSEL_L = 0x024A); -PROVIDE(PCSEL_H = 0x024B); -/************************************************************ -* DIGITAL I/O Port7/8 Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PDIN = 0x0260); -PROVIDE(PDIN_L = 0x0260); -PROVIDE(PDIN_H = 0x0261); -PROVIDE(PDOUT = 0x0262); -PROVIDE(PDOUT_L = 0x0262); -PROVIDE(PDOUT_H = 0x0263); -PROVIDE(PDDIR = 0x0264); -PROVIDE(PDDIR_L = 0x0264); -PROVIDE(PDDIR_H = 0x0265); -PROVIDE(PDREN = 0x0266); -PROVIDE(PDREN_L = 0x0266); -PROVIDE(PDREN_H = 0x0267); -PROVIDE(PDDS = 0x0268); -PROVIDE(PDDS_L = 0x0268); -PROVIDE(PDDS_H = 0x0269); -PROVIDE(PDSEL = 0x026A); -PROVIDE(PDSEL_L = 0x026A); -PROVIDE(PDSEL_H = 0x026B); -/************************************************************ -* DIGITAL I/O PortJ Pull up / Pull down Resistors -************************************************************/ -PROVIDE(PJIN = 0x0320); -PROVIDE(PJIN_L = 0x0320); -PROVIDE(PJIN_H = 0x0321); -PROVIDE(PJOUT = 0x0322); -PROVIDE(PJOUT_L = 0x0322); -PROVIDE(PJOUT_H = 0x0323); -PROVIDE(PJDIR = 0x0324); -PROVIDE(PJDIR_L = 0x0324); -PROVIDE(PJDIR_H = 0x0325); -PROVIDE(PJREN = 0x0326); -PROVIDE(PJREN_L = 0x0326); -PROVIDE(PJREN_H = 0x0327); -PROVIDE(PJDS = 0x0328); -PROVIDE(PJDS_L = 0x0328); -PROVIDE(PJDS_H = 0x0329); -/************************************************************ -* PORT MAPPING CONTROLLER -************************************************************/ -PROVIDE(PMAPKEYID = 0x01C0); -PROVIDE(PMAPKEYID_L = 0x01C0); -PROVIDE(PMAPKEYID_H = 0x01C1); -PROVIDE(PMAPCTL = 0x01C2); -PROVIDE(PMAPCTL_L = 0x01C2); -PROVIDE(PMAPCTL_H = 0x01C3); -/************************************************************ -* PORT 4 MAPPING CONTROLLER -************************************************************/ -PROVIDE(P4MAP01 = 0x01E0); -PROVIDE(P4MAP01_L = 0x01E0); -PROVIDE(P4MAP01_H = 0x01E1); -PROVIDE(P4MAP23 = 0x01E2); -PROVIDE(P4MAP23_L = 0x01E2); -PROVIDE(P4MAP23_H = 0x01E3); -PROVIDE(P4MAP45 = 0x01E4); -PROVIDE(P4MAP45_L = 0x01E4); -PROVIDE(P4MAP45_H = 0x01E5); -PROVIDE(P4MAP67 = 0x01E6); -PROVIDE(P4MAP67_L = 0x01E6); -PROVIDE(P4MAP67_H = 0x01E7); -/************************************************************ -* PMM - Power Management System -************************************************************/ -PROVIDE(PMMCTL0 = 0x0120); -PROVIDE(PMMCTL0_L = 0x0120); -PROVIDE(PMMCTL0_H = 0x0121); -PROVIDE(PMMCTL1 = 0x0122); -PROVIDE(PMMCTL1_L = 0x0122); -PROVIDE(PMMCTL1_H = 0x0123); -PROVIDE(SVSMHCTL = 0x0124); -PROVIDE(SVSMHCTL_L = 0x0124); -PROVIDE(SVSMHCTL_H = 0x0125); -PROVIDE(SVSMLCTL = 0x0126); -PROVIDE(SVSMLCTL_L = 0x0126); -PROVIDE(SVSMLCTL_H = 0x0127); -PROVIDE(SVSMIO = 0x0128); -PROVIDE(SVSMIO_L = 0x0128); -PROVIDE(SVSMIO_H = 0x0129); -PROVIDE(PMMIFG = 0x012C); -PROVIDE(PMMIFG_L = 0x012C); -PROVIDE(PMMIFG_H = 0x012D); -PROVIDE(PMMRIE = 0x012E); -PROVIDE(PMMRIE_L = 0x012E); -PROVIDE(PMMRIE_H = 0x012F); -PROVIDE(PM5CTL0 = 0x0130); -PROVIDE(PM5CTL0_L = 0x0130); -PROVIDE(PM5CTL0_H = 0x0131); -/************************************************************* -* RAM Control Module -*************************************************************/ -PROVIDE(RCCTL0 = 0x0158); -PROVIDE(RCCTL0_L = 0x0158); -PROVIDE(RCCTL0_H = 0x0159); -/************************************************************ -* Shared Reference -************************************************************/ -PROVIDE(REFCTL0 = 0x01B0); -PROVIDE(REFCTL0_L = 0x01B0); -PROVIDE(REFCTL0_H = 0x01B1); -/************************************************************ -* Real Time Clock -************************************************************/ -PROVIDE(RTCCTL01 = 0x04A0); -PROVIDE(RTCCTL01_L = 0x04A0); -PROVIDE(RTCCTL01_H = 0x04A1); -PROVIDE(RTCCTL23 = 0x04A2); -PROVIDE(RTCCTL23_L = 0x04A2); -PROVIDE(RTCCTL23_H = 0x04A3); -PROVIDE(RTCPS0CTL = 0x04A8); -PROVIDE(RTCPS0CTL_L = 0x04A8); -PROVIDE(RTCPS0CTL_H = 0x04A9); -PROVIDE(RTCPS1CTL = 0x04AA); -PROVIDE(RTCPS1CTL_L = 0x04AA); -PROVIDE(RTCPS1CTL_H = 0x04AB); -PROVIDE(RTCPS = 0x04AC); -PROVIDE(RTCPS_L = 0x04AC); -PROVIDE(RTCPS_H = 0x04AD); -PROVIDE(RTCIV = 0x04AE); -PROVIDE(RTCTIM0 = 0x04B0); -PROVIDE(RTCTIM0_L = 0x04B0); -PROVIDE(RTCTIM0_H = 0x04B1); -PROVIDE(RTCTIM1 = 0x04B2); -PROVIDE(RTCTIM1_L = 0x04B2); -PROVIDE(RTCTIM1_H = 0x04B3); -PROVIDE(RTCDATE = 0x04B4); -PROVIDE(RTCDATE_L = 0x04B4); -PROVIDE(RTCDATE_H = 0x04B5); -PROVIDE(RTCYEAR = 0x04B6); -PROVIDE(RTCYEAR_L = 0x04B6); -PROVIDE(RTCYEAR_H = 0x04B7); -PROVIDE(RTCAMINHR = 0x04B8); -PROVIDE(RTCAMINHR_L = 0x04B8); -PROVIDE(RTCAMINHR_H = 0x04B9); -PROVIDE(RTCADOWDAY = 0x04BA); -PROVIDE(RTCADOWDAY_L = 0x04BA); -PROVIDE(RTCADOWDAY_H = 0x04BB); -/************************************************************ -* SFR - Special Function Register Module -************************************************************/ -PROVIDE(SFRIE1 = 0x0100); -PROVIDE(SFRIE1_L = 0x0100); -PROVIDE(SFRIE1_H = 0x0101); -PROVIDE(SFRIFG1 = 0x0102); -PROVIDE(SFRIFG1_L = 0x0102); -PROVIDE(SFRIFG1_H = 0x0103); -PROVIDE(SFRRPCR = 0x0104); -PROVIDE(SFRRPCR_L = 0x0104); -PROVIDE(SFRRPCR_H = 0x0105); -/************************************************************ -* SYS - System Module -************************************************************/ -PROVIDE(SYSCTL = 0x0180); -PROVIDE(SYSCTL_L = 0x0180); -PROVIDE(SYSCTL_H = 0x0181); -PROVIDE(SYSBSLC = 0x0182); -PROVIDE(SYSBSLC_L = 0x0182); -PROVIDE(SYSBSLC_H = 0x0183); -PROVIDE(SYSJMBC = 0x0186); -PROVIDE(SYSJMBC_L = 0x0186); -PROVIDE(SYSJMBC_H = 0x0187); -PROVIDE(SYSJMBI0 = 0x0188); -PROVIDE(SYSJMBI0_L = 0x0188); -PROVIDE(SYSJMBI0_H = 0x0189); -PROVIDE(SYSJMBI1 = 0x018A); -PROVIDE(SYSJMBI1_L = 0x018A); -PROVIDE(SYSJMBI1_H = 0x018B); -PROVIDE(SYSJMBO0 = 0x018C); -PROVIDE(SYSJMBO0_L = 0x018C); -PROVIDE(SYSJMBO0_H = 0x018D); -PROVIDE(SYSJMBO1 = 0x018E); -PROVIDE(SYSJMBO1_L = 0x018E); -PROVIDE(SYSJMBO1_H = 0x018F); -PROVIDE(SYSBERRIV = 0x0198); -PROVIDE(SYSBERRIV_L = 0x0198); -PROVIDE(SYSBERRIV_H = 0x0199); -PROVIDE(SYSUNIV = 0x019A); -PROVIDE(SYSUNIV_L = 0x019A); -PROVIDE(SYSUNIV_H = 0x019B); -PROVIDE(SYSSNIV = 0x019C); -PROVIDE(SYSSNIV_L = 0x019C); -PROVIDE(SYSSNIV_H = 0x019D); -PROVIDE(SYSRSTIV = 0x019E); -PROVIDE(SYSRSTIV_L = 0x019E); -PROVIDE(SYSRSTIV_H = 0x019F); -/************************************************************ -* Timer0_A5 -************************************************************/ -PROVIDE(TA0CTL = 0x0340); -PROVIDE(TA0CCTL0 = 0x0342); -PROVIDE(TA0CCTL1 = 0x0344); -PROVIDE(TA0CCTL2 = 0x0346); -PROVIDE(TA0CCTL3 = 0x0348); -PROVIDE(TA0CCTL4 = 0x034A); -PROVIDE(TA0R = 0x0350); -PROVIDE(TA0CCR0 = 0x0352); -PROVIDE(TA0CCR1 = 0x0354); -PROVIDE(TA0CCR2 = 0x0356); -PROVIDE(TA0CCR3 = 0x0358); -PROVIDE(TA0CCR4 = 0x035A); -PROVIDE(TA0IV = 0x036E); -PROVIDE(TA0EX0 = 0x0360); -/************************************************************ -* Timer1_A3 -************************************************************/ -PROVIDE(TA1CTL = 0x0380); -PROVIDE(TA1CCTL0 = 0x0382); -PROVIDE(TA1CCTL1 = 0x0384); -PROVIDE(TA1CCTL2 = 0x0386); -PROVIDE(TA1R = 0x0390); -PROVIDE(TA1CCR0 = 0x0392); -PROVIDE(TA1CCR1 = 0x0394); -PROVIDE(TA1CCR2 = 0x0396); -PROVIDE(TA1IV = 0x03AE); -PROVIDE(TA1EX0 = 0x03A0); -/************************************************************ -* Timer2_A3 -************************************************************/ -PROVIDE(TA2CTL = 0x0400); -PROVIDE(TA2CCTL0 = 0x0402); -PROVIDE(TA2CCTL1 = 0x0404); -PROVIDE(TA2CCTL2 = 0x0406); -PROVIDE(TA2R = 0x0410); -PROVIDE(TA2CCR0 = 0x0412); -PROVIDE(TA2CCR1 = 0x0414); -PROVIDE(TA2CCR2 = 0x0416); -PROVIDE(TA2IV = 0x042E); -PROVIDE(TA2EX0 = 0x0420); -/************************************************************ -* Timer0_B7 -************************************************************/ -PROVIDE(TB0CTL = 0x03C0); -PROVIDE(TB0CCTL0 = 0x03C2); -PROVIDE(TB0CCTL1 = 0x03C4); -PROVIDE(TB0CCTL2 = 0x03C6); -PROVIDE(TB0CCTL3 = 0x03C8); -PROVIDE(TB0CCTL4 = 0x03CA); -PROVIDE(TB0CCTL5 = 0x03CC); -PROVIDE(TB0CCTL6 = 0x03CE); -PROVIDE(TB0R = 0x03D0); -PROVIDE(TB0CCR0 = 0x03D2); -PROVIDE(TB0CCR1 = 0x03D4); -PROVIDE(TB0CCR2 = 0x03D6); -PROVIDE(TB0CCR3 = 0x03D8); -PROVIDE(TB0CCR4 = 0x03DA); -PROVIDE(TB0CCR5 = 0x03DC); -PROVIDE(TB0CCR6 = 0x03DE); -PROVIDE(TB0EX0 = 0x03E0); -PROVIDE(TB0IV = 0x03EE); -/************************************************************ -* USB -************************************************************/ -PROVIDE(USBKEYID = 0x0900); -PROVIDE(USBKEYID_L = 0x0900); -PROVIDE(USBKEYID_H = 0x0901); -PROVIDE(USBCNF = 0x0902); -PROVIDE(USBCNF_L = 0x0902); -PROVIDE(USBCNF_H = 0x0903); -PROVIDE(USBPHYCTL = 0x0904); -PROVIDE(USBPHYCTL_L = 0x0904); -PROVIDE(USBPHYCTL_H = 0x0905); -PROVIDE(USBPWRCTL = 0x0908); -PROVIDE(USBPWRCTL_L = 0x0908); -PROVIDE(USBPWRCTL_H = 0x0909); -PROVIDE(USBPLLCTL = 0x0910); -PROVIDE(USBPLLCTL_L = 0x0910); -PROVIDE(USBPLLCTL_H = 0x0911); -PROVIDE(USBPLLDIVB = 0x0912); -PROVIDE(USBPLLDIVB_L = 0x0912); -PROVIDE(USBPLLDIVB_H = 0x0913); -PROVIDE(USBPLLIR = 0x0914); -PROVIDE(USBPLLIR_L = 0x0914); -PROVIDE(USBPLLIR_H = 0x0915); -PROVIDE(USBIEPCNF_0 = 0x0920); -PROVIDE(USBIEPCNT_0 = 0x0921); -PROVIDE(USBOEPCNF_0 = 0x0922); -PROVIDE(USBOEPCNT_0 = 0x0923); -PROVIDE(USBIEPIE = 0x092E); -PROVIDE(USBOEPIE = 0x092F); -PROVIDE(USBIEPIFG = 0x0930); -PROVIDE(USBOEPIFG = 0x0931); -PROVIDE(USBVECINT = 0x0932); -PROVIDE(USBVECINT_L = 0x0932); -PROVIDE(USBVECINT_H = 0x0933); -PROVIDE(USBMAINT = 0x0936); -PROVIDE(USBMAINT_L = 0x0936); -PROVIDE(USBMAINT_H = 0x0937); -PROVIDE(USBTSREG = 0x0938); -PROVIDE(USBTSREG_L = 0x0938); -PROVIDE(USBTSREG_H = 0x0939); -PROVIDE(USBFN = 0x093A); -PROVIDE(USBFN_L = 0x093A); -PROVIDE(USBFN_H = 0x093B); -PROVIDE(USBCTL = 0x093C); -PROVIDE(USBIE = 0x093D); -PROVIDE(USBIFG = 0x093E); -PROVIDE(USBFUNADR = 0x093F); -PROVIDE(USBIEPSIZXY_7 = 0x23FF); -PROVIDE(USBIEPBCTY_7 = 0x23FE); -PROVIDE(USBIEPBBAY_7 = 0x23FD); -PROVIDE(USBIEPBCTX_7 = 0x23FA); -PROVIDE(USBIEPBBAX_7 = 0x23F9); -PROVIDE(USBIEPCNF_7 = 0x23F8); -PROVIDE(USBIEPSIZXY_6 = 0x23F7); -PROVIDE(USBIEPBCTY_6 = 0x23F6); -PROVIDE(USBIEPBBAY_6 = 0x23F5); -PROVIDE(USBIEPBCTX_6 = 0x23F2); -PROVIDE(USBIEPBBAX_6 = 0x23F1); -PROVIDE(USBIEPCNF_6 = 0x23F0); -PROVIDE(USBIEPSIZXY_5 = 0x23EF); -PROVIDE(USBIEPBCTY_5 = 0x23EE); -PROVIDE(USBIEPBBAY_5 = 0x23ED); -PROVIDE(USBIEPBCTX_5 = 0x23EA); -PROVIDE(USBIEPBBAX_5 = 0x23E9); -PROVIDE(USBIEPCNF_5 = 0x23E8); -PROVIDE(USBIEPSIZXY_4 = 0x23E7); -PROVIDE(USBIEPBCTY_4 = 0x23E6); -PROVIDE(USBIEPBBAY_4 = 0x23E5); -PROVIDE(USBIEPBCTX_4 = 0x23E2); -PROVIDE(USBIEPBBAX_4 = 0x23E1); -PROVIDE(USBIEPCNF_4 = 0x23E0); -PROVIDE(USBIEPSIZXY_3 = 0x23DF); -PROVIDE(USBIEPBCTY_3 = 0x23DE); -PROVIDE(USBIEPBBAY_3 = 0x23DD); -PROVIDE(USBIEPBCTX_3 = 0x23DA); -PROVIDE(USBIEPBBAX_3 = 0x23D9); -PROVIDE(USBIEPCNF_3 = 0x23D8); -PROVIDE(USBIEPSIZXY_2 = 0x23D7); -PROVIDE(USBIEPBCTY_2 = 0x23D6); -PROVIDE(USBIEPBBAY_2 = 0x23D5); -PROVIDE(USBIEPBCTX_2 = 0x23D2); -PROVIDE(USBIEPBBAX_2 = 0x23D1); -PROVIDE(USBIEPCNF_2 = 0x23D0); -PROVIDE(USBIEPSIZXY_1 = 0x23CF); -PROVIDE(USBIEPBCTY_1 = 0x23CE); -PROVIDE(USBIEPBBAY_1 = 0x23CD); -PROVIDE(USBIEPBCTX_1 = 0x23CA); -PROVIDE(USBIEPBBAX_1 = 0x23C9); -PROVIDE(USBIEPCNF_1 = 0x23C8); -PROVIDE(USBOEPSIZXY_7 = 0x23BF); -PROVIDE(USBOEPBCTY_7 = 0x23BE); -PROVIDE(USBOEPBBAY_7 = 0x23BD); -PROVIDE(USBOEPBCTX_7 = 0x23BA); -PROVIDE(USBOEPBBAX_7 = 0x23B9); -PROVIDE(USBOEPCNF_7 = 0x23B8); -PROVIDE(USBOEPSIZXY_6 = 0x23B7); -PROVIDE(USBOEPBCTY_6 = 0x23B6); -PROVIDE(USBOEPBBAY_6 = 0x23B5); -PROVIDE(USBOEPBCTX_6 = 0x23B2); -PROVIDE(USBOEPBBAX_6 = 0x23B1); -PROVIDE(USBOEPCNF_6 = 0x23B0); -PROVIDE(USBOEPSIZXY_5 = 0x23AF); -PROVIDE(USBOEPBCTY_5 = 0x23AE); -PROVIDE(USBOEPBBAY_5 = 0x23AD); -PROVIDE(USBOEPBCTX_5 = 0x23AA); -PROVIDE(USBOEPBBAX_5 = 0x23A9); -PROVIDE(USBOEPCNF_5 = 0x23A8); -PROVIDE(USBOEPSIZXY_4 = 0x23A7); -PROVIDE(USBOEPBCTY_4 = 0x23A6); -PROVIDE(USBOEPBBAY_4 = 0x23A5); -PROVIDE(USBOEPBCTX_4 = 0x23A2); -PROVIDE(USBOEPBBAX_4 = 0x23A1); -PROVIDE(USBOEPCNF_4 = 0x23A0); -PROVIDE(USBOEPSIZXY_3 = 0x239F); -PROVIDE(USBOEPBCTY_3 = 0x239E); -PROVIDE(USBOEPBBAY_3 = 0x239D); -PROVIDE(USBOEPBCTX_3 = 0x239A); -PROVIDE(USBOEPBBAX_3 = 0x2399); -PROVIDE(USBOEPCNF_3 = 0x2398); -PROVIDE(USBOEPSIZXY_2 = 0x2397); -PROVIDE(USBOEPBCTY_2 = 0x2396); -PROVIDE(USBOEPBBAY_2 = 0x2395); -PROVIDE(USBOEPBCTX_2 = 0x2392); -PROVIDE(USBOEPBBAX_2 = 0x2391); -PROVIDE(USBOEPCNF_2 = 0x2390); -PROVIDE(USBOEPSIZXY_1 = 0x238F); -PROVIDE(USBOEPBCTY_1 = 0x238E); -PROVIDE(USBOEPBBAY_1 = 0x238D); -PROVIDE(USBOEPBCTX_1 = 0x238A); -PROVIDE(USBOEPBBAX_1 = 0x2389); -PROVIDE(USBOEPCNF_1 = 0x2388); -PROVIDE(USBSUBLK = 0x2380); -PROVIDE(USBIEP0BUF = 0x2378); -PROVIDE(USBOEP0BUF = 0x2370); -PROVIDE(USBTOPBUFF = 0x236F); -PROVIDE(USBSTABUFF = 0x1C00); -/************************************************************ -* UNIFIED CLOCK SYSTEM -************************************************************/ -PROVIDE(UCSCTL0 = 0x0160); -PROVIDE(UCSCTL0_L = 0x0160); -PROVIDE(UCSCTL0_H = 0x0161); -PROVIDE(UCSCTL1 = 0x0162); -PROVIDE(UCSCTL1_L = 0x0162); -PROVIDE(UCSCTL1_H = 0x0163); -PROVIDE(UCSCTL2 = 0x0164); -PROVIDE(UCSCTL2_L = 0x0164); -PROVIDE(UCSCTL2_H = 0x0165); -PROVIDE(UCSCTL3 = 0x0166); -PROVIDE(UCSCTL3_L = 0x0166); -PROVIDE(UCSCTL3_H = 0x0167); -PROVIDE(UCSCTL4 = 0x0168); -PROVIDE(UCSCTL4_L = 0x0168); -PROVIDE(UCSCTL4_H = 0x0169); -PROVIDE(UCSCTL5 = 0x016A); -PROVIDE(UCSCTL5_L = 0x016A); -PROVIDE(UCSCTL5_H = 0x016B); -PROVIDE(UCSCTL6 = 0x016C); -PROVIDE(UCSCTL6_L = 0x016C); -PROVIDE(UCSCTL6_H = 0x016D); -PROVIDE(UCSCTL7 = 0x016E); -PROVIDE(UCSCTL7_L = 0x016E); -PROVIDE(UCSCTL7_H = 0x016F); -PROVIDE(UCSCTL8 = 0x0170); -PROVIDE(UCSCTL8_L = 0x0170); -PROVIDE(UCSCTL8_H = 0x0171); -/************************************************************ -* USCI A0 -************************************************************/ -PROVIDE(UCA0CTLW0 = 0x05C0); -PROVIDE(UCA0CTLW0_L = 0x05C0); -PROVIDE(UCA0CTLW0_H = 0x05C1); -PROVIDE(UCA0BRW = 0x05C6); -PROVIDE(UCA0BRW_L = 0x05C6); -PROVIDE(UCA0BRW_H = 0x05C7); -PROVIDE(UCA0MCTL = 0x05C8); -PROVIDE(UCA0STAT = 0x05CA); -PROVIDE(UCA0RXBUF = 0x05CC); -PROVIDE(UCA0TXBUF = 0x05CE); -PROVIDE(UCA0ABCTL = 0x05D0); -PROVIDE(UCA0IRCTL = 0x05D2); -PROVIDE(UCA0IRCTL_L = 0x05D2); -PROVIDE(UCA0IRCTL_H = 0x05D3); -PROVIDE(UCA0ICTL = 0x05DC); -PROVIDE(UCA0ICTL_L = 0x05DC); -PROVIDE(UCA0ICTL_H = 0x05DD); -PROVIDE(UCA0IV = 0x05DE); -/************************************************************ -* USCI B0 -************************************************************/ -PROVIDE(UCB0CTLW0 = 0x05E0); -PROVIDE(UCB0CTLW0_L = 0x05E0); -PROVIDE(UCB0CTLW0_H = 0x05E1); -PROVIDE(UCB0BRW = 0x05E6); -PROVIDE(UCB0BRW_L = 0x05E6); -PROVIDE(UCB0BRW_H = 0x05E7); -PROVIDE(UCB0STAT = 0x05EA); -PROVIDE(UCB0RXBUF = 0x05EC); -PROVIDE(UCB0TXBUF = 0x05EE); -PROVIDE(UCB0I2COA = 0x05F0); -PROVIDE(UCB0I2COA_L = 0x05F0); -PROVIDE(UCB0I2COA_H = 0x05F1); -PROVIDE(UCB0I2CSA = 0x05F2); -PROVIDE(UCB0I2CSA_L = 0x05F2); -PROVIDE(UCB0I2CSA_H = 0x05F3); -PROVIDE(UCB0ICTL = 0x05FC); -PROVIDE(UCB0ICTL_L = 0x05FC); -PROVIDE(UCB0ICTL_H = 0x05FD); -PROVIDE(UCB0IV = 0x05FE); -/************************************************************ -* USCI A1 -************************************************************/ -PROVIDE(UCA1CTLW0 = 0x0600); -PROVIDE(UCA1CTLW0_L = 0x0600); -PROVIDE(UCA1CTLW0_H = 0x0601); -PROVIDE(UCA1BRW = 0x0606); -PROVIDE(UCA1BRW_L = 0x0606); -PROVIDE(UCA1BRW_H = 0x0607); -PROVIDE(UCA1MCTL = 0x0608); -PROVIDE(UCA1STAT = 0x060A); -PROVIDE(UCA1RXBUF = 0x060C); -PROVIDE(UCA1TXBUF = 0x060E); -PROVIDE(UCA1ABCTL = 0x0610); -PROVIDE(UCA1IRCTL = 0x0612); -PROVIDE(UCA1IRCTL_L = 0x0612); -PROVIDE(UCA1IRCTL_H = 0x0613); -PROVIDE(UCA1ICTL = 0x061C); -PROVIDE(UCA1ICTL_L = 0x061C); -PROVIDE(UCA1ICTL_H = 0x061D); -PROVIDE(UCA1IV = 0x061E); -/************************************************************ -* USCI B1 -************************************************************/ -PROVIDE(UCB1CTLW0 = 0x0620); -PROVIDE(UCB1CTLW0_L = 0x0620); -PROVIDE(UCB1CTLW0_H = 0x0621); -PROVIDE(UCB1BRW = 0x0626); -PROVIDE(UCB1BRW_L = 0x0626); -PROVIDE(UCB1BRW_H = 0x0627); -PROVIDE(UCB1STAT = 0x062A); -PROVIDE(UCB1RXBUF = 0x062C); -PROVIDE(UCB1TXBUF = 0x062E); -PROVIDE(UCB1I2COA = 0x0630); -PROVIDE(UCB1I2COA_L = 0x0630); -PROVIDE(UCB1I2COA_H = 0x0631); -PROVIDE(UCB1I2CSA = 0x0632); -PROVIDE(UCB1I2CSA_L = 0x0632); -PROVIDE(UCB1I2CSA_H = 0x0633); -PROVIDE(UCB1ICTL = 0x063C); -PROVIDE(UCB1ICTL_L = 0x063C); -PROVIDE(UCB1ICTL_H = 0x063D); -PROVIDE(UCB1IV = 0x063E); -/************************************************************ -* WATCHDOG TIMER A -************************************************************/ -PROVIDE(WDTCTL = 0x015C); -PROVIDE(WDTCTL_L = 0x015C); -PROVIDE(WDTCTL_H = 0x015D); -/************************************************************ -* TLV Descriptors -************************************************************/ -/************************************************************ -* Interrupt Vectors (offset from 0xFF80) -************************************************************/ -/************************************************************ -* End of Modules -************************************************************/ |