dcd/ch32_usbfs: support CH32V103 combined endpoint control register

CH32V103 uses the older USBFS IP: a single combined UEPn_CTRL register per
endpoint (IN response in bits [1:0], OUT response in [3:2], shared auto-toggle,
separate IN/OUT toggles) instead of the separate UEPn_TX_CTRL/UEPn_RX_CTRL
bytes of the newer IP (CH32V20x/V307). The shared driver was written for the
newer IP, so EP0 control transfers never worked on V103: the OUT response was
written to a reserved byte and the IN write clobbered the OUT bits.

- ch32_usbfs_reg.h: annotate the V103 register struct with byte offsets and add
  a union exposing the combined UEPn_CTRL at the UEPn_TX_CTRL offset; define
  CH32_USBFS_EP_CTRL_COMBINED and the combined-register bit positions.
- dcd_ch32_usbfs.c: abstract EP control access behind ep_tx/rx_ctrl_set() (full
  write) and ep_tx/rx_set_response() (response-only RMW). The newer-IP path is
  unchanged; the combined path read-modify-writes the single register and arms
  the post-SETUP data stage at DATA1.
- bsp/ch32v10x: implement board_get_unique_id() (real chip UID) and drop the
  CSR 0x800 writes that corrupted the QingKe V3 interrupt config and left all
  interrupts disabled (the USB ISR never ran).

Verified on ch32v103r_r1_1v0: enumerates and passes HIL for cdc_msc, hid,
msc, midi, mtp, dfu, etc.

Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>

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