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| author | Zixun LI <[email protected]> | 2026-09-01 12:53:45 +0200 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-09-01 12:53:45 +0200 |
| commit | 762517e6c41bedba73df04bc3c2181d7e5fe1d5e (patch) | |
| tree | 01cae9f0ad8fb7b4c0b21b1f716b27818bbddc90 /examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Registers.xml | |
| parent | f4697a0626ffa81617c457c93b64e3c3816c1af0 (diff) | |
| parent | 04a6ec80d94e13c70087c44dcf095d842302bafa (diff) | |
Fix DWC2 DMA data toggle mismatch in IN-transfers
Diffstat (limited to 'examples/device/cdc_msc/ses/samd21/ATSAMD21G18A_Registers.xml')
0 files changed, 0 insertions, 0 deletions