diff options
| author | HiFiPhile <[email protected]> | 2024-05-09 13:45:44 +0200 |
|---|---|---|
| committer | HiFiPhile <[email protected]> | 2024-05-09 13:45:44 +0200 |
| commit | fd1cde9b894e5312e6c6f9da63cfea5aa05d83d2 (patch) | |
| tree | 5f43ffeecb05d80788cbe0bbc43913202a922a2a /examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h | |
| parent | d0bff6fd3ec9fc133032dea84732451d93d202b4 (diff) | |
| parent | 74e57499baac36c4cccf76549259905162031e41 (diff) | |
Merge branch 'master' into pr/2181
Diffstat (limited to 'examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h')
| -rw-r--r-- | examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 9bef9bbbf..6cc7a6577 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -81,7 +81,7 @@ #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 +#define configQUEUE_REGISTRY_SIZE 4 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 0 #define configUSE_NEWLIB_REENTRANT 0 @@ -96,6 +96,7 @@ #define configUSE_TICK_HOOK 0 #define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning #define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 /* Run time and task stats gathering related definitions. */ #define configGENERATE_RUN_TIME_STATS 0 @@ -130,23 +131,6 @@ #define INCLUDE_xEventGroupSetBitFromISR 0 #define INCLUDE_xTimerPendFunctionCall 0 -/* Define to trap errors during development. */ -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) - #define configASSERT(_exp) \ - do {\ - if ( !(_exp) ) { \ - volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ - if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ - taskDISABLE_INTERRUPTS(); \ - __asm("BKPT #0\n"); \ - }\ - }\ - } while(0) -#else - #define configASSERT( x ) -#endif - #ifdef __RX__ /* Renesas RX series */ #define vSoftwareInterruptISR INT_Excep_ICU_SWINT |