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authorZixun LI <[email protected]>2025-12-16 11:09:16 +0100
committerZixun LI <[email protected]>2025-12-16 11:09:16 +0100
commit5a7e5db78770d6fd37992b5812f910c3546f2a72 (patch)
tree1878cba0dd7a239424be31039b3c4fa3795f4989 /examples
parente00c3d1726950fda4833c265d4df0ad9b1b97c00 (diff)
fix riscv toolchain
Signed-off-by: Zixun LI <[email protected]>
Diffstat (limited to 'examples')
-rw-r--r--examples/build_system/make/toolchain/riscv_gcc.mk2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/build_system/make/toolchain/riscv_gcc.mk b/examples/build_system/make/toolchain/riscv_gcc.mk
index 843aff38c..b5de12a83 100644
--- a/examples/build_system/make/toolchain/riscv_gcc.mk
+++ b/examples/build_system/make/toolchain/riscv_gcc.mk
@@ -1,7 +1,7 @@
# makefile for arm gcc toolchain
# Can be set by family, default to ARM GCC
-CROSS_COMPILE ?= riscv-none-embed-
+CROSS_COMPILE ?= riscv-none-elf-
CC = $(CROSS_COMPILE)gcc
CXX = $(CROSS_COMPILE)g++