Merge master updates into the UAC1 host branch

Bring the audio work onto the current host core and build files before applying the remaining review fixes.

Signed-off-by: HiFiPHile <[email protected]>

3 files changed, 151 insertions, 0 deletions

diff --git a/hw/bsp/same7x/boards/same70_xplained/board.h b/hw/bsp/same7x/boards/same70_xplained/board.h
index 85e23deb8..86edf606f 100644
--- a/hw/bsp/same7x/boards/same70_xplained/board.h
+++ b/hw/bsp/same7x/boards/same70_xplained/board.h
@@ -52,6 +52,10 @@ extern "C" {
 #define UART_PORT_CLOCK ID_USART1
 #define BOARD_USART USART1
 
+// TRACE_ETM: this board wires the KSZ8081 PHY reset to PC10; the family
+// trace init holds it in reset (RMII rx lines share the trace pads)
+#define TRACE_ETM_QUIET_ENET_PHY 1
+
 static inline void board_vbus_set(uint8_t rhport, bool state) {
   (void) rhport;
   (void) state;
diff --git a/hw/bsp/same7x/boards/same70_xplained/ozone/same70.jdebug b/hw/bsp/same7x/boards/same70_xplained/ozone/same70.jdebug
new file mode 100644
index 000000000..f024f0ceb
--- /dev/null
+++ b/hw/bsp/same7x/boards/same70_xplained/ozone/same70.jdebug
@@ -0,0 +1,115 @@
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+* Notes
+*   SAM E70 Xplained: solder a 20-pin 50-mil header on the J403 ETM footprint
+*   (bottom side). TRACECLK=PD8 (peripheral D), TRACED0-3=PD4-7 (peripheral C),
+*   shared with the Ethernet PHY - no Ethernet while tracing. TRACE_ETM=1
+*   builds mux the pins and clock the TPIU from PCK3=MCK; TPIU/ETM are
+*   ROM-table-discoverable so no J-Link script is required.
+*   Trace clock pin is PCK3/2 = 75 MHz at the stock 300 MHz core (MCK 150).
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+  Project.SetSWO (0);
+  Edit.SysVar (VAR_TRACE_CORE_CLOCK, 300000000);
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
+
+  Project.SetDevice ("ATSAME70Q21B");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("4 MHz");
+
+  File.Open ("../../../../../../examples/cmake-build-same70_xplained/device/cdc_msc/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+
+  // TPIU trace clock = PCK3; it must run BEFORE Ozone arms the trace
+  // components (TPIU programming while PCK3 is stopped is lost and the port
+  // emits unformatted garbage). A target reset wipes the PMC, so this runs
+  // in the post-reset/post-download hooks, not AfterTargetConnect.
+  Target.WriteU32 (0x400E064C, 0x00000014);  // PMC_PCK3: CSS=MCK, PRESS=/2
+  Target.WriteU32 (0x400E0600, 0x00000800);  // PMC_SCER: PCK3 on
+  // wait for PCKRDY3 (bounded) before Ozone arms the trace components
+  int i;
+  i = 0;
+  while (((Target.ReadU32 (0x400E0668) & 0x00000800) == 0) && (i < 100)) {
+    i = i + 1;
+  }
+}
+
+/*********************************************************************
+*
+*       AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+
+  // TPIU trace clock = PCK3; it must run BEFORE Ozone arms the trace
+  // components (TPIU programming while PCK3 is stopped is lost and the port
+  // emits unformatted garbage). A target reset wipes the PMC, so this runs
+  // in the post-reset/post-download hooks, not AfterTargetConnect.
+  Target.WriteU32 (0x400E064C, 0x00000014);  // PMC_PCK3: CSS=MCK, PRESS=/2
+  Target.WriteU32 (0x400E0600, 0x00000800);  // PMC_SCER: PCK3 on
+  // wait for PCKRDY3 (bounded) before Ozone arms the trace components
+  int i;
+  i = 0;
+  while (((Target.ReadU32 (0x400E0668) & 0x00000800) == 0) && (i < 100)) {
+    i = i + 1;
+  }
+}
diff --git a/hw/bsp/same7x/family.c b/hw/bsp/same7x/family.c
index d02e6c5f1..8ec6a708b 100644
--- a/hw/bsp/same7x/family.c
+++ b/hw/bsp/same7x/family.c
@@ -62,6 +62,38 @@ void board_init(void) {
   /* Disable Watchdog */
   hri_wdt_set_MR_WDDIS_bit(WDT);
 
+#if defined(TRACE_ETM)
+  // same70_xplained J403 (Cortex Debug+ETM footprint, bottom side) carries
+  // 4-bit trace: TRACECLK=PD8 (peripheral D), TRACED0-3=PD4-7 (peripheral C).
+#ifdef TRACE_ETM_QUIET_ENET_PHY
+  // The trace pins double as the Ethernet PHY's RMII receive lines
+  // (PD4=CRS_DV, PD5/6=RXD0/1, PD7=RXER - PHY OUTPUTS): hold the KSZ8081 in
+  // reset or it drives against the trace stream. The reset net is a BOARD
+  // property (same70_xplained: PHY_RESET=PC10), hence the board.h gate.
+  _pmc_enable_periph_clock(ID_PIOC);
+  gpio_set_pin_level(GPIO(GPIO_PORTC, 10), false);
+  gpio_set_pin_direction(GPIO(GPIO_PORTC, 10), GPIO_DIRECTION_OUT);
+  gpio_set_pin_function(GPIO(GPIO_PORTC, 10), GPIO_PIN_FUNCTION_OFF);
+#endif
+
+  // The TPIU is clocked from PCK3 (datasheet 16.7.4) - run it from MCK.
+  // skip if the debugger already started PCK3 (reprogramming glitches the
+  // clock mid-stream and desyncs the decoder)
+  uint32_t const pck3 = PMC_PCK_CSS_MCK | PMC_PCK_PRES(1); // MCK/2 = 75 MHz -> 37.5 MHz pin
+  if (PMC->PMC_PCK[3] != pck3 || !(PMC->PMC_SR & PMC_SR_PCKRDY3)) {
+    PMC->PMC_PCK[3] = pck3;
+    PMC->PMC_SCER = PMC_SCER_PCK3;
+    while (!(PMC->PMC_SR & PMC_SR_PCKRDY3)) {}
+  }
+  _pmc_enable_periph_clock(ID_PIOD);
+  uint32_t const clk_pin = PIO_PD8D_TPIU_TRACECLK;
+  uint32_t const dat_pin = PIO_PD4C_TPIU_TRACED0 | PIO_PD5C_TPIU_TRACED1 |
+                           PIO_PD6C_TPIU_TRACED2 | PIO_PD7C_TPIU_TRACED3;
+  PIOD->PIO_ABCDSR[0] = (PIOD->PIO_ABCDSR[0] | clk_pin) & ~dat_pin; // D=11, C=01
+  PIOD->PIO_ABCDSR[1] |= clk_pin | dat_pin;
+  PIOD->PIO_PDR = clk_pin | dat_pin; // hand the pins to the peripheral
+#endif
+
 #ifdef LED_PIN
   _pmc_enable_periph_clock(LED_PORT_CLOCK);
   gpio_set_pin_level(LED_PIN, LED_STATE_OFF);