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authorhathach <[email protected]>2026-08-17 01:02:22 +0700
committerhathach <[email protected]>2026-08-18 22:07:49 +0700
commit5baf5925c8b6a033de85e3b5537ea879de75e3da (patch)
treeafadd39899510c9982b26ae5b396d04e7946823a /lib/FreeRTOS/Source/include
parenta85a6afc6d98726f5edfb2d7606527c87c963dba (diff)
dcd(ip3511): fix DEVCMDSTAT write-1-to-clear handling and EP0 setup races
DEVCMDSTAT mixes read/write fields with write-1-to-clear latches, so a blind read-modify-write writes a pending latch back as a one and silently clears it - a setup consumed that way strands EP0. Mask the latches on every update. The setup path follows the manual's order: acknowledge the latch, then read the payload. The EP0 IN interrupt is cleared along with EP0 OUT, as the control endpoint flowchart requires - a control IN completion latched before the setup must not reach usbd after it, where it would be applied to the request the setup just started and arm its status stage early. The payload is copied a byte at a time out of a buffer now declared volatile: the controller DMAs a new setup packet into it as soon as the latch is cleared, and C orders volatile accesses only against each other, so gcc sinks a plain memcpy below the guard read that follows at -O2 and -O3 - leaving only -Os, the level CI builds, correct.
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