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authorhathach <[email protected]>2024-11-21 10:15:30 +0700
committerhathach <[email protected]>2024-11-21 10:22:09 +0700
commitfa523a5682d8dc91cc1c7a63475623743e37ac83 (patch)
treebf479ba344d21dff4b6bd761584bc500a188e651 /src/class/cdc
parent2571889061f70b9fd425ee4e4174018bf07c5309 (diff)
make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid
HIL enable device DMA for p4
Diffstat (limited to 'src/class/cdc')
-rw-r--r--src/class/cdc/cdc_device.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index ebc408f5a..3e856383e 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -69,8 +69,14 @@ typedef struct {
OSAL_MUTEX_DEF(tx_ff_mutex);
// Endpoint Transfer buffer
- CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
- CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+ union {
+ CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
+ TUD_DCACHE_PADDING;
+ };
+ union {
+ CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+ TUD_DCACHE_PADDING;
+ };
} cdcd_interface_t;
#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char)