change code style

1 files changed, 235 insertions, 291 deletions

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4f36f7517..05a061487 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -106,7 +106,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 
 static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST };
 enum {
-  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+  FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_pids)
 };
 
 // Store last request baudrate since divisor to baudrate is not easy
@@ -114,7 +114,6 @@ static uint32_t _ftdi_requested_baud;
 
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
-
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -125,12 +124,11 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 
 static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST };
 enum {
-  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+  CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_pids)
 };
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
-
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -141,16 +139,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
 enum {
-  CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
+  CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids)
 };
 
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
-
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 #endif
 
+//------------- Common -------------//
 
 enum {
   SERIAL_DRIVER_ACM = 0,
@@ -204,29 +202,25 @@ static const cdch_serial_driver_t serial_drivers[] = {
 };
 
 enum {
-  SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0])
+  SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers)
 };
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline cdch_interface_t* get_itf(uint8_t idx)
-{
+static inline cdch_interface_t* get_itf(uint8_t idx) {
   TU_ASSERT(idx < CFG_TUH_CDC, NULL);
   cdch_interface_t* p_cdc = &cdch_data[idx];
 
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
     if ( (p_cdc->daddr == daddr) &&
-         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
-    {
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) {
       return i;
     }
   }
@@ -234,14 +228,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
   return TUSB_INDEX_INVALID_8;
 }
 
-
-static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     if (cdch_data[i].daddr == 0) {
       cdch_interface_t* p_cdc = &cdch_data[i];
-
       p_cdc->daddr              = daddr;
       p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
@@ -262,20 +252,16 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
     const cdch_interface_t* p_cdc = &cdch_data[i];
-
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
   return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
-{
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && info);
 
@@ -297,30 +283,26 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
   return true;
 }
 
-bool tuh_cdc_mounted(uint8_t idx)
-{
+bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   return p_cdc != NULL;
 }
 
-bool tuh_cdc_get_dtr(uint8_t idx)
-{
+bool tuh_cdc_get_dtr(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
 
-bool tuh_cdc_get_rts(uint8_t idx)
-{
+bool tuh_cdc_get_rts(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
-bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
-{
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -333,32 +315,28 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
 // Write
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_write_flush(uint8_t idx)
-{
+uint32_t tuh_cdc_write_flush(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
 }
 
-bool tuh_cdc_write_clear(uint8_t idx)
-{
+bool tuh_cdc_write_clear(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_clear(&p_cdc->stream.tx);
 }
 
-uint32_t tuh_cdc_write_available(uint8_t idx)
-{
+uint32_t tuh_cdc_write_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -369,32 +347,28 @@ uint32_t tuh_cdc_write_available(uint8_t idx)
 // Read
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_read_available(uint8_t idx)
-{
+uint32_t tuh_cdc_read_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
-bool tuh_cdc_peek(uint8_t idx, uint8_t* ch)
-{
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
 }
 
-bool tuh_cdc_read_clear (uint8_t idx)
-{
+bool tuh_cdc_read_clear (uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -408,15 +382,13 @@ bool tuh_cdc_read_clear (uint8_t idx)
 //--------------------------------------------------------------------+
 
 // internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer)
-{
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
 
-  if (xfer->result == XFER_RESULT_SUCCESS)
-  {
+  if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
@@ -502,7 +474,6 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_state = (uint8_t) line_state;
     return true;
   }
@@ -526,7 +497,6 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding.bit_rate = baudrate;
     return true;
   }
@@ -552,7 +522,6 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding = *line_coding;
     return true;
   }
@@ -562,31 +531,26 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 // CLASS-USBH API
 //--------------------------------------------------------------------+
 
-void cdch_init(void)
-{
+void cdch_init(void) {
   tu_memclr(cdch_data, sizeof(cdch_data));
 
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
-  {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
 
     tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
-                          p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
-                          p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
 
     tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
-                          p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
-                          p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
 }
 
-void cdch_close(uint8_t daddr)
-{
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
+void cdch_close(uint8_t daddr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
     cdch_interface_t* p_cdc = &cdch_data[idx];
-    if (p_cdc->daddr == daddr)
-    {
+    if (p_cdc->daddr == daddr) {
       TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
 
       // Invoke application callback
@@ -618,16 +582,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
       // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
-  }
-  else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
+  } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
     #if CFG_TUH_CDC_FTDI
     if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
       // FTDI reserve 2 bytes for status
-      // FTDI status
-//      uint8_t status[2] = {
-//        p_cdc->stream.rx.ep_buf[0],
-//        p_cdc->stream.rx.ep_buf[1]
-//      };
+      // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]};
       tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
     }else
     #endif
@@ -653,20 +612,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
-{
-  for(size_t i=0; i<2; i++)
-  {
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) {
+  for (size_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
-              TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
-
+              TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
 
-    if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
       tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
-    }else
-    {
+    } else {
       tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
     }
 
@@ -676,20 +630,17 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co
   return true;
 }
 
-bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   (void) rhport;
 
-  // Only support ACM subclass
+  // For CDC: only support ACM subclass
   // Note: Protocol 0xFF can be RNDIS device
-  if ( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass)
-  {
+  if (TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+      CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
-  {
+  else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
@@ -721,7 +672,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     }
     #endif
   }
-  #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  #endif
 
   return false;
 }
@@ -767,94 +718,85 @@ enum {
   CONFIG_ACM_COMPLETE,
 };
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
+  uint8_t const* p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
+  while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) {
+    if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) {
       // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities;
     }
 
     p_desc = tu_desc_next(p_desc);
   }
 
   // Open notification endpoint of control interface if any
-  if (itf_desc->bNumEndpoints == 1)
-  {
+  if (itf_desc->bNumEndpoints == 1) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
     // next to endpoint descriptor
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
-    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc));
   }
 
   return true;
 }
 
-static void acm_process_config(tuh_xfer_t* xfer)
-{
+static void acm_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc, );
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
 
-  switch(state)
-  {
+  switch (state) {
     case CONFIG_ACM_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
-        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config,
-                                             CONFIG_ACM_SET_LINE_CODING), );
+      if (p_cdc->acm_capability.support_line_request) {
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),);
         break;
       }
-          #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_SET_LINE_CODING:
-        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),);
         break;
       }
-        #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
-      set_config_complete(p_cdc, idx, itf_num+1);
+      set_config_complete(p_cdc, idx, itf_num + 1);
       break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
@@ -987,13 +929,12 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1
   return tuh_control_xfer(&xfer);
 }
 
-static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool
+ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -1001,8 +942,7 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
   return true;
 }
 
-static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
-{
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) {
   const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
   uint32_t divisor;
 
@@ -1022,13 +962,11 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
   return divisor;
 }
 
-static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
-{
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
   return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
 }
 
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
@@ -1055,8 +993,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
+      TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1172,8 +1109,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
@@ -1213,8 +1149,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_SET_DTR_RTS:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1248,8 +1183,7 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
-{
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) {
   // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
   TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
   TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
@@ -1303,23 +1237,19 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
   return false;
 }
 
-static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
 }
 
-static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
 }
 
-static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
 }
 
-static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
 }
 
@@ -1335,8 +1265,7 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u
  */
 // calculate baudrate devisors
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
-{
+static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   uint32_t fact, div, clk_div;
   bool force_fact0 = false;
   int32_t ps;
@@ -1362,20 +1291,19 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
    */
   fact = 1;
   for (ps = 3; ps >= 0; ps--) {
-    if (speed > ch341_min_rates[ps])
-      break;
+    if (speed > ch341_min_rates[ps]) break;
   }
 
-  if (ps < 0)
-    return -EINVAL;
+  if (ps < 0) return -EINVAL;
 
   /* Determine corresponding divisor, rounding down. */
   clk_div = CH341_CLK_DIV(ps, fact);
   div = CH341_CLKRATE / (clk_div * speed);
 
   /* Some devices require a lower base clock if ps < 3. */
-  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
+  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) {
     force_fact0 = true;
+  }
 
   /* Halve base clock (fact = 0) if required. */
   if (div < 9 || div > 255 || force_fact0) {
@@ -1384,16 +1312,16 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
     fact = 0;
   }
 
-  if (div < 2)
-    return -EINVAL;
+  if (div < 2) return -EINVAL;
 
   /*
    * Pick next divisor if resulting rate is closer to the requested one,
    * scale up to avoid rounding errors on low rates.
    */
   if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
-      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
+      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) {
     div++;
+  }
 
   /*
    * Prefer lower base clock (fact = 0) if even divisor.
@@ -1411,16 +1339,13 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
 // set baudrate (low level)
 // do not confuse with ch34x_set_baudrate
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   int val;
 
-  if (!baud_rate)
-    return -EINVAL;
+  if (!baud_rate) return -EINVAL;
 
   val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0)
-    return -EINVAL;
+  if (val < 0) return -EINVAL;
 
   /*
    * CH341A buffers data until a full endpoint-size packet (32 bytes)
@@ -1429,100 +1354,94 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate,
    * At least one device with version 0x27 appears to have this bit
    * inverted.
    */
-  if ( p_cdc->ch34x.version > 0x27 )
+  if ( p_cdc->ch34x.version > 0x27 ) {
     val |= BIT(7);
+  }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
 }
 
 // set lcr register
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * Chip versions before version 0x30 as read using
    * CH341_REQ_READ_VERSION used separate registers for line control
    * (stop bits, parity and word length). Version 0x30 and above use
    * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
    */
-  if ( p_cdc->ch34x.version < 0x30 )
-    return 0;
+  if ( p_cdc->ch34x.version < 0x30 ) return 0;
 
   return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
 }
 
 // set handshake (modem controls)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
 }
 
 // detect quirks (special versions of CH34x)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * A subset of CH34x devices does not support all features. The
    * prescaler is limited and there is no support for sending a RS232
    * break condition. A read failure when trying to set up the latter is
    * used to detect these devices.
    */
-  switch ( step )
-  {
-  case 1:
-    p_cdc->ch34x.quirks = 0;
-    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
-    break;
-  case 2:
-    if ( xfer->result != XFER_RESULT_SUCCESS )
-      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
-    return true;
-    break;
-  default:
-    TU_ASSERT ( false ); // suspicious step
-    break;
+  switch (step) {
+    case 1:
+      p_cdc->ch34x.quirks = 0;
+      return ch341_read_reg_request(p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data);
+      break;
+
+    case 2:
+      if (xfer->result != XFER_RESULT_SUCCESS) {
+        p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
+      }
+      return true;
+      break;
+
+    default:
+      TU_ASSERT (false); // suspicious step
+      break;
   }
 }
 
 // internal control complete to update state such as line state, encoding
 // CH34x needs a special interface recovery due to abnormal wIndex usage
-static void ch34x_control_complete(tuh_xfer_t* xfer)
-{
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
-  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
-  cdch_interface_t  *p_cdc  = get_itf ( idx );
-  TU_ASSERT ( p_cdc, );
-  TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
+static void ch34x_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) ((xfer->user_data & 0xff00) >> 8);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT (p_cdc,);
+  TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,); // ch34x_control_complete is only used for CH34x
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (xfer->setup->bRequest) {
-    case CH341_REQ_WRITE_REG: { // register write request
-      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
-      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
-        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+      case CH341_REQ_WRITE_REG: // register write request
+        switch (tu_le16toh (xfer->setup->wValue)) {
+          case (CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER): // baudrate write
+            p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+            break;
+
+          default:
+            TU_ASSERT(false,); // unexpected register write
+            break;
+        }
         break;
-      }
-      default: {
-        TU_ASSERT(false, ); // unexpected register write
+
+      default:
+        TU_ASSERT(false,); // unexpected request
         break;
-      }
-      }
-      break;
-    }
-    default: {
-      TU_ASSERT(false, ); // unexpected request
-      break;
-    }
     }
     xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb)
-      xfer->complete_cb(xfer);
+    if (xfer->complete_cb) xfer->complete_cb(xfer);
   }
 }
 
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
-{
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) /* do not confuse with ch341_set_baudrate */ {
   TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->ch34x.baud_rate = baudrate;
@@ -1530,15 +1449,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh
   return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
 }
 
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
   // todo later
   return false;
 }
 
-static void ch34x_process_config ( tuh_xfer_t* xfer )
-{
+static void ch34x_process_config ( tuh_xfer_t* xfer ) {
   uintptr_t const   state   = xfer->user_data & 0xff;
   // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
   uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
@@ -1561,81 +1478,108 @@ static void ch34x_process_config ( tuh_xfer_t* xfer )
      */
     p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
   }
+
   // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
-  switch ( state ) {
-  case CONFIG_CH34X_STEP1: // request version read
-    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
-    break;
-  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
-    p_cdc->ch34x.version = xfer->buffer[0];
-    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
-    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
-    break;
-  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
-    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
-    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP6: // detect quirks step 1
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
-    break;
-  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
-    switch ( line_coding.data_bits ) {
-    case 5:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+  switch (state) {
+    case CONFIG_CH34X_STEP1: // request version read
+      TU_ASSERT (ch341_control_in(p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */0,
+                                  buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2),);
       break;
-    case 6:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+
+    case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
+      p_cdc->ch34x.version = xfer->buffer[0];
+      TU_LOG_DRV ("Chip version=%02x\r\n", p_cdc->ch34x.version);
+      TU_ASSERT (ch341_control_out(p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */0,
+                                   ch34x_process_config, CONFIG_CH34X_STEP3),);
       break;
-    case 7:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+
+    case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
+      TU_ASSERT (ch341_set_baudrate(p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config,
+                                    CONFIG_CH34X_STEP4) > 0,);
       break;
-    case 8:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+
+    case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5) > 0,);
       break;
-    default:
-      TU_ASSERT ( false, ); // not supported data_bits
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+
+    case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
+      TU_ASSERT (ch341_set_handshake(p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6) > 0,);
       break;
-    }
-    if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
-      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
-    }
-    TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
-    if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
-      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
+
+    case CONFIG_CH34X_STEP6: // detect quirks step 1
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE,
+                                     ch34x_process_config, CONFIG_CH34X_STEP7) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0) > 0,);
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      TU_ASSERT (ch34x_set_baudrate(p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8),);
+#else
+      TU_ATTR_FALLTHROUGH;
+#endif
+      break;
+
+    case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+      switch (line_coding.data_bits) {
+        case 5:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+          break;
+
+        case 6:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+          break;
+
+        case 7:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+          break;
+
+        case 8:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+
+        default:
+          TU_ASSERT (false,); // not supported data_bits
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+      }
+
+      if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
+        p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+        }
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+        }
+      }
+      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
+                                                                         CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
+      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+        p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
+      }
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE) > 0,);
 #else
-    TU_ATTR_FALLTHROUGH;
+      TU_ATTR_FALLTHROUGH;
 #endif
-    break;
+      break;
+
     case CONFIG_CH34X_COMPLETE:
-      set_config_complete ( p_cdc, idx, itf_num );
+      set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
-      TU_ASSERT ( false, );
+      TU_ASSERT (false,);
       break;
   }
 }
 
 #endif // CFG_TUH_CDC_CH34X
 
-#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
+#endif