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authorhathach <[email protected]>2024-07-12 20:17:14 +0700
committerhathach <[email protected]>2024-07-12 20:17:14 +0700
commit4ce1cce40a01dce56cab2c73745f4f2c9d212b25 (patch)
treebb2c79e5e5204f7d3f539c4c25a47b82560ed2fe /src/common/tusb_mcu.h
parentb97520e89f500bfa7972d7fce973f20185512006 (diff)
simplify dwc2 test mode
- all dwc2 ip seems to support test mode in both fs/hs -> remove TUP_USBIP_DWC2_TEST_MODE - remove dcd_check_test_mode_support(), all should be supported - move enum tusb_feature_test_mode_t to tusb_types.h
Diffstat (limited to 'src/common/tusb_mcu.h')
-rw-r--r--src/common/tusb_mcu.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 80826c895..637281bfc 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -195,7 +195,6 @@
#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
- #define TUP_USBIP_DWC2_TEST_MODE
// For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
#define TUP_DCD_ENDPOINT_MAX 6
@@ -210,7 +209,6 @@
// MCU with on-chip HS Phy
#if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
- #define TUP_USBIP_DWC2_TEST_MODE
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -285,7 +283,6 @@
defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
#define TUP_DCD_ENDPOINT_MAX 9
#define TUP_RHPORT_HIGHSPEED 1
- #define TUP_USBIP_DWC2_TEST_MODE
#else
#define TUP_DCD_ENDPOINT_MAX 6
#endif