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| author | Zixun LI <[email protected]> | 2025-12-26 18:15:26 +0100 |
|---|---|---|
| committer | GitHub <[email protected]> | 2025-12-26 18:15:26 +0100 |
| commit | 3eafddb02a3347873dc1816f53b428518eb97c61 (patch) | |
| tree | 84482370893feae4f9e0a39e98d9cd7e04b005fc /src/common | |
| parent | b209b177ecc41ca733a4420c60fb7c1170be2342 (diff) | |
| parent | d77f1e8eb6f53cdb55987165b36e301daf1f9828 (diff) | |
Merge pull request #3433 from Precidata/fix-compilation-v2
Fix compilation v2
Diffstat (limited to 'src/common')
| -rw-r--r-- | src/common/tusb_mcu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 55f7e0b7c..ebe486e40 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -245,13 +245,12 @@ #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #elif TU_CHECK_MCU(OPT_MCU_STM32H7) - #include "stm32h7xx.h" #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 9 - #if __CORTEX_M == 7 + #ifndef CORE_CM4 // Enable dcache if DMA is enabled #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE |