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authorzhiqiang <[email protected]>2025-07-07 14:13:15 +0800
committerzhiqiang <[email protected]>2025-07-07 14:13:15 +0800
commit73bf9aeaa6e1ffd453b7bffa4dd3818773e6a763 (patch)
tree2ced76d8c5d9b0475c0bc7323127ed20883202cc /src/common
parentb012e95dfe40c6cd73cde7a6917848c4131dc548 (diff)
support at32 mcu
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_mcu.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index a08ed79c8..41c291600 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -550,6 +550,44 @@
#define TUP_RHPORT_HIGHSPEED 1
#define TUD_ENDPOINT_ONE_DIRECTION_ONLY
+//--------------------------------------------------------------------+
+// ArteryTek
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F413)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F415)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 4
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
#endif
//--------------------------------------------------------------------+