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authorCédric Berger <[email protected]>2026-02-22 21:39:14 +0100
committerGitHub <[email protected]>2026-02-22 21:39:14 +0100
commit942479407e3bfb4e0800aeb428dc2a3d03d77ded (patch)
treef6f65d88bfe1789f06c1d788994bb73f4871cc5f /src/common
parent90d0514630d9b0f6d50881aabd82dcd613141f6b (diff)
parentdc072da5cc6a6b326a832f104c0a395d119ce35c (diff)
Merge branch 'hathach:master' into non-blocking-host-v2
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_verify.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index c9e06361c..bd00b9d11 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -73,8 +73,13 @@
#define TU_MESS_FAILED() do {} while (0)
#endif
+// Custom defined application function
+#ifdef CFG_TUSB_DEBUG_BREAKPOINT
+ extern void CFG_TUSB_DEBUG_BREAKPOINT(void);
+ #define TU_BREAKPOINT() CFG_TUSB_DEBUG_BREAKPOINT()
+
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define TU_BREAKPOINT() do { \
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \