diff options
| author | YixingShen <[email protected]> | 2023-12-28 00:28:24 +0800 |
|---|---|---|
| committer | YixingShen <[email protected]> | 2023-12-28 00:28:24 +0800 |
| commit | 9a1559a35653e34c2fc8b4dccdc9f40ad476913c (patch) | |
| tree | 1e940673c1f060bb943656a3e7f8bfd552ef8b19 /src/common | |
| parent | 1117880411094b9bd442a1178dc1190b79845541 (diff) | |
add __ARM_ARCH_8_1M_MAIN__ for M55
Diffstat (limited to 'src/common')
| -rw-r--r-- | src/common/tusb_verify.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 1b5f53dfc..8aa66b4df 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -75,8 +75,8 @@ #define _MESS_FAILED() do {} while (0) #endif -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) #define TU_BREAKPOINT() do \ { \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ |