summaryrefslogtreecommitdiff
path: root/src/common
diff options
context:
space:
mode:
authorHa Thach <[email protected]>2025-08-01 10:39:47 +0700
committerGitHub <[email protected]>2025-08-01 10:39:47 +0700
commita16c7a27e44990e4025f7d169344eb4a6cf2a377 (patch)
treef6725f3ab347c9f0e50526b15658caa0f3d7719d /src/common
parentde9a6c8561e439c397bbb44cc053701a76d9988d (diff)
parente0f2343954c71743358f2b2362bef64bbc68e4a3 (diff)
Merge pull request #3191 from hathach/at32
support at32 mcu (2)
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_mcu.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 4b987cbaf..a91759b84 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -568,6 +568,44 @@
#define TUP_RHPORT_HIGHSPEED 1
#define TUD_ENDPOINT_ONE_DIRECTION_ONLY
+//--------------------------------------------------------------------+
+// ArteryTek
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F413)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F415)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 4
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_AT32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
#endif
//--------------------------------------------------------------------+