Merge remote-tracking branch 'tinyusb/master' into dwc2_deinit

Signed-off-by: HiFiPhile <[email protected]>

5 files changed, 65 insertions, 45 deletions

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a92435912..9f188f296 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -33,7 +33,7 @@
 // Suppress IAR warning
 // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
 #if defined(__ICCARM__)
-#pragma diag_suppress = Pa082
+  #pragma diag_suppress = Pa082
 #endif
 
 #if OSAL_MUTEX_REQUIRED
@@ -110,8 +110,9 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
 }
 
 //--------------------------------------------------------------------+
-// Pull & Push
-// copy data to/from fifo without updating read/write pointers
+// Hardware FIFO API
+// Support different data access width and address increment scheme
+// Can support multiple i.e both 16 and 32-bit data access if needed
 //--------------------------------------------------------------------+
 #if CFG_TUSB_FIFO_HWFIFO_API
   #if CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE
@@ -122,18 +123,31 @@ void tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) {
 
   #define HWFIFO_ADDR_NEXT(_hwfifo, _const) HWFIFO_ADDR_NEXT_N(_hwfifo, _const, CFG_TUSB_FIFO_HWFIFO_ADDR_STRIDE)
 
+//------------- Write -------------//
   #ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_WRITE
-static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
+TU_ATTR_ALWAYS_INLINE static inline void stride_write(volatile void *hwfifo, const void *src, uint8_t data_stride) {
+  (void)data_stride; // possible unused
     #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
-  if (data_stride == 4) {
+      #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
+  if (data_stride == 4)
+      #endif
+  {
     *((volatile uint32_t *)hwfifo) = tu_unaligned_read32(src);
   }
-  #endif
-  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
-  if (data_stride == 2) {
+    #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 2
+      #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 2
+  if (data_stride == 2)
+      #endif
+  {
     *((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
   }
-  #endif
+    #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+  *((volatile uint8_t *)hwfifo) = *(const uint8_t *)src;
+    #endif
 }
 
 // Copy from fifo to fixed address buffer (usually a tx register) with TU_FIFO_FIXED_ADDR_RW32 mode
@@ -147,7 +161,8 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, );
   }
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
   // 16-bit access is allowed for odd bytes
   if (len >= 2) {
     *((volatile uint16_t *)hwfifo) = tu_unaligned_read16(src);
@@ -155,16 +170,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     len -= 2;
     HWFIFO_ADDR_NEXT_N(hwfifo, , 2);
   }
-    #endif
+      #endif
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_8BIT_ACCESS
   // 8-bit access is allowed for odd bytes
   while (len > 0) {
     *((volatile uint8_t *)hwfifo) = *src++;
     len--;
     HWFIFO_ADDR_NEXT_N(hwfifo, , 1);
   }
-    #else
+      #else
 
   // Write odd bytes i.e 1 byte for 16 bit or 1-3 bytes for 32 bit
   if (len > 0) {
@@ -173,13 +188,16 @@ void tu_hwfifo_write(volatile void *hwfifo, const uint8_t *src, uint16_t len, co
     stride_write(hwfifo, &tmp, data_stride);
     HWFIFO_ADDR_NEXT(hwfifo, );
   }
+      #endif
     #endif
 }
   #endif
 
+//------------- Read -------------//
   #ifndef CFG_TUSB_FIFO_HWFIFO_CUSTOM_READ
-static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
+TU_ATTR_ALWAYS_INLINE static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t data_stride) {
   (void)data_stride; // possible unused
+
     #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE & 4
       #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE != 4
   if (data_stride == 4)
@@ -197,6 +215,10 @@ static inline void stride_read(const volatile void *hwfifo, void *dest, uint8_t
     tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
   }
     #endif
+
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+  *(uint8_t *)dest = *((const volatile uint8_t *)hwfifo);
+    #endif
 }
 
 void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, const tu_hwfifo_access_t *access_mode) {
@@ -209,7 +231,8 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, const);
   }
 
-    #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
+    #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE > 1
+      #ifdef CFG_TUSB_FIFO_HWFIFO_DATA_ODD_16BIT_ACCESS
   // 16-bit access is allowed for odd bytes
   if (len >= 2) {
     tu_unaligned_write16(dest, *((const volatile uint16_t *)hwfifo));
@@ -235,6 +258,7 @@ void tu_hwfifo_read(const volatile void *hwfifo, uint8_t *dest, uint16_t len, co
     HWFIFO_ADDR_NEXT(hwfifo, const);
   }
     #endif
+    #endif
 }
   #endif
 
@@ -251,7 +275,11 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
     tu_hwfifo_read(hwfifo, ff_buf, n, access_mode);
   } else {
     // Wrap around case
-
+  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+    tu_hwfifo_read(hwfifo, ff_buf, lin_bytes, access_mode);     // linear part
+    HWFIFO_ADDR_NEXT_N(hwfifo, const, lin_bytes);
+    tu_hwfifo_read(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
+  #else
     // Write full words to linear part of buffer
     const uint8_t  data_stride = access_mode->data_stride;
     const uint32_t odd_mask    = data_stride - 1;
@@ -286,6 +314,7 @@ static void hwff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uin
     if (wrap_bytes > 0) {
       tu_hwfifo_read(hwfifo, ff_buf, wrap_bytes, access_mode);
     }
+  #endif
   }
 }
 
@@ -303,11 +332,15 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
     tu_hwfifo_write(hwfifo, ff_buf, n, access_mode);
   } else {
     // Wrap around case
-
+  #if CFG_TUSB_FIFO_HWFIFO_DATA_STRIDE == 1
+    tu_hwfifo_write(hwfifo, ff_buf, lin_bytes, access_mode);     // linear part
+    HWFIFO_ADDR_NEXT_N(hwfifo, , lin_bytes);
+    tu_hwfifo_write(hwfifo, f->buffer, wrap_bytes, access_mode); // wrapped part
+  #else
     // Read full words from linear part
     const uint8_t  data_stride = access_mode->data_stride;
     const uint32_t odd_mask    = data_stride - 1;
-    uint16_t       lin_even = lin_bytes & ~odd_mask;
+    uint16_t       lin_even    = lin_bytes & ~odd_mask;
     tu_hwfifo_write(hwfifo, ff_buf, lin_even, access_mode);
     HWFIFO_ADDR_NEXT_N(hwfifo, , lin_even);
     ff_buf += lin_even;
@@ -338,10 +371,15 @@ static void hwff_pull_n(const tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t
     if (wrap_bytes > 0) {
       tu_hwfifo_write(hwfifo, ff_buf, wrap_bytes, access_mode);
     }
+  #endif
   }
 }
 #endif
 
+//--------------------------------------------------------------------+
+// Pull & Push
+// copy data to/from fifo without updating read/write pointers
+//--------------------------------------------------------------------+
 // send n items to fifo WITHOUT updating write pointer
 static void ff_push_n(const tu_fifo_t *f, const void *app_buf, uint16_t n, uint16_t wr_ptr) {
   uint16_t lin_bytes  = f->depth - wr_ptr;
@@ -787,6 +825,6 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) {
   } else {
     info->linear.len  = f->depth - wr_ptr;
     info->wrapped.len = remain - info->linear.len; // Remaining length - n already was limited to remain or FIFO depth
-    info->wrapped.ptr = f->buffer;              // Always start of buffer
+    info->wrapped.ptr = f->buffer;                 // Always start of buffer
   }
 }
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1a4e517b7..5b9497b9a 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -635,17 +635,7 @@
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 4
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F423)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
-#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405)
+#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405, OPT_MCU_AT32F423, OPT_MCU_AT32F425, OPT_MCU_AT32F435_437, OPT_MCU_AT32F45X)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_AT32
   #define TUP_DCD_ENDPOINT_MAX 8
@@ -657,11 +647,6 @@
     #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
   #endif
 
-#elif TU_CHECK_MCU(OPT_MCU_AT32F425)
-  #define TUP_USBIP_DWC2
-  #define TUP_USBIP_DWC2_AT32
-  #define TUP_DCD_ENDPOINT_MAX 8
-
 //--------------------------------------------------------------------+
 // HPMicro
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index 10e12c2af..43ce7a1df 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -37,14 +37,6 @@
 // Configuration
 //--------------------------------------------------------------------+
 
-#if CFG_TUD_ENABLED && CFG_TUD_VENDOR && (CFG_TUD_VENDOR_TX_BUFSIZE == 0 || CFG_TUD_VENDOR_RX_BUFSIZE == 0)
-  #define CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED 1
-#endif
-
-#ifndef CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED
-  #define CFG_TUSB_EDPT_STREAM_NO_FIFO_ENABLED 0
-#endif
-
 #define TUP_USBIP_CONTROLLER_NUM 2
 extern tusb_role_t _tusb_rhport_role[TUP_USBIP_CONTROLLER_NUM];
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index d473e53e6..7d26ac74e 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -554,7 +554,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) {
-  return (uint8_t) (num | (dir == TUSB_DIR_IN ? TUSB_DIR_IN_MASK : 0u));
+  return (uint8_t) (num | (dir == (uint8_t)TUSB_DIR_IN ? (uint8_t)TUSB_DIR_IN_MASK : 0u));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index c9e06361c..bd00b9d11 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -73,8 +73,13 @@
   #define TU_MESS_FAILED() do {} while (0)
 #endif
 
+// Custom defined application function
+#ifdef CFG_TUSB_DEBUG_BREAKPOINT
+  extern void CFG_TUSB_DEBUG_BREAKPOINT(void);
+  #define TU_BREAKPOINT() CFG_TUSB_DEBUG_BREAKPOINT()
+
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+#elif defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
     defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
   #define TU_BREAKPOINT() do {                                                                              \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \