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authorHiFiPhile <[email protected]>2024-07-28 11:59:52 +0200
committerHiFiPhile <[email protected]>2024-07-28 11:59:52 +0200
commitf48a4567a6f97c6f814ad6cd3de544bcce42e585 (patch)
tree2b5e4d18f4d1ac827f97531db6729ecb13583189 /src/common
parentb0f5422262a26fb1ab496e33bb8009efb6660788 (diff)
parentcfbdc44a8d099240ad5ef208bd639487c2f28153 (diff)
Merge branch 'master' of https://github.com/hathach/tinyusb into rx_fb
Diffstat (limited to 'src/common')
-rw-r--r--src/common/tusb_mcu.h35
-rw-r--r--src/common/tusb_types.h9
-rw-r--r--src/common/tusb_verify.h10
3 files changed, 38 insertions, 16 deletions
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index c66996c4f..637281bfc 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -195,7 +195,6 @@
#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_STM32
- #define TUP_USBIP_DWC2_TEST_MODE
// For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
#define TUP_DCD_ENDPOINT_MAX 6
@@ -210,7 +209,6 @@
// MCU with on-chip HS Phy
#if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
#define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS
- #define TUP_USBIP_DWC2_TEST_MODE
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -271,17 +269,23 @@
#define TUP_DCD_ENDPOINT_MAX 8
#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
- #define TUP_USBIP_DWC2
- #define TUP_USBIP_DWC2_STM32
+ #if defined (STM32U535xx) || defined (STM32U545xx)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_STM32
+ #define TUP_DCD_ENDPOINT_MAX 8
- // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
- #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
- defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
- #define TUP_DCD_ENDPOINT_MAX 9
- #define TUP_RHPORT_HIGHSPEED 1
- #define TUP_USBIP_DWC2_TEST_MODE
#else
- #define TUP_DCD_ENDPOINT_MAX 6
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_STM32
+
+ // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+ #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
+ defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
+ #define TUP_DCD_ENDPOINT_MAX 9
+ #define TUP_RHPORT_HIGHSPEED 1
+ #else
+ #define TUP_DCD_ENDPOINT_MAX 6
+ #endif
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
@@ -420,6 +424,15 @@
#define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS
#define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
+#elif TU_CHECK_MCU(OPT_MCU_CH32V103)
+ #define TUP_USBIP_WCH_USBFS
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+ #define CFG_TUD_WCH_USBIP_USBFS 1
+ #endif
+
+ #define TUP_DCD_ENDPOINT_MAX 8
+
#elif TU_CHECK_MCU(OPT_MCU_CH32V20X)
// v20x support both FSDEV (USBD) and USBFS, default to FSDEV
#define TUP_USBIP_WCH_USBFS
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index b571f9b72..1501a5af6 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -214,6 +214,15 @@ enum {
#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2)
+// USB 2.0 Spec Table 9-7: Test Mode Selectors
+typedef enum {
+ TUSB_FEATURE_TEST_J = 1,
+ TUSB_FEATURE_TEST_K,
+ TUSB_FEATURE_TEST_SE0_NAK,
+ TUSB_FEATURE_TEST_PACKET,
+ TUSB_FEATURE_TEST_FORCE_ENABLE,
+} tusb_feature_test_mode_t;
+
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index dde0550d3..4344575b7 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -56,8 +56,8 @@
* #define TU_VERIFY(cond) if(cond) return false;
* #define TU_VERIFY(cond,ret) if(cond) return ret;
*
- * #define TU_ASSERT(cond) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
- * #define TU_ASSERT(cond,ret) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
+ * #define TU_ASSERT(cond) if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return false;}
+ * #define TU_ASSERT(cond,ret) if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
*------------------------------------------------------------------*/
#ifdef __cplusplus
@@ -70,9 +70,9 @@
#if CFG_TUSB_DEBUG
#include <stdio.h>
- #define _MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
+ #define TU_MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
#else
- #define _MESS_FAILED() do {} while (0)
+ #define TU_MESS_FAILED() do {} while (0)
#endif
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
@@ -119,7 +119,7 @@
*------------------------------------------------------------------*/
#define TU_ASSERT_DEFINE(_cond, _ret) \
do { \
- if ( !(_cond) ) { _MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
+ if ( !(_cond) ) { TU_MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
} while(0)
#define TU_ASSERT_1ARGS(_cond) TU_ASSERT_DEFINE(_cond, false)