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| author | Ha Thach <[email protected]> | 2024-04-25 12:31:14 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-04-25 12:31:14 +0700 |
| commit | fc91e15488523548b6eafa63a3cb6190c1ba72d8 (patch) | |
| tree | 0ab7c22b1facc83e740844d54651c790fc438b6a /src/common | |
| parent | c237d18ef5c6f5ca6ad625a3b22bdaaaa1df55e8 (diff) | |
| parent | c2f836279e88d15c2dd818f44f3c563071f36bca (diff) | |
Merge pull request #2607 from HiFiPhile/dwc2_fix
Some misc fixes
Diffstat (limited to 'src/common')
| -rw-r--r-- | src/common/tusb_verify.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 8aa66b4df..71406dacf 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -76,7 +76,8 @@ #endif // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ + defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define TU_BREAKPOINT() do \ { \ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ |