diff options
| author | hathach <[email protected]> | 2020-05-19 00:55:43 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2020-05-19 00:55:43 +0700 |
| commit | 58cedf4c061fbf9f95cd88cafb6e581fc04549ff (patch) | |
| tree | 3a8d0855fd69d45501750c93ff8072c17d575b3e /src/host/ehci | |
| parent | 905a80d1b2de5e8ad67b3687ffd0543d90ac904e (diff) | |
usb0 host on mcb1800 work with fullspeed mode.
use usbh_edpt_open() to correctly map ep2drv[]
Diffstat (limited to 'src/host/ehci')
| -rw-r--r-- | src/host/ehci/ehci.c | 21 | ||||
| -rw-r--r-- | src/host/ehci/ehci.h | 4 |
2 files changed, 23 insertions, 2 deletions
diff --git a/src/host/ehci/ehci.c b/src/host/ehci/ehci.c index 048affb1e..e2ead7b08 100644 --- a/src/host/ehci/ehci.c +++ b/src/host/ehci/ehci.c @@ -120,10 +120,27 @@ void hcd_port_reset(uint8_t rhport) ehci_registers_t* regs = ehci_data.regs; - regs->portsc_bm.port_enabled = 0; // disable port before reset - regs->portsc_bm.port_reset = 1; +// regs->portsc_bm.port_enabled = 0; // disable port before reset +// regs->portsc_bm.port_reset = 1; + + uint32_t portsc = regs->portsc; + + portsc &= ~(EHCI_PORTSC_MASK_PORT_EANBLED); + portsc |= EHCI_PORTSC_MASK_PORT_RESET; + + regs->portsc = portsc; } +#if 0 +void hcd_port_reset_end(uint8_t rhport) +{ + (void) rhport; + + ehci_registers_t* regs = ehci_data.regs; + regs->portsc_bm.port_reset = 0; +} +#endif + bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; diff --git a/src/host/ehci/ehci.h b/src/host/ehci/ehci.h index f11c4536a..a6342b2d2 100644 --- a/src/host/ehci/ehci.h +++ b/src/host/ehci/ehci.h @@ -311,10 +311,14 @@ enum ehci_usbcmd_pos_ { }; enum ehci_portsc_change_mask_{ + EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0), EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1), + EHCI_PORTSC_MASK_PORT_EANBLED = TU_BIT(2), EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3), EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5), + EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8), + EHCI_PORTSC_MASK_ALL = EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE | EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE | |