diff options
| author | HiFiPhile <[email protected]> | 2024-11-30 18:05:04 +0100 |
|---|---|---|
| committer | HiFiPhile <[email protected]> | 2024-11-30 18:05:04 +0100 |
| commit | c41d9db3b1cf23b10b755b55a231fc9b1a7dd147 (patch) | |
| tree | cfd006e9a2b6b3cb82a1c8c9f96a6671d5cf7cbb /src/host/hcd.h | |
| parent | 486e14ea9b66432396089367e61a0480bbb960a9 (diff) | |
| parent | 2179fb1bd93b71d755c4bf212aff7094f5e8337d (diff) | |
Merge branch 'master' into rt1170
Signed-off-by: HiFiPhile <[email protected]>
Diffstat (limited to 'src/host/hcd.h')
| -rw-r--r-- | src/host/hcd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h index 6518e6fd2..56b6fdb5d 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -103,15 +103,15 @@ typedef struct { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API |
