diff options
| author | Ha Thach <[email protected]> | 2023-07-24 21:36:15 +0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-07-24 21:36:15 +0700 |
| commit | 0b38941362b6ff2fe3fb7aba1507e82798cd9c16 (patch) | |
| tree | 3a0884e47d9d92c9701b8104f4185b0ebb03821a /src/host | |
| parent | d685ac689bebf778bbf401ff06ba513cee02182c (diff) | |
| parent | fd29fd923a0a64be96fe4bdfa2a5fa9f184ea6c7 (diff) | |
Merge pull request #2173 from hathach/imxrt-dcache-align
change dcache clean/invalidate return type to bool
Diffstat (limited to 'src/host')
| -rw-r--r-- | src/host/hcd.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h index 3355c18b2..a98286053 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -110,15 +110,15 @@ typedef struct // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; //--------------------------------------------------------------------+ // Controller API |
