diff options
| author | hathach <[email protected]> | 2022-04-01 16:01:24 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2022-04-01 16:01:24 +0700 |
| commit | 75bca96bc630b98723c9f4bbb4958dac22ac594d (patch) | |
| tree | 912526cde9affbd675f449ccbd9fa85eecf4275e /src/host | |
| parent | e94d11a5b39cae08f39722eaa5f6ac4d527a329b (diff) | |
pio usb control work well including stall response
Diffstat (limited to 'src/host')
| -rw-r--r-- | src/host/hcd.h | 4 | ||||
| -rw-r--r-- | src/host/usbh.c | 16 |
2 files changed, 5 insertions, 15 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h index 0e18351fc..9b41f2447 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -153,10 +153,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]); -// Optional: some controllers are capable of carry out the whole Control Transfer (setup, data, status) -// without help of USBH. -bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data) TU_ATTR_WEAK; - // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr); diff --git a/src/host/usbh.c b/src/host/usbh.c index b388a4c08..520ef4c7d 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -543,19 +543,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) const uint8_t rhport = usbh_get_rhport(daddr); TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request"); - TU_LOG2_VAR(&xfer->setup); + TU_LOG2_VAR(xfer->setup); TU_LOG2("\r\n"); if (xfer->complete_cb) { - if ( hcd_edpt_control_xfer ) - { - _ctrl_xfer.stage = CONTROL_STAGE_ACK; - TU_ASSERT( hcd_edpt_control_xfer(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request, _ctrl_xfer.buffer) ); - }else - { - TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); - } + TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); }else { // blocking if complete callback is not provided @@ -643,7 +636,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result { // DATA stage: initial data toggle is always 1 _set_control_xfer_stage(CONTROL_STAGE_DATA); - return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength); + TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) ); + return true; } __attribute__((fallthrough)); @@ -658,7 +652,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result // ACK stage: toggle is always 1 _set_control_xfer_stage(CONTROL_STAGE_ACK); - hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0); + TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0) ); break; case CONTROL_STAGE_ACK: |
