diff options
| author | hathach <[email protected]> | 2023-05-18 10:04:48 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2023-05-18 10:04:48 +0700 |
| commit | a3e017bfd2923dcb1ce86d395606a24e2285e54a (patch) | |
| tree | 2c07175cf4bc4ff15dd71fe14cb1c2ee4b0e6c8c /src/host | |
| parent | eb89df411540cb8cf5323991516a45590fa0b81d (diff) | |
EHCI adding dcahe support, passing enumertaion
Diffstat (limited to 'src/host')
| -rw-r--r-- | src/host/hcd.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h index 38c89a1d2..c6fde2adc 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -108,12 +108,18 @@ typedef struct // Memory API //--------------------------------------------------------------------+ -// clean/flush data cache: write cache -> memory +// clean/flush data cache: write cache -> memory. +// Required before an DMA TX transfer to make sure data is in memory void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory +// Required BOTH before and after an DMA RX transfer void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; +// clean and invalidate data cache +// Required before an DMA transfer where memory is both read/write by DMA +void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -194,6 +200,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr) event.event_id = HCD_EVENT_DEVICE_ATTACH; event.connection.hub_addr = 0; event.connection.hub_port = 0; + hcd_event_handler(&event, in_isr); } @@ -224,7 +231,6 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred event.xfer_complete.result = result; event.xfer_complete.len = xferred_bytes; - hcd_event_handler(&event, in_isr); } |
