diff options
| author | hathach <[email protected]> | 2023-07-24 17:54:24 +0700 |
|---|---|---|
| committer | hathach <[email protected]> | 2023-07-24 17:54:24 +0700 |
| commit | d2542560470de242dd8988d0b3c10d7df0496bb0 (patch) | |
| tree | 2420165dd05796e9ced75f13a35aeda46c305b4f /src/host | |
| parent | 8fa0b74d8016554d23f84981f78c656f215d76e8 (diff) | |
change dcache clean/invalidate return type to bool
add tu_assert() check for aligned 32byte address for imxrt
Diffstat (limited to 'src/host')
| -rw-r--r-- | src/host/hcd.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/host/hcd.h b/src/host/hcd.h index 3355c18b2..52fcc834e 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -104,21 +104,21 @@ typedef struct uint8_t speed; } hcd_devtree_info_t; -//--------------------------------------------------------------------+ +//-------------------------------------------------------------- // Memory API //--------------------------------------------------------------------+ // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; //--------------------------------------------------------------------+ // Controller API |
